Download ECE - 703 - NIT Arunachal Pradesh

NATIONAL INSTITUTE OF TECHNOLOGY, ARUNACHAL PRADESH, YUPIA, Pin-791112
(Established by MHRD, Govt. of India)
Website : www.nitap.in, Fax No: (0360) 2284972
E-Mail: [email protected] / [email protected]
Exercises Proposed for teaching in (July – December, 2016 Semester)
1. Name of the Teacher : Abir Jyoti Mondal
2. Department
: Electronics & Communication Engineering
3. Course Title
: VLSI Design
4. Course code
: ECE 703
5. Course Hands out (in reference to framed & approved syllabus) (maximum 500 words)
Unit
I
II
III
IV
Topics
MOS inverters, CMOS inverters, state characteristics, switching
characteristics, power dissipation issues, CMOS logic gates: NAND,
NOR, XOR, CMOS logic design of half and full adders. CMOS
transmission gates, pseudo-nMOS, domino logic gates, Sequential MOS
Logic Circuit: The SR latch circuit, clocked latch and flip-flop, CMOS
D-latch and edge-triggered circuits, Schmitt trigger circuit, Comparator,
Dynamic Logic Circuit: Pass transistor logic, synchronous dynamic
circuit techniques, Semiconductor Memories: ROM circuit, SRAM
circuits, DRAM circuits, drivers and buffers, Buffer scaling and design
issues
Review of MOSFET characteristics, scaling and small-geometry effects,
MOSFET capacitance, .MOS resistor, MOS current source, current
mirror circuits. MOS voltage source linear voltage and current
converters, CMOS operational amplifier (OPAMP) design: Differential
amplifier, level shifter, source follower, output stage voltage and power
amplifiers. Cascaded OPAMP. Compensation techniques.
Stick diagram, λ-rule, conversion circuit to stick diagrams and stick
diagrams to layout. Analog Filters: Switched capacitor (SC)
fundamentals, first order SC circuits, second-order SC circuit and
cascade design Analog to digital and digital to analog converters, speed
of conversion and over sampling issues, VLSI Interconnects: distributed
RC model, transmission line model. Future inter connect technologies.
SPICE : Element lines, Control lines, Command lines, Types of
analysis, Models and model parameters, Sub circuits and Macros,
Layout design rules, Layout of inverters, NAND, NOR gates using
LASI, VHDL Syntax: Basic concepts in VHDL/Verilog and VHDL
Classes
10
10
10
10
NATIONAL INSTITUTE OF TECHNOLOGY, ARUNACHAL PRADESH, YUPIA, Pin-791112
(Established by MHRD, Govt. of India)
Website : www.nitap.in, Fax No: (0360) 2284972
E-Mail: [email protected] / [email protected]
grammar, Structural specification, VHDL description of Inverter,
NAND gate, Full adder.
6. Books/Literature to be followed:
(a) Books (Min. 2 texts + 3 references)
(i)
Title
Microelectronics Circuits: Theory and applications
Author
Adel S Sedra and Kenneth C Smith
Publisher
Oxford
Edition
6th
(ii)
Title
CMOS VLSI Design: A circuits and Systems Perspective
Author
Neil H E Weste, David Harris and Ayan Banerjee
Publisher
Pearson
Edition
3rd
(iii) Title
CMOS Digital Integrated Circuits Analysis and Design
Author
Sung Mo Kang and Yusuf Leblebici
Publisher
McGraw Hill
Edition
3rd
(iv)
Title
Design of Analog CMOS Integrated Circuits
Author
Behzad Razavi
Publisher
Tata McGraw Hill
Edition
2nd
(b) Magazines/Journals (Minimum 5)
(i) IEEE Solid State Circuits Society Newsletter
(ii) Springer
(iii)Electronics Letter
(iv) IEEE Magazines on Semiconductor Manufacturing
(v) IEEE Magazines on Consumer Electronics
7. Mode of Teaching: J.C Bose/S. N. Bose (please tick).
J.C. Bose Model
8. If the course is of practices, list the experiments to be offered.
(i)
N-MOS and P-MOS transistors are taken from library and appropriate voltages is
applied at gate and drain terminals to obtain the desired current versus voltage
waveforms.
(ii)
A CMOS inverter is designed using n-MOS and p-MOS transistors and an appropriate
voltage is applied at the input to verify the inverter operation.
NATIONAL INSTITUTE OF TECHNOLOGY, ARUNACHAL PRADESH, YUPIA, Pin-791112
(Established by MHRD, Govt. of India)
Website : www.nitap.in, Fax No: (0360) 2284972
E-Mail: [email protected] / [email protected]
(iii)
NAND and AND gates are designed using MOS transistors and an appropriate input is
applied to verify the corresponding logic.
(iv)
NOR and OR gates are designed using MOS transistors and an appropriate input is
applied to verify the corresponding logic.
(v)
XOR and XNOR gates are designed using MOS transistors and an appropriate input is
applied to verify the corresponding logic.
(vi)
Half adder and Full adder are designed using MOS transistors and an appropriate input
is applied to verify the output expression.
(vii) Half subtractor and Full subtractor are designed using MOS transistors and an
appropriate input is applied to verify the output expression.
(viii) Common Source, Common Drain and Common Gate amplifiers are designed using
MOS and an appropriate voltage is applied at the input to verify their output waveforms.
(ix)
A basic Current Mirror is designed using MOS and its output waveform is obtained to
verify the relation Iout=Iref.
(x)
A Cascoded Current Mirror is designed using MOS and its out waveform is obtained to
verify the minimum overdrive voltage.
Are the manuals ready for the experiments to be conducted?
Yes/No (please tick)
If “No”, the reasons there of and fixing responsibility
__________________________________________
__________________________________________
__________________________________________
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Remarks/ Endorsement by the HoD
With his /her signature with date
Name of the Teacher: Abir Jyoti Mondal
Designation: Assistant Professor
Signature with Date: 01.06.2016