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Assignment - 3 - Design a ALU with functions mentioned below - Draw the layout of your ALU, you may use the full adder cell from previous assignment © Digital Integrated Circuits2nd Interconnect Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Coping with Interconnect December 15, 2002 © Digital Integrated Circuits2nd Interconnect Impact of Interconnect Parasitics • Reduce Robustness • Affect Performance • Increase delay • Increase power dissipation Classes of Parasitics • Capacitive • Resistive • Inductive © Digital Integrated Circuits2nd Interconnect INTERCONNECT © Digital Integrated Circuits2nd Interconnect Capacitive Cross Talk (Floating lines) capacitor voltage divider network X CXY VX Y CY © Digital Integrated Circuits2nd Interconnect Capacitive Cross Talk Driven Node 0.5 0.45 0.4 X VX CXY RY 0.3 Y CY tr↑ 0.35 tXY = RY(CXY+CY) 0.25 0.2 0.15 V (Volt) 0.1 0.05 0 0 0.2 0.4 0.6 0.8 1 t (nsec) Keep time-constant smaller than rise time © Digital Integrated Circuits2nd Interconnect Dealing with Capacitive Cross Talk Avoid floating nodes Protect sensitive nodes from full swing signals Make rise and fall times as large as possible Differential signaling (cross talk becomes common mode noise rejected) Do not run wires together for a long distance Use shielding wires (GND/VDD) Use shielding layers (interleave every single layer with a GND or VDD metal plane. © Digital Integrated Circuits2nd Interconnect Shielding Shielding wire GND metal layer 2 V DD Shielding layer GND metal layer 1 Substrate (GND ) © Digital Integrated Circuits2nd Interconnect Cross Talk and Performance - When neighboring lines switch in opposite direction of victim line, delay increases Cc DELAY DEPENDENT UPON ACTIVITY IN NEIGHBORING WIRES Miller Effect - Both terminals of capacitor are switched in opposite directions (0 Vdd, Vdd 0) - Effective voltage is doubled and additional charge is needed (from Q=CV) © Digital Integrated Circuits2nd Interconnect Interconnect Projections Low-k dielectrics Both delay and power are reduced by dropping interconnect capacitance Types of low-k materials include: inorganic (SiO2), organic (Polyimides) and aerogels (ultra low-k) The numbers below are on the conservative side of the NRTS roadmap Generation Dielectric Constant 0.25 m 3.3 © Digital Integrated Circuits2nd 0.18 m 2.7 0.13 m 2.3 0.1 m 2.0 0.07 m 1.8 e 0.05 m 1.5 Interconnect Driving Large Capacitances V DD V in V out CL • Transistor Sizing • Cascaded Buffers © Digital Integrated Circuits2nd Interconnect Using Cascaded Buffers In Out 1 2 0.25 m process Cin = 2.5 fF tp0 = 30 ps N CL = 20 pF F = CL/Cin = 8000 fopt = 3.6 N = 7 tp = 0.76 ns (See Chapter 5) © Digital Integrated Circuits2nd Interconnect Output Driver Design Trade off Performance for Area and Energy Given tpmax find N and f Area f 1 F 1 A 1 f f ... f A A A f 1 f 1 2 N N 1 driver Energy min 2 Edriver 1 f f 2 ... f N 1 CiVDD © Digital Integrated Circuits2nd min min F 1 C 2 2 CiVDD L VDD f 1 f 1 Interconnect How to Design Large/Wide Transistors D(rain) Multiple Contacts Reduces diffusion capacitance Reduces gate resistance S(ource) small transistors in parallel G(ate) © Digital Integrated Circuits2nd Interconnect ESD Protection A human walking over a synthetic carpet over in 80% relative humidity can accumulate a voltage potential of 1.5 kV—you have probably experienced the sparks that jump from your hand when touching a metal object under those circumstances. The same is true for the assembly machinery. The gate connection of an MOS transistor has a very high input resistance. The voltage at which the gate oxide punctures and breaks down is about 40-100 V, and is getting smaller with reducing oxide thicknesses. A human or machine, charged up to a high static potential, can hence easily cause a fatal breakdown of the input transistors to happen when brought in contact with the input pin. This phenomena called Electrostatic Discharge (ESD) has proven to be fatal to many circuits during manufacturing and assembly. © Digital Integrated Circuits2nd Interconnect © Digital Integrated Circuits2nd Interconnect ESD Protection When a chip is connected to a board, there is unknown (potentially large) static voltage difference Equalizing potentials requires (large) charge flow through the pads Diodes sink this charge into the substrate – need guard rings to pick it up. Guard rings are grounded p+ diffusions in a p-well and supply-connected n+ diffusions in an n-well that are used to collect injected minority carriers before they reach the base of the parasitic bipolar transistors. © Digital Integrated Circuits2nd Interconnect © Digital Integrated Circuits2nd Interconnect ESD Protection The protection diodes D1 and D2 turn on when the voltage at node X rises above VDD or goes below ground. The resistor R is used to limit the peak current that flows in the diodes in the event of an unusual voltage excursion. © Digital Integrated Circuits2nd Interconnect Chip Packaging Bonding wire •Bond wires (~25m) are used to connect the package to the chip Chip L Mounting cavity L´ Lead frame • Pads are arranged in a frame around the chip • Pads are relatively large (~100m in 0.25m technology), with large pitch (100m) Pin •Many chips areas are ‘pad limited’ © Digital Integrated Circuits2nd Interconnect Pad Frame Layout © Digital Integrated Circuits2nd Die Photo Interconnect Chip Packaging An alternative is ‘flip-chip’: Pads are distributed around the chip The soldering balls are placed on pads The chip is ‘flipped’ onto the package Can have many more pads © Digital Integrated Circuits2nd Interconnect Flip Chip © Digital Integrated Circuits2nd Interconnect Impact of Resistance We have already learned how to drive RC interconnect Impact of resistance is commonly seen in power supply distribution: IR drop Voltage variations Power supply is distributed to minimize the IR drop and the change in current due to switching of gates © Digital Integrated Circuits2nd Interconnect Power Dissipation Trends 160 140 120 100 80 60 40 20 0 3.5 2.5 2 1.5 1 0 EV4 EV5 EV6 EV7 EV8 Supply Current 3.5 120 3 100 2.5 80 2 60 1.5 40 1 20 0.5 0 Better cooling technology needed Supply current is increasing faster! OnOn-chip signal integrity will be a major issue Power and current distribution are critical Opportunities to slow power growth Voltage (V) Current (A) 0.5 140 Power consumption is increasing 3 Voltage (V) Power (W) Power Dissipation Accelerate Vdd scaling Low κ dielectrics & thinner (Cu) interconnect SOI circuit innovations Clock system design micromicro-architecture L o w κ d i e l e c t r i c s & t h i n n e r ( C u ) 0 EV4 EV5 EV6 EV7 EV8 © Digital Integrated Circuits2nd ASP DAC 2000 19 Interconnect Electromigration (1) Line-open failure Limits dc-current to 1 mA/m causes the wire to break or to short circuit to another wire © Digital Integrated Circuits2nd Interconnect Electromigration (2) Open failure in contact plug © Digital Integrated Circuits2nd Interconnect The Global Wire Problem Td 0.377 RwCw 0.693Rd Cout Rd Cw RwCout Challenges No further improvements to be expected after the introduction of Copper (superconducting, optical?) Design solutions Use of fat wires Insert repeaters — but might become prohibitive (power, area) Efficient chip floorplanning Towards “communication-based” design How to deal with latency? Is synchronicity an absolute necessity? © Digital Integrated Circuits2nd Interconnect Diagonal Wiring destination diagonal y source x Manhattan • 20+% Interconnect length reduction • Clock speed Signal integrity Power integrity • 15+% Smaller chips plus 30+% via reduction © Digital Integrated Circuits2nd Courtesy Cadence X-initiative Interconnect Reducing RC-delay Making an interconnect line m times shorter reduces its propagation delay quadratically, and is sufficient to offset the extra delay of the repeaters when the wire is sufficiently long. Repeater Assuming that the repeaters have a fixed delay tpbuf, we can derive the delay of the partitioned wire. (chapter 5) © Digital Integrated Circuits2nd Interconnect Repeater Insertion (Revisited-ch.5) Sizing the repeaters is needed to reduce the delay. A more precise expression of the delay of the interconnect chain is obtained by modeling the repeater as an RC network, and by using the Elmore delay approach. Assuming that Rd and Cd are the resistance and capacitance of a minimum-sized repeater, and s is the sizing factor, this leads to the following expression: © Digital Integrated Circuits2nd Interconnect Repeater Insertion (Revisited-ch.5) © Digital Integrated Circuits2nd Interconnect INTERCONNECT © Digital Integrated Circuits2nd Interconnect L di/dt V DD L i(t) V ’DD V out V in CL Impact of inductance on supply voltages: • Change in current induces a change in voltage • Longer supply lines have larger L GND ’ L © Digital Integrated Circuits2nd Interconnect Dealing with Ldi/dt Separate power pins for I/O pads and chip core. Careful selection of the positions of the power and ground pins on the package. Increase the rise and fall times of the off-chip signals to the maximum extent allowable. Use advanced packaging technologies. © Digital Integrated Circuits2nd Interconnect Choosing the Right Pin Careful selection of the positions of the power and ground pins on the package —The inductance of pins located at the corners of the package is substantially higher Bonding wire Chip L Mounting cavity L´ Lead frame Pin © Digital Integrated Circuits2nd Interconnect Decoupling Capacitors 1 Board wiring Bonding wire Cd SUPPLY CHIP 2 Decoupling capacitor High frequency spike collection Decoupling capacitors are added: • on the board (right under every supply pin) • on the chip (under the supply straps, near large buffers) © Digital Integrated Circuits2nd low-pass network Interconnect The Transmission Line When an interconnection wire becomes sufficiently long or when the circuits become sufficiently fast, the inductance of the wire starts to dominate the delay behavior, and transmission line effects must be considered. l V in l r l r g c © Digital Integrated Circuits2nd l r g c x g c r V out g c Interconnect Design Rules of Thumb Transmission line effects should be considered when the rise or fall time of the input signal (tr, tf) is smaller than the time-of-flight of the transmission line (tflight). tr (tf) << 2.5 tflight Transmission line effects should only be considered when the total resistance of the wire is limited: R < 5 Z0 The transmission line is considered lossless when the total resistance is substantially smaller than the characteristic impedance, R < Z0/2 © Digital Integrated Circuits2nd Interconnect Should we be worried? Transmission line effects cause overshooting and nonmonotonic behavior Clock signals in 400 MHz IBM Microprocessor (measured using e-beam prober) [Restle98] © Digital Integrated Circuits2nd Interconnect Matched Termination Z0 Z0 ZL Series Source Termination ZS Z0 Z0 Parallel Destination Termination © Digital Integrated Circuits2nd Interconnect Carbon Nanotube as interconnects © Digital Integrated Circuits2nd Interconnect The “Network-on-a-Chip” Embedded Processors Memory Sub-system Interconnect Backplane Accelators © Digital Integrated Circuits2nd Configurable Accelerators Peripherals Interconnect