Download LAB 3 Timer Interrupt and ADC

LAB 6
Low-Power Optimization
CS 4101 Introduction to Embedded Systems
Chung-Ta King
Introduction
• In this lab, we will learn
– Configuring the low-power mode of MSP430
– Various techniques for making use of the lowpower modes of MSP430
Recall That …
• In the end of Lab 5, we have talked about
WDT+ & Serial Communication
Clock
System
IO
USI
Timer System
Low-Power Mode (1/3)
We can make ourselves in low-power mode, and
so does the MSP430 LanuchPad.
Low-Power Mode (2/3)
RST/NMI
Reset Active
SVS_POR
• There are
four bitsWDTIFG=1
to control the CPU and the operation of the
WDT
POR
Time Expired,
Overflowgenerator:
system
clock
– CPUOff
WDTIFG=0
RST/NMI
– WDT
OscOff
WDTIFG=1
NMI Active
Active,
PUC
Security Key Violation
– SCG0
RST/NMI is Reset Pin
CPUOFF=1
– SCG1
WDT is Active
OSCOFF=1
Active Mode
CPU I s Active
Peripheral Modules Are Active
CPUOFF=1
SCG0=0
SCG1=0
LPM0
CPU Off, MCLK Off
SMCLK On,ACLK On
SCG0=1
SCG1=1
CPUOFF=1
SCG0=1
SCG1=0
LPM1
CPU Off, MCLK Off ,
DCO Off
SMCLK On , ACLK On
DC Generator Off if DCO
Not used for SMCLK
CPUOFF=1
SCG0=0
SCG1=1
CPUOFF=1
SCG0=1
SCG1=1
LPM2
CPU Off, MCLK Off ,
DCO Off
SMCLK Off , ACLK On
LPM4
CPU Off, MCLK Off ,
DCO Off
SMCLK Off , ACLK
Off
DC Generator Off
LPM3
CPU Off, MCLK Off ,
DCO Off
SMCLK Off , ACLK On
DC Generator Off
Low-Power Mode (3/3)
Mode
CPU and Clocks
Active
CPU active. All enabled clocks active
LPM0
CPU, MCLK disabled. SMCLK, ACLK active
LPM1
CPU, MCLK disabled. DCO disabled if not used for SMCLK. ACLK active
LPM2
CPU, MCLK, SMCLK, DCO disabled. ACLK active
LPM3
CPU, MCLK, SMCLK, DCO disabled. ACLK active
LPM4
CPU and all clocks disabled
Clock Gating (1/2)
• Clock gating is a popular technique used in
many synchronous circuits for reducing
dynamic power dissipation
– Saving power by pruning the clock tree, i.e.,
disabling portions of the circuitry so that the flipflop in them do not switch states.
• Clock gating works by taking the enable inputs
attached to the registers to gate the clocks
Clock Gating (2/2)
Low-Power Operation (1/2)
• Power-efficient MSP430 applications:
– Minimize instantaneous current draw
– Maximize time spent in low power modes
• MSP430 is inherently low-power, but your design has a big
impact on power efficiency
• Proper low-power design techniques make the difference
“Instant on” clock
Low-Power Operation (2/2)
• Power draw increases with…
– Vcc
– CPU clock speed (MCLK)
– Temperature
• Slowing MCLK reduces instantaneous power, but
usually increases active duty cycle
– Power savings can be nullified
– Optimize core voltage for chosen MCLK speed
System MCLK & Vcc
•
Match needed clock speed with required Vcc to achieve the lowest power
• External LDO regulator required
• Unreliable execution results if Vcc > minimum required for selected freq.
• All G2xxx device operate up to 16MHz
Unused Pin Termination
• Digital input pins subject to shoot-through current
– Input voltages between VIL and VIH cause shoot-through if input is
allowed to “float” (left unconnected)
• Port I/Os should
– Driven as outputs
– Be driven to Vcc or ground by an external device
– Have a pull-up/down resistor
Power Saving in MSP430 (1/2)
• The most important factor for reducing power
consumption is using the MSP430 clock
system to maximize the time in LPM3
– Use interrupts to wake the processor and control
program flow.
– Peripherals should be switched on only when
needed.
– Use low-power integrated peripheral modules in
place of software driven functions. For example
Timer_A and Timer_B.
Power Saving in MSP430 (2/2)
• Define the power mode.
• Configure the I/O pins.
• Set the interrupt and ISR, remove the
software delays.
Current Consumption of MSP430 (1/3)
• The majority of the power being used by the
application we are running is spent in the
while(1) loop waiting for an interrupt.
If you could limit the amount of time the CPU is active,
the overall current requirement would be significantly reduced.
Current Consumption of MSP430 (2/3)
• Place the device in a low-power mode during
that time spent in the while(1) loop waiting
for an interrupt and save a considerable
amount of power.
The CPU is spending the majority of
the sampling period in LPM3,
drawing very little power.
Current Consumption of MSP430 (3/3)
• Optimize the code for low-power by removing
the software delays in the ISR.
LPM3 is re-entered in main()
Basic Lab
• Please refer to the document,
lab6_insruction.pdf and the sample codes.
• You don’t have to demo the lab this time, but
make sure you finish and demo all the labs
before.
Reference
• http://www.piclist.com/techref/logic/xtrapins.
htm