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Dynamic Random Access
Memories (DRAMs)
Siddharth Sharma
Indian Institute of Technology Kanpur
Tutor: Dr. A. Dasgupta
Outline
Introduction
 DRAMs
 DRAM organisation
 Enhanced DRAMs
 Volatile Memory Comparison
 Processor Memory Performance Gap
 Conclusion

Dynamic Random Access Memories (DRAMs), Siddharth Sharma, IIT Kanpur
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Introduction- Memory




Memory ─ A collection of storage cells
together with the necessary circuits to
transfer information to and from them.
Directly or indirectly connected to the CPU
via a memory bus
Comprises of two buses: an address bus and
a data bus
The CPU firstly sends a number through an
address bus, a number called memory
address, that indicates the desired location
of data. Then it reads or writes the data itself
using the data bus.
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Introduction- Random Access
Memory (RAM)
Direct Access: The memory cells can be
assessed for information transfer from any
desired location, i.e. the processing of a word
in memory is the same and requires an equal
amount of memory.
 It is the fastest main memory technology.
 It requires constant power to maintain the
stored information, therefore, it is volatile.
 Its purpose is to temporarily hold programs
and data for processing. In modern
computers it also holds the operating system.

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Introduction- Block Diagram of RAM
n data input lines
K address line
Control
lines
read
Memory unit
2k words
N bits per word
write
n data output
lines
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Dynamic RAM
A type of RAM that stores each bit of
data in a separate capacitor within an
integrated circuit.
 Since real capacitors leak charge, the
information eventually fades unless the
capacitor charge is refreshed periodically.
 Its advantage is its structural simplicity:
only one transistor and a capacitor are
required per bit, compared to four
transistors in SRAM. This allows DRAM
to reach very high density.

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The DRAM cell
Transistor acts as gate
 Capacitor can hold charge
 No charge is a 0
 Can close switch, and
add charge to store a 1
 Then open switch
bit line
(disconnect)

Dynamic Random Access Memories (DRAMs), Siddharth Sharma, IIT Kanpur
word line
DRAM bit cell
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The DRAM cell

row select
Write:
◦ 1. Drive bit line
◦ 2. Select row

Read:
◦ 1. Precharge bit line to V/2
◦ 2. Select row
◦ 3. Cell and bit line share charges
bit
 Minute voltage changes on the bit line
◦ 4. Sense (fancy sense amp)
 Can detect changes of ~1 million electrons
◦ 5. Write: restore the value

Read is really a
read followed by
a restoring write
Refresh
◦ 1. Just do a dummy read to every cell.
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DRAMHYDRAULIC ANALOGY
Select
T
B
Stored 0
Stored 1
To Pump
C
DRAM cell
(b)
(a)
Write 1
Select
B
(c)
D
Q
C
C
(d)
Write 0
(e)
Read 0
Read 1
DRAM cell
model
(h)
(f)
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(g)
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DRAMs- Read Write Characteristics
• Destructive Read
When cell read, charge removed
o Must be restored after a read
o
• Refresh
o
o
Also, there’s steady leakage
Charge must be restored periodically
• DRAM are dense (lots of cells) so there are many
address lines.
o
To reduce the physical size of DRAM we can reduce the
number of pins by applying the address lines serially in to
parts (Row Address and then Column Address)
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DRAM BIT SLICE
C is driven by 3-state
drivers
 Sense amplifier is used
to change the small
voltage change on C
into H or L
 In the electronics, B, C,
and the sense amplifier
output are connected
to make destructive
read into nondestructive read
Word
select
0
Select
B

D
C
Q
C
Word
select
0
D RA M cell
model
D RA M cell
Word
select
1
D RA M cell
Select
2 1
D
Q
2 1
C
D RA M cell
model
D RA M cell
Read/Write
logic
Sense
amplifier
D ata in
D ata in
D ata out
Read/
Bit
Write
select
(b) Symbol
Write logic
Read/
Write
Bit
select
Read logic
D ata out
(a) Logic diagram
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SENSE AMPLIFIER
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ADDRESS DECODER
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READ OPERATION
1. Precharge Amp
2. Set Read Line High
3. Set Word Line High
4. Balance Charges
5. Begin Amplification
6. Force to High or Low
7. Read to Output
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WRITE OPERATION
1. Set Word Line High
2. Precharge Cell
3. Add/Subtract Charge from
Cell
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CLASSICAL DRAM
ORGANIZATION (SQUARE)
r
o
w
bit (data) lines
Each intersection represents
a 1-T DRAM Cell
RAM Cell
Array
d
e
c
o
d
e
r
Square keeps the wires short:
Power and speed advantages
Less RC, faster precharge and
discharge is faster access time!
word (row) select
row
address
Column Selector &
I/O Circuits
data
Column
Address
Row and Column Address together
select 1 bit a time
Dynamic Random Access Memories (DRAMs), Siddharth Sharma, IIT Kanpur
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DRAM LOGICAL DIAGRAM
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DRAM LOGICAL
ORGANIZATION (4 MBIT)
column decoder
A0…A10
a
d
d
r
e
s
s
b
u
f
f
e
r
…
11
Sense Amps & I/O
r
o
w
d
e
c
o
d
e
r
11 Memory Array
(2,048 x 2,048)
Word Line

Row decoder selects 1 row of 2048 bits from 2048 rows

Column decoder selects 1 bit out of 2048 bits in such a row
Bit Line
4 Mbit = 22 address bits
11 row address bits
11 col address bits
data IN
D
data OUT
Q
Storage
Cell
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LOGIC DIAGRAM
OF A TYPICAL DRAM
RAS_L
A



CAS_L WE_L
9
256K x 8
DRAM
OE_L
8
D
Control Signals (RAS_L, CAS_L, WE_L, OE_L) are all active low
Din and Dout are combined (D):
◦
WE_L is asserted (Low), OE_L is disasserted (High)
 D serves as the data input pin
◦
WE_L is disasserted (High), OE_L is asserted (Low)
 D is the data output pin
Row and column addresses share the same pins (A)
◦
RAS_L goes low: Pins A are latched in as row address
◦
CAS_L goes low: Pins A are latched in as column address
◦
RAS/CAS edge-sensitive
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General DRAM Characteristics






Optimized for high density and therefore low cost/bit
Special fabrication process – DRAM rarely merged with
logic circuits.
Needs periodic refresh (in most applications)
Relatively slow because:
 High capacity leads to large cell arrays with high
word- and bit-line capacitance
 Complex read/write cycle. Read needs “precharge”
and write-back
Multiple clock cycles per read or write access
Multiple reads and writes are often grouped together to
amortize overhead. Referred to as “bursting”.
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Enhanced DRAMs- SDRAM
(Synchronous DRAM)
Uses a conventional clock signal instead of
asynchronous control
 SDRAM has a synchronous interface, meaning
that it waits for a signal before responding to
control inputs and is therefore synchronized
with the computer's system bus.
 This allows the chip to have a more complex
pattern of operation than asynchronous
DRAM which does not have a synchronized
interface.

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Enhanced DRAMs- DDRDRAM
(Double Data Rate DRAM)


Double edge clocking sends two bits per cycle per pin.
Uses both rising (positive edge) and falling (negative)
edge of clock for data transfer. (typical 100MHz clock
with 200 MHz transfer)
Unlike SDRAM, it can do two operations per cycle
thereby doubling the memory bandwidth over the
corresponding single-data-rate SDRAM
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Enhanced DRAMs- RDRAM
(Rambus DRAM)
It is a type of synchronous DRAM, designed by
the Rambus Corporation.
 Uses faster signaling over fewer wires (source directed
clocking) with a Transaction oriented interface protocol
 Entire data blocks are access and transferred out on a
high-speed bus-like interface (500 MB/s, 1.6 GB/s)
 It is fairly fast and has tried to address some of the
complex electrical and physical problems involved with
memory.

Dynamic Random Access Memories (DRAMs), Siddharth Sharma, IIT Kanpur
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DRAM Performance Specs
• Important DRAM Performance Considerations
• Random access time: time required to read any
random single cell
• Fast Page Cycle time: time required for page mode
access read/write to memory location on the most
recentlyaccessed page (no need to repeat RAS in this
case)
• Required refresh rate: minimum rate of refreshes
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SRAM cell
DRAM cell

Larger cell  lower density, higher
cost/bit

Smaller cell  higher density, lower
cost/bit

No dissipation


Read non-destructive
Needs periodic refresh, and refresh after
read

No refresh required

Complex read  longer access time

Simple read  faster access


Standard IC process  natural for
integration with logic
Special IC process  difficult to integrate
with logic circuits

Density impacts addressing
addr
word line
word line
bit line
data
bit line
bit line
Volatile Memory Comparison
Dynamic Random Access Memories (DRAMs), Siddharth Sharma, IIT Kanpur
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SRAM vs. DRAM summary
Tran.
per bit
Access Needs Needs
time
refresh? EDC?
Cost
Applications
SRAM
4 or 6
1X
No
Maybe
100x
Cache memories
DRAM
1
10X
Yes
Yes
1X
Main memories
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Processor-Memory Performance Gap


The development of processor and memory devices has
proceeded independently. Advances in process
technology, circuit design, and processor architecture
have led to a near-exponential increase in processor
speed and memory capacity. However, memory latencies
have not improved as dramatically.
Technological trends have produced a large and growing
gap between CPU and DRAM.
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Processor-Memory Performance Gap


Ground breaking design: merge processor and memory
into a single chip.
Compare to the conventional on-chip cache:
 Cache uses SRAM
 Uses DRAM – since the DRAM is in practice
approximately 20 times denser than SRAM
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An Example of Combined Design
4096b buf
4096b buf
4096b buf
4096b buf
16Mbit
DRAM
Cell
16Mbit
DRAM
Cell
4096b buf
4096b buf
Ld/St
Unit
Mem
Controll
Serial
port
512 B
Victim
Cache
Reg
File
Int
Uni
t
FP
Uni
t
Branch
Unit
Decode
Fetch
Memory
Processor
Figure: the design of combination of CPU and DRAM
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Conclusion
The trend towards larger DRAM devices exacerbates
the processor / memory bottleneck, requiring costly
cache hierarchies to effectively support high
performance microprocessors.
 A viable alternative is to move the processor closer to
the memory, by integrating it onto the DRAM chip.
 Processor / memory integration is advantageous, even if
it requires the use of a simpler processor.

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Potential Disadvantages




Area and power impact of increasing bandwidth to the
DRAM core
◦ Need to add more I/O lines
◦ More cost per bit
Retention time of DRAM core operating at high
temperatures
DRAM industry?
◦ A $37 billion industry need a reform? Testing DRAM
cost higher
Chip
◦ Speed, area, power, yield in DRAM process?
◦ Good performance and reasonable power?
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