Download Design of an Analog Memory Cell

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Design of an Analog Memory Cell
in 0.25 micron CMOS process
Thesis submitted in partial fulfillment
of the requirements for the degree of
Bachelor of Technology (Honours)
in
Electronics and Electrical Communication Engineering
by
Paramita Barai
under the guidance of
Dr. A. S. Dhar
Department of Electronics and Electrical Communication Engineering
Indian Institute of Technology, Kharagpur
2002
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Motivation: Why Analog Design?
Digital Design: Accurate, Greater Noise Margin, Flexible.
Limitation in speed & Hardware Cost. Delays add up.
Advantages of Analog Design:
Fig. 1: Analog Signal Processing Block
1. Low cost and high speed
2. Hardware cost reduces (ADC & DAC not req.)
3. Modern integration technologies have reduced noise
affecting ICs (NM of 0.5 volts in digital designs)
4. Trade off between quality of performance, accuracy,
hardware cost and speed
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Digital Memory
Fig.2 : DRAM structure for storing 8 bit digital word
Analog Memory
Fig 3 : Analog memory structure
Dielectric quality of capacitor
Long term storage – Charge Loses – Refreshing required
Challenging?????
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1. Basic idea to store charge in a capacitor
Fig. 4 : Main scheme of storing charge in a capacitor in analog
domain
Fig 5.
Charge fall in Cprimary
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2. Introducing another capacitor for reading out stored voltage
Fig. 6 :
Circuit with secondary capacitor for memory read
out
Fig 7 : When Vtransfer not ON, Voltages across primary and
secondary capacitors
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Fig 8 : When Vtransfer is ON, Voltages across primary and
secondary capacitors
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3. Discharging the secondary capacitor to prevent it’s
leakage charging
Fig 9 : Circuit with discharging of secondary capacitor
Fig 10 : Comparison of voltages across primary and secondary capacitors
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Fig 12 : Voltages across primary and secondary capacitors as
compared to the voltage amplified by the op amp
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Required
Output
of op amp
ie. value of
Vin
Serial
No.
VOUTPUT
Input
to op amp
ie. voltage
across
Csecondary
Taking
( 1 + R1 / R0 ) R0 = 500
ohms,
VIN
GAIN
Required
R1
1.
0.2
48m
4.167
1.5835
2.
0.3
72m
4.167
1.5835
3.
0.4
95m
4.21
1.605
4.
0.5
0.118
4.24
1.62
5.
0.6
0.14
4.286
1.643
6.
0.7
0.162
4.32
1.66
7.
0.8
0.185
4.324
1.662
9.
0.9
0.206
4.369
1.6845
10.
1.0
0.228
4.386
1.693
11.
1.1
0.25
4.4
1.7
12.
1.2
0.273
4.4
1.7
13.
1.3
0.295
4.407
1.7035
14.
1.4
0.32
4.41
1.705
15.
1.5
0.338
4.438
1.719
16.
1.6
0.36
4.44
1.72
17.
1.7
0.383
4.44
1.72
18.
1.8
0.402
4.477
1.7385
19.
1.9
0.424
4.48
1.74
20.
2.0
0.446
4.484
1.742
Table 1 : Determining value of R1 from Gain
required
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Results :
1. Assumed: voltage is to be stored till 120 milliseconds,
Refreshed every 40 ms
Frame rate is 25 frames per second.
2. Stores voltage in range 0.4 volts to 2 volts with max
5% error.
0.2 volts -------- 15% error
3. Refreshing interval is to be decided depending on the
frame rate.
4. Vwrite must be present till 40 nanoseconds
Vin must be present > 40 nanoseconds
highest speed ------------------- 25 MHz.
5. Voltage stored constant with 5 % accuracy till 120
milliseconds.
Slow systems --------------------- 8 frames per second.
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Input
analog
voltage
Voltage
after
120 ms
VIN
VLATER
1.
0.2
0.23
15
2.
0.3
0.33
10
3.
0.4
0.42
5
4.
0.5
0.52
4
5.
0.6
0.61
1.67
6.
0.7
0.71
1.43
7.
0.8
0.8
0
8.
0.9
0.9
0
9.
1.0
1.0
0
10.
1.1
1.1
0
11.
1.2
1.2
0
12.
1.3
1.3
0
13.
1.4
1.4
0
14.
1.5
1.48
1.33
15.
1.6
1.58
1.25
16.
1.7
1.68
1.18
17.
1.8
1.76
2.22
18.
1.9
1.85
2.63
19.
2.0
1.94
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Serial
No.
Accuracy
of
storage
(%)
Table 2 Quality of storage of analog voltage in the
memory (as % error)
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Conclusions and future scopes
 Linear op amp is used which has a constant gain adjusted by
the two constant biasing resistances R1 and R0.
Best results : R1 ~ 1.5 K and 1.7 K ohms
Non-linear op amp.
Variable amounts of gain ------- Non-linear resistance in
place of R1.
 Dual power supply of + 2.5 volts and – 2.5 volts.
Improve by Proper circuit design techniques.
E.g. Rail-to-rail op amp ----------single unipolar power
supply of 0 to + 2.5 volts will do.
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References :
[1] S. M. Sze, Physics of Semiconductor Devices, John Wiley & Sons Inc., 1981
[2] P. Allen and Holberg, CMOS Analog Integrated Circuits, Holt, Rinehart and
Winston, 1987
[3] Laker, K. R., and Sansen, W. M. C., Design of Analog Integrated Circuits and
Systems, McGraw-Hill, Inc., 1994.
[4] Gray, P. R., & Meyer, Analysis and Design of Analog Integrated Circuits, Third
Ed., John Wiley & Sons Inc., 1995.
[5] R.R. Harrison, P. Hasler, and B.A. Minch, “Floating-Gate CMOS Analog
Memory Cell Array”, Proceedings of the IEEE International Symposium on Circuits and Systems, Monterey, Vol.
2, pp. 204-207, 1998.
[6] B. Wang, J. R. Hellums, G. C. Sodini, “MOSFET thermal noise modelling for
analog integrated circuits”, IEEE JSSC, Vol. 29, No. 7, pp. 833-835, July 1994.
[7] A. Simoni, G. Torelli, F. Maloberti, A. Sartori, S.E. Plevridis, and A.N. Birbas,
“A single-chip optical sensor with analog memory for motion detection”, IEEE J. Solid State Circuits, vol.
30, no. 7, pp. 800-806, July 1995.
[8] R. Carmona, S. Espejo, R. Domínguez-Castro, A. Rodríguez-Vázquez, T. Roska,
T. Kozek and L. O. Chua, “A 0.5µm CMOS Random Access Analog Memory Chip for TeraOPS Speed Multimedia
Video Processing”, IEEE Transactions on Multimedia. (Accepted for publication in 1999).