Download Topic: High Performance Data Acquisition Systems Analog

Topic: High Performance Data Acquisition Systems
Analog Components: The Sample and Hold Function
Figure 1 High Performance Sample and Hold Function
Figure 1 shows a simplified block diagram of a basic high performance sample and hold
amplifier. The sample and hold function is fundamentally necessary to drive the input of a high
speed analog to digital convertor (ADC). As ADC technology has advanced, so has the sample
and hold functionality. In the 1990’s, the process technology for incorporating the sample and
hold, with the analog to digital convertor, was extremely rare and expensive, and therefore the
sample and hold amplifier was usually separate from the ADC. But within a few years, the
integration of the sample and hold function was made possible by new process developments
including high speed complimentary bipolar and advanced CMOS processes. Therefore, now,
sampling ADC’s (with an on-chip sample and hold function) are the norm and a designer rarely
has the need for a separate sample and hold amplifier when designing a high performance data
acquisition system. Although, sample and holds are still occasionally used as DAC deglitchers,
peak detectors, analog delay circuits, simultaneous sampling systems, and data distribution
systems. Having said this, it is still necessary to understand the sample and hold function in
order to design and specify an integrated sampling analog to digital convertor as well as
optimizing the overall system solution. When designing a high performance data acquisition
system, so often designers fail to account for the parameters necessary for the sample and hold
function in the ADC to operate at full capacity. Let’s talk about the sample and hold function
and how to make it work properly.
Regardless of the circuit details of any sample and hold amplifier function, the overall circuit
has four major components: The input amplifier, an energy storage device (a capacitor), an
output buffer, and a switching circuit that is digitally clocked (again see Figure 1). Of course,
central to the sample and hold function is the energy storage device. The input amplifier buffers
the input of the ADC and presents a high input impedance to the signal source (ultimately
coming from the sensor) and providing current gain to charge the energy storage device (the
hold capacitor). When the sample and hold amplifier is in track mode, the voltage on the hold
capacitor follows (or tracks) the input signal. In the hold mode, the switch function is opened
and the capacitor retains the voltage present before it was disconnected from the input buffer.
The output buffer offers a high impedance to the hold capacitor to keep the held voltage from
discharging. The switching circuit and its driver, form the mechanism by which the sample and
hold amplifier is alternately switched between track and hold modes.
Figure 2 Functional Modes and Acquisition Errors of a Sample and Hold Amplifier
There are basically four functional modes that describe the sample and hold amplifier during a
full cycle of operation: Track mode, track to hold mode, hold mode, and hold to track mode.
These modes and their respective impact to the acquisition process are summarized in Figure 2.
During track mode, the sample and hold amplifier simply operates as an amplifier and
parametrically operates as any amplifier would. Errors such as gain, offset, linearity, bandwidth,
slew rate, settling time, noise and distortion are all critical considerations for overall circuit
performance. In addition, the buffer amplifier (especially for integrated sampling ADC’s) can be
highly sensitive to input drive conditions.
Often times the switching function will propagate (backwards) through the buffer amplifier (as
current and/or voltage glitches) and disrupt what should be a clean signal on the input of the
buffer amplifier. Remember, driving the input buffer amplifier of any high performance ADC
must be designed with extreme caution. Many manufacturers of high performance ADC’s, in
order to minimize the noise and distortion of the overall ADC, will actually minimize also the
design of the buffer amplifier in which case it doesn’t “buffer” like it should and therefore to
achieve adequate real life performance, the system designer must actually create the buffer
amplifier function externally to the ADC!
Figure 3 Aperture Time
Switching from track mode to hold mode is the most important operation of a sample and hold
amplifier. The most essential dynamic property is the ability for the buffer amplifier to
disconnect quickly from the hold capacitor. This short time interval is called the “aperture time”
(see Figure 3). The actual value of the voltage that is held on the hold capacitor is a function of
both the input signal and the error introduced by this non-zero time interval which adds
uncertainty to the sample taken. The aperture uncertainty would simply introduce a fixed time
delay in the sample being taken, but of course the error can tend to change as the sampled
signal amplitude and slew rate increases. Of course in addition to the aperture uncertainty,
aperture jitter (which is the noise or timing uncertainty that is overlaid on the internal switch
signal and is also a function of the ADC sample clock noise) also increases the error in sampling
the signal (more about that later). In addition, when the sample and hold amplifier switches
from track to hold mode, there is a small amount of charge sent to the hold capacitor because
of non-ideal switches. This results in a hold mode DC offset voltage which is called the
“pedestal” error (see Figure 4). If the sample and hold is driving an ADC, the pedestal error
appears as a DC offset voltage which is usually removed by performing a system calibration.
But, if the pedestal error is a function of the input signal level, this will result to hold mode
distortion. Pedestal errors (which come from non-idealities in the switch) would normally be
solved by increasing the hold capacitor and acquisition time (both which go against higher
performing systems). Instead, most higher performing ADC’s have lower voltage differential
inputs that help to cancel the error along with calibration. Also, remember switching from track
to hold produces a transient called hold mode settling time.
Figure 4 Timing Errors
Finally, during the hold mode, there exist errors due to imperfections in the hold capacitor,
switch and the output amplifier. If a leakage current flows in or out of the hold capacitor, it will
slowly charge or discharge its voltage. This effect is known as droop and is expressed in V/nsec.
The phenomenon of droop is most often why high performance ADC’s have minimum sample
rates that can actually be quite high.
So the bottom line is, when designing a high performance data acquisition system, ultimately,
choosing the proper analog to digital convertor is the most critical function in order to achieve
the desired accuracy. But embedded within the ADC is usually a sample and hold amplifier that
must be driven properly. This requires significant understanding in what is required to drive the
ADC inputs, sample clock, data registration alignment, power supply decoupling, grounding and
printed circuit board layout to fit the desired application and results.
We will continue more into the design, implementation and characterization of the ADC (and
sample and hold amplifier) in the future.
Kai ge from CADEKA