Download A novel Majority Gate By Using Ambipolar CNTFETs

A novel Majority Gate By Using Ambipolar CNTFETs
Amir Shadmanpour1and Peiman Keshavarzian2
1
Department of Computer Engineering, Science and Research branch, Islamic Azad university, kerman, Iran.
[email protected]
2
Department of Computer Engineering, Islamic Azad university of Kerman, Iran
[email protected]
ABSTRACT
In this paper, presented a new majority gate by using ambipolar cntfet transistors. To design this majority gate, which include new
AND-2 and OR-2 gates used the minimum number of transistors. Also for design new AND-2 and OR-2 gates, we have benefited from
ambipolar transistors. As regards, ambipolar transistors have double-gate property and the most important feacher of these
transistors are transmission gate, also, the proposed gate include smallest number of transistors, expected our gate designed to be the
fastest and smallest gate.
KEY WORDS
: Majority gate, Ambipolar cntfets, New AND-2/OR-2, Carbon nano-tube,
1. INTRODUCTION
One of the new devices are cntfets that the
transistors are scaled, by this feature expected to
increase circuit performance. One of the main
differences between cntfets and mosfets are
channel components that carbon nano-tubes
instead of silicon is used. Other differences
between these two type of transistors are greater
current carrying one-dimensional gate control of
carbon nanotube to silicon[1,2]. Although the two
types of transistors is similar, but cntfets due to
the different gate cause optimize the threshold
voltage and also using contact metal drain/source
cause reduced shotkky barrier[3]. Because, the
oxygen plasma is used in cnts, most chances in
front of silicones to selection[4]. The reason for
reliable carbon nanotubes is an electric field in
the process of manufacturing and processing of
cnts. Simulation results show that energy delay in
carbon nanotubes almost 13 × better than mosfets
[1,2,5]. Many researchers prefer using CNTFETs
in the design of logic gates and memory [6].
Researchers by using of carbon nanotubes and
enjoying the shottky barrier idea, new ideas found
in transistors which called ambiplolar cntfet.
In this study, in part II shows a brief description
of the structure and function of ambipolar
transistors. And also, in port III, we will discussed
to full description of the proposed majority gate
Ambipolar majority gate, quick majority
and the full expression of our ideas. Finally, in
section IV, we will conclude.
2. AMBIPOLAR CNTFETs
Researchers by using shottky barrier ideas found
new innovations in science transistors. Ability to
control the polarity of n-type and p-type
transistors in CNTFET technology by control of
the border gate, new ideas for the use of the
second gate brovided. Polarity gate electrically,
field at the cnt/metal junction and where the
polarity is set to control [7,8].
Control gate is an electric field which located
within the cnt and it’s task is to distinguish
between the two gates. Whereas, polarity gate is
an electric field that located within the framework
cnt to drain and cnt to source. In figure 1, a view
of ambipolar cntfets transistor is shown.
figure 1. View of ambipolar double-gate CNTFET
The researchers used a substrate that has a
function as a back gates as PG and this result is in
control of all PGs. Lately, a self-aligned
drain/source in [9] suggested. The aim of this
ideas, study of unipolar cntfets. This technique
orderly queuing used for making regular queuing
PGs and CGs in design very compact device and
enabling high gate[10,11]. Figure 2 shows an
cross-section device. The main idea of this device
is an follows : carbon nano-tube are deposited on
the oxidized layer and covered by a layer of oxid
nuclear(ALD), then an aluminum gate control in
the middle of cnt is used. The negative AL2O3
guarantees insulation from the control gate to gate
polarity. Then polarity gate terminals are
activated
and
drain
and
source
are
connected[11,13].
Figure 2. Ambipolar CNFET: device (a), layout (b),
symbol (c)
Another method of manufacture, the compact
circuit layout used of double-gate shottky barrier
cntfets(figure 3.a)[14]. It’s terminals includes
drain, source, PG and CG. By using of si
substrate that included some cntfet models by
which can change the behavior of the device. In
figure 3.b you can see the symbol is used and
figure 3.c shows how to choose n and p-type
devices which dependent on the voltage applied
to the PG terminal. Ambipolar cntfets, provides
the opportunity to have field programmable
transistor[15].
3. PROPOSED DESIGN
Majority function is one of functions which in
design of full adder circuit is used [17]. In the
paper [17,18,19 ] observed that the capacitors are
used to build the majority function. Use
capacitors is one of the factors that lead to high
power consumption of this circuit. The
performance majority is considers the maximum
inputs. According to table 1, the output will be
“1” when at least two of the three inputs entrie
have a value of “1”. And also if at least two of the
three inputes have a value of “0”, the output will
be value of “0”.
Table 1. Truth table of majority gate
a
0
0
0
0
1
1
1
1
b
0
0
1
1
0
0
1
1
c
0
1
0
1
0
1
0
1
Output
0
0
0
1
0
1
1
1
We used the truth table for the design of majority
gate. So that, the truth table can be divided into
two parts. With this approach, we can design the
circuit with minimum transistor. In this case, we
selected “a” input as condition of truth table. And
also, with the simple clause at a time half circuit
will be cut-off and the other half of the circuit is
only active. So, if a = 0 the output will be “AND”
gate and if a = 1 the output will be “OR” gates. In
addition, we are enjoying ambipolar transistors
designed this gate. As regards, by ambipolar
transistors just designed XOR and XNOR gates,
we use interesting and new ideas overcome
designing AND and OR gates and we use them in
our majority gate. For design “AND-2” gate, we
used the XNOR ambipolar cntfets.
Table 2. Truth table of XNOR and AND gates
Figure 3. Double gate ambipolar transistor. (a)
Layout. (b) Symbol. (c) Configuration as n-type and ptype.
b
c
XNOR
AND
0
0
1
1
0
1
0
1
1
0
0
1
0
0
0
1
According to XNOR gate law, when the two
inputs are not same, the output will be “0” and
when the two inputs are same, the output will be
“1”. As you can see in table 2, to convert the
XNOR table to And table should look for
similarities and difference between these two
tables. When ( bc = 01 and bc = 10 ) both tables
have zero output. So, no need to change these two
outputs in AND table. In this made, the output
always will be zero. By connected input b or c to
source terminal, we succeeded in time (“0” and
“1”) the output circuit to zero and one values
changed, respectivle. So, we used this approach
interesting and could designing AND-2 gate only
one ambipolar transistor. Figure 4.a shows the
proposed ambipolar cntfet AND gate.
Table 3. Truth table of XOR and OR gates
a
b
XOR
AND
OR
0
0
0
0
0
0
1
1
0
1
1
0
1
0
1
1
1
0
1
1
(a)
(b)
(c)
For design OR gate based ambipolar, we’ve
benefited from the XOR and AND gates. Act
XOR gate, when the inputs have equal amounts
(bc = 00 and bc = 11) the output will be zero.
Also, when the input values are not equal (bc = 01
and bc = 10), the output will be “1” (according to
table 3.a ). Also, according to And gate law, the
output value will be “1” when both input values
are equal to 1, in order word, both inputs
connected (bc = 11,table 3.b). On the other, act
OR gate, when at least one of the inputs have
value “1” (connected), the output will be “1”
(according to table 3.c). We’ve combined AND
gate and XOR gate and with this combination, we
design OR gate by ambipolar transistors. Figure
4.b shows the proposed ambipolar cntfet OR gate.
Figure 4. The proposed AND-2/OR-2 gates : AND-2
(a), OR-2 (b)
After making the AND-2 and OR-2 gates, we
need to design a majority gate. We combine these
two gates designed a majority gate. In fact, if a =
0, the output should be connected to the “AND”
gate and if a = 1, OR gate results goes to output.
The proposed majority gate is shown in figure 5.
Figure 5. The proposed majority gate
Among of the very good features of majority gate
: First, the use of ambipolar transistors that
benefit from the property transmission gate,
secondly, by activating half of the circuit in one
time and disable the other half will increase the
circuit speed. Also, in this circuit is used to
minimum number of transistors to construct.
4. CONCLUSION
In this study, we designed a majority gate by
using AND-2 and OR-2 gates and benefited of
ambipolar cntfet transistors. The design of this
gate, circuit divided two parts. In fact, a partition
of the circuit always is off and other part is active.
This is one of the most important ideas that are
very effective in reducing the number of
transistors and circuit speed. According to the
main characteristic of ambipolar transistors is that
acts like a transmission gates. So, the output
should best rate and values 0 and 1 would be
ideal.
References
[1] M.H Een jama, (2009) “Fabrication and design
of nanoscale regular circuits “, EPFL Switzerland.
[2] S-M. Khalat bari, N-e-e. Shonchoy, F.
Tasnuba kabir, A. Khan, (2012) “Design and
Performance Analysis of ultra Fast CNTFET
Comparator
and
CMOS
Implementation
Comparison“, International Conference on
modeling and simulation; 28-30 March;
Cambridge:IEEE.pp 665 – 670
[3] D. Jiménez, X. Cartoixà, E. Miranda, J. Suñé,
F-A. Chaves, S. Roche, (2006)” A simple drain
current model for Schottky-barrier carbon
nanotube field effect transistors”, IOP Science
Nanotechnology, Vol. 18, No. 2, pp 1-22.
[4] S. Biswas, K-M. Jameel, R. Haque, Md. Abul
Hayat, (2012) “ A Novel Design and Simulation
of a Compact and Ultra Fast CNTFET MultiValued Inverter Using HSPICE”, International
Conference on Modelling and Simulation ;28-30
March; Cambridge:IEEE.PP 671 – 677.
[5] A-H. Chowdhury, N. Akhter, A. Al Faisal,
(2012)” Performance Analysis and Development
of Self- Consistent Model of Carbon Nanotube
Field Effect Transistor (CNTFET)”, Proceedings
of the Global Engineering, Science and
Technology Conference; 28-29 December; Dhaka,
Bangladesh .PP 1-9.
[6] D. Franklin A, M. Luisier, S-J. Han, G.
Tulevski, C. M Breslin, L. Gignac, M. S
Lundstrom, W. Haensch, (2012) “ Sub-10 nm
Carbon Nanotube Transistor “,NANO Letters,
Vol. 12,No. 2,pp 758−762.
[7] M. Pourfath, E. Ungersboeck, A. Gehring, BH. Cheongy, W. Park, H. Kosina, S. Selberherr,
(2004) ”Improving the Ambipolar Behavior of
Schottky Barrier Carbon Nanotube Field Effect
Transistors “, Solid-State Device Research
conference; 21-23 Sept:IEEE.PP 429 – 432.
[8] A. Zukoski, X. Yang, K. Mohanram, (2011)
“Universal Logic Modules Based on Double-Gate
Carbon
Nanotube
Transistors”
Design
Automation Conference (DAC); 5-9 June; New
York, NY: IEEE.PP 884 – 889.
[9] A. Javey, J. Guo, DB. Farmer, Q. Wang, E.
Yenilmez, RG. Gordon, M. Lundstrom, H. Dai .
Self-aligned ballistic molecular transistors and
electrically parallel nanotube arrays. Nano
letters,Vol. 4,No. 7,pp 1319-1322.
[10] M. H Ben Jamaa, D. Atienza, Y. Leblebici,
G. De Micheli, (2008) “Programmable Logic
Circuits Based on Ambipolar CNFET”, Design
Automation Conference; 8-13 June; Anaheim,
CA:IEEE.PP 339 – 340.
[11] M. H Ben-Jamaa, K. Mohanram, G. De
Micheli, (2011) ”An Efficient Gate Library for
Ambipolar
CNTFET
Logic”,
IEEE
TRANSACTIONS ON COMPUTER-AIDED
DESIGN OF INTEGRATED CIRCUITS AND
SYSTEMS,Vol. 30, No. 2, pp 242-255.
[12] M. H Ben Jamaa, K. Mohanram, G. De
Micheli,(2010) “ Power Consumption of Logic
Circuits in Ambipolar Carbon Nanotube
Technology”, Design, Automation & Test in
Europe Conference & Exhibition (DATE); 8-12
March 2010; Dresden:IEEE.PP 303 – 306
[13] D. Sacchetto, Y. Leblebici, G. De Micheli,
(2012) “ Ambipolar Gate-Controllable SiNW
FETs for Configurable Logic Circuits With
Improved Expressive Capability” Electron Device
Letters, IEEE,Vol. 33, No. 2,pp 143 – 145.
[14] K. Jabeur, N. Yakymets, I. O Connor, S. Le
Beux, (2011) “Ambipolar double-gate PET
binary-decisiondiagram
(Am-BDD)
for
reconfigurable
logic
cells”,
IEEE/ACM
international
Symposium
on
Nanoscale
Architectures:pp 62-168.
[15] M. De Marchi, D. Sacchetto, S. Frache, J.
Zhang, P-E. Gaillardon., Y. Leblebici, G. De
Micheli, (2012) “Polarity Control in Double-Gate,
Gate-All-Around Vertically Stacked Silicon
Nanowire FETs”, International Electron Devices
Meeting (IEDM);10-12 December: San Francisco,
California, USA.PP 183-186.
[16] M. Najari, S. Frégonèse, C. Maneux, H.
Mnif, N. Masmoudi, T. Zimmer, (2011) “
Schottky
Barrier
Carbon
Nanotube
Transistor:Compact Modeling, Scaling Study, and
Circuit
Design
Applications”
IEEE
TRANSACTIONS ON ELECTRON DEVICES,
Vol. 58, No. 1, pp 195-205.
[17] K. Navi, MH. Moaiyeri, R. Faghih Mirzaee,
O. Hashemipour, B. Mazloom Nezhad, (2009)
“Two new low-power Full Adders based on
majority-not gates”, Microelectronics Journal
ELSEVIER, Vol. 40, Issue. 1, pp 126-130.
[18] K. Navi, M. Rashtian, A. Khatir, P.
Keshavarzian, O. Hashemipour, (2010) “High
Speed Capacitor-Inverter Based Carbon Nanotube
Full Adder”, Nanoscale Res Lett,Vol. 5, No. 5, pp
859–862.
[19] K. Navi, A. Momeni, F. Sharifi, P.
Keshavarzian, (2009) ” Two novel ultra high
speed carbon nanotube Full-Adder cells”, IEICE
Electronics Express, Vol. 6,No. 19,pp 1395-1401.