Download Programmable Drum Machine Hardware Review

PROGRAMMABLE DRUM MACHINE
HARDWARE REVIEW
ENGINEER: Macgregor Gainor
PROFESSOR: Todd Morton
LAST REVISION: May 8, 2013
INTRODUCTION
This document is a hardware description for the construction of a programmable drum
machine. The device provides an intuitive interface allowing users to compose rhythmic
patterns along a 16-step bar. Nine pressure sensitive drum pads play distinct sounds when
struck. The output volume is proportional to the velocity of a pad strike. Input controls allow
the user to modify sounds with variable digital filters and effects. A microphone input
provides a signal source allowing individual drum pads to be programmed to output sounds
as desired. With two dual-axis joysticks, the user can apply digital filters and effects to their
composition. The final product provides a real-time digital drum with interactive effect
control.
In order to realize the requirements of a real-time digital drum, hardware must be
synchronized to sample and process a range of user input data. This document describes
motivation for the chosen hardware scheme. Power, Analog input, signal processing, and
user interface are discussed.
POWER
In order to supply power to the device, a 5V wall wart is used to convert 120V AC wall
supply to 5V DC. Three total rails are needed to power integrated circuits and the digital
signal processor. The 5V rail supplies voltage to IC’s used for sampling user input as well
as an LCD module. 3.3V and 1.26V rails are needed to power the DSP core. The Micrel
MIC2238 2.5MHz fixed-voltage buck switching regulator is ideal for system demands and
power consumption. The chip provides voltage rails at 3.3V and 1.26V with a 5V input.
Switching supply allows operation at about 95 percent efficiency. The regulator can supply
1.6A output current to power the DSP core rated at 1A maximum input current. Circuits
external to the core receive current from the 5V wall wart supply.
Voltage supply ripple can be a concern with a 5V wall wart and sensitive DSP core.
Decoupling capacitors are implemented to stabilize the voltage rails. 0.1uF ceramic and
10uF polarized electrolytic capacitors are placed between power and ground nodes to
remove supply ripple.
DRUM PAD AND JOYSTICK INPUT
For real-time drum pad input, piezo electric sensor voltages are continuously sampled,
converted to digital format and sent to the DSP. Nine sensors correspond to nine different
drum pads. The sensors provide a voltage relative to the velocity at which a pad is struck.
A few problems arise when interfacing the piezo sensors with a digital sampling circuit.
The sensors output positive and negative voltages to a 5V single-supply ADC. To ensure
proper operation, negative voltages are converted to positive with a full wave rectifier. A
4.3V zener is reverse biased from the rectifier output to ground to ensure that harmful
voltage levels don’t reach the ADC input. The sampling interval is limited to approximately
8ms by the number number of analog inputs and the ADC conversion time. Piezo voltage
pulses have a period of approximately 10us. In order to effectively sample pad inputs, the
piezo pulse duration must be extended to last at least as long as the sampling period. To
achieve an appropriate pulse duration specification, a parallel RC circuit is used to set a
slow voltage decay at the rectified sensor output.
Two dual-axis potentiometer joysticks provide four analog voltages that must be sampled
and converted to digital format for processing. The joysticks are used to control audio
effects and filters. The potentiometers are supplied with 5V and output between 0 and 5V.
Joystick output can be sent directly to an ADC.
With 13 total analog inputs, two eight-input multiplexing ADC’s are implemented for input
sampling. TI’s ADC0809 was chosen to provide multiplexed successive approximation
conversion with 8-bit digital output resolution. Both chips have an output enable, 3-bit input
channel select, and end-of-conversion interrupts. The multiplexers are clocked with 125kHz
clock received from a 555-timer circuit. The conversion process can take about 64 clock
cycles.
Input channel select is controlled with a 74LS393 dual 4-bit binary counter. The counter is
clocked by the end-of-conversion interrupt from an ADC. When a conversion is complete,
the counter increments and the next input channel is selected. The most significant bit is
buffered to the output enable on one ADC and inverted to the output enable on the second
ADC. That means that in one complete counting cycle, only one chip is enabled while each
input channel is sequentially sampled and converted to digital format. Once eight input
samples have been converted, the second chip will be enabled and the first will be disabled
and the process repeats. The counter runs through all 16 input channels using the EOC
interrupt to trigger a change. The result is 8-bit digital samples for 14 total analog inputs
with a sampling period of approximately 8ms.
With each completed conversion, 8-bit resolution digital sample values are fed to a
HEF4021 parallel-in/serial-out shift register. Parallel serial control is received from the
binary counter at twice the frequency of channel select. Serial output is clocked at
31.25kHz provided by the 555-timer and a HEF4013 dual D flip-flop clock divider circuit.
Two DSP GPIO pins are used to receive input. The first pin receives an interrupt from the
counter notifying the DSP that serial data will be sent. The second pin sends serial 8-bit
digital sample values at 31.25kHz.
MICROPHONE INPUT AND LINE OUT
The AIC23B Stereo Audio Codec is implemented to receive microphone input and send
stereo output to a speaker. A mono electret microphone is sent through a low pass filter
and DC blocking capacitor before reaching the codec’s microphone input. Microphone input
is received and processed by an ADC before being sent to the DSP via a multichannel
buffered serial port. The ADC is 16-bit 90-dB SNR Multibit Sigma-Delta at 48kHz sampling
frequency. Stereo output is received from the core via a second buffered serial port. The
codec contains a 16-bit 100-dB SNR Multibit Sigma-Delta DAC output. The output is sent
through a low pass filter and matched with a 48k ohm load before being sent to a stereo
headphone jack. A 12.88Mhz codec clock is maintained by the DSP core.
DIGITAL SIGNAL PROCESSOR
In order to meet the high speed processing demands for digital filtering and effects, a
225MHz TMS320C6713 floating-point DSP core is implemented. The 32-bit processor can
handle complex operations required by IIR digital filters. The device has two multichannel
audio serial ports for interfacing with the AIC23B stereo codec. 256kb onboard RAM allows
buffering of input data samples and data processing. An external memory interface is
connected with a AM29LV400 512kB flash chip for additional ROM storage. 16 GPIO pins
are available for real-time input and output. Two 32-bit general purpose timers are used for
clocking the audio codec as well as synchronizing input and output data.
USER INTERFACE
The goal of the programmable drum machine is to provide an intuitive interface for creating
and tweaking rhythmic patterns. To achieve this goal, a robust but simple UI design is
necessary. A 16x2 character serial LCD module is incorporated to display program status
and user control options. ‘Play/Pause’, ‘Loop’, ‘Undo’, and ‘Clear’ buttons are integrated as
user inputs and interfaced with the LCD. Two joysticks control programmable effects and
filters. Nine drum pads send pressure sensitive information to the DSP. To enhance user
experience, the LCD is used to display the status of individual inputs as well as user
options.