Download A Novel Table-Based Approach for Design of FinFET Circuits

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 28, NO. 7, JULY 2009
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A Novel Table-Based Approach for
Design of FinFET Circuits
Rajesh A. Thakker, Student Member, IEEE, Chaitanya Sathe, Angada B. Sachid,
Maryam Shojaei Baghini, Member, IEEE, V. Ramgopal Rao, Senior Member, IEEE, and
Mahesh B. Patil, Senior Member, IEEE
Abstract—A new lookup-table (LUT) approach, based on normalization of the drain current with an ID –VG template, is
proposed for simulation of MOS transistor circuits. The LUT approach is validated by considering two examples and by comparing the LUT results with mixed-mode (device-circuit) simulation
results. This approach is implemented in a circuit simulator and
integrated, for the first time, with an optimizer to enable efficient
design of circuits, particularly those involving novel technologies
for which compact models are not fully developed. Three FinFETbased circuits are designed to demonstrate the effectiveness of
the proposed environment. Furthermore, it is shown that the
table-based platform can take into account variations in process,
supply voltage, and temperature during the design.
of FinFET circuits. This paper is organized as follows. In
Section II, a previous work on the LUT approach for MOS
transistors is briefly reviewed. A new LUT approach and its
implementation details are described. In Section III, the proposed LUT approach is validated by comparing simulation
results obtained with the LUT approach with mixed-mode
(device-circuit) simulation. In Section IV, integration of the
LUT approach and optimization techniques is proposed for designing FinFET circuits. Three circuit examples are presented
to demonstrate the usefulness of the new platform.
Index Terms—Circuit design, FinFET, hierarchical particle
swarm optimization (PSO), lookup table (LUT).
II. LUT A PPROACH FOR F IN FET S
I. I NTRODUCTION
W
ITH REDUCING device dimensions, MOS transistor
models have become increasingly complex, and it is required to extract accurately a large number of model parameters
for the purpose of circuit simulation. Furthermore, for some of
the technologies under development, satisfactory device models
are not available. The lookup-table (LUT) approach [1]–[12]
provides an alternative to analytical models and is particularly useful for evaluating circuit performance for emerging
technologies.
Our focus in this paper is on the circuits involving FinFETs
which are currently being investigated as a possible alternative
to planar MOSFETs. FinFETs have better gate control over the
channel as compared to planar MOSFETs, which enables scaling into the sub-45-nm regime [13], [14]. Analytical models for
these devices are still under study [16], [17] and not available
for circuit design. The LUT approach provides an attractive
alternative for simulation of FinFET circuits since it does not
require a detailed physical description of the device operation.
In this paper, we present a new LUT approach and demonstrate its usefulness for simulation, design, and optimization
Manuscript received June 30, 2008; revised November 21, 2008 and
January 30, 2009. Current version published June 17, 2009. This work
was supported by the Ministry of Communications and Information Technology, Government of India. This paper was recommended by Associate
Editor H. Kosina.
R. A. Thakker, A. B. Sachid, M. Shojaei Baghini, V. Ramgopal Rao, and
M. B. Patil are with the Department of Electrical Engineering, Indian Institute
of Technology, Bombay 400 076, India.
C. Sathe was with the Department of Electrical Engineering, Indian Institute
of Technology, Bombay 400 076, India. He is now with the Department of
Electrical Engineering, University of Illinois, Urbana, IL 61801 USA.
Digital Object Identifier 10.1109/TCAD.2009.2017431
The use of LUTs to simulate circuits was first proposed
by Chawla et al. [1], where the goal was to obtain timing
information in digital circuits. Shima et al. [2] developed a 3-D
LUT approach for simulating analog circuits. The use of splines
that guarantee monotonic interpolated data for table lookup
models was suggested by Coughran et al. [4]. Barby et al. [5]
proposed optimized splines to reduce storage and also take care
of monotonicity of the interpolated data. A very general scheme
for construction of table models was proposed by Meijer [6].
Rofougaran and Abidi [9] proposed a table model which used
derivative information to construct the table of currents and
charges for accurate analog circuit simulation.
A template-based approach was described by Graham et al.
[10] in which one ID –VD characteristic was stored as a template and all other ID –VD characteristics were represented in
terms of the stored template. However, this approach is not
suitable for circuit simulation because analytic derivatives are
not available and capacitances are not represented accurately.
In the early years of the MOS transistor, accurate modeling
of the subthreshold region was not critical because the OFFstate (leakage) currents did not significantly affect the power
dissipation. However, in modern MOS circuits, leakage currents contribute substantially to the total power dissipation. In
addition, in CMOS analog circuits, since the supply voltage
has scaled down, some of the transistors operate in the nearthreshold regime, and this region therefore needs to be accurately represented by the LUT approach being employed.
A major challenge in using the LUT approach for MOS
transistors is to represent accurately the transition between
the subthreshold and strong inversion regions [15]. In the
subthreshold region, an exponential function can be used to fit
the ID –VG data. In the strong inversion region, on the other
hand, a polynomial in VG is more appropriate. However, in the
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Fig. 2. (a) Interpolation of I¯D in the VD direction. (b) Knots and table points
in the VG direction.
The VG range of interest is partitioned into N intervals by
defining “knot” points ṼGp such that
VGmin = ṼG1 < ṼG2 < ṼG3 < · · · < ṼGN +1 = VGmax .
Fig. 1. (a) ID versus VG on log scale. (b) Normalized ID versus VG [for the
same VD values as in (a)].
region of transition between these two behaviors, the ID –VG
data cannot be fitted with either of these functions. This issue
has been addressed by Bourenkov et al. [12] by using blending
functions [11] to model the transition region. However, the
approach described in [12] requires a nonuniform grid which
needs to be carefully chosen by the user manually, depending
on the different regions of device operation.
A state-function-based LUT approach was reported in [18]
and was recently validated for nonlinear RF FinFET modeling
using large-signal network analyzer measurements [19]. The
issue of transition region between subthreshold and strong
inversion was not addressed in [18] and [19].
As will be seen, the LUT approach presented in this paper
for FinFET device circumvents the difficulties of nonuniform
grid and also addresses the important issue of representation
of transition region with the help of a novel technique of data
representation and a new interpolation method.
We now describe a new LUT approach which is accurate in
all three regimes (viz., subthreshold, moderate inversion, and
strong inversion), is efficient in terms of memory requirement
and CPU time, and is robust. We present some examples which
demonstrate the accuracy and robustness of the new approach.
A. Interpolation of Current (ID )
For accurate description of the subthreshold, moderate inversion, and strong-inversion regions, we use an ID –VG template
and represent all ID –VG characteristics in terms of that template, as shown in Fig. 1. Note that, although the drain current
ID varies by orders of magnitude with respect to VG [Fig. 1(a)],
the normalized I¯D (VG , VD ) (i.e., ID (VG , VD )/ID (VG , VDmax ),
where ID (VG , VDmax ) is the template) varies smoothly between
0 and 1 [see Fig. 1(b)] and can be accurately fitted with cubic
splines as described hereinafter.
For simplicity, let us first consider I¯D (VG0 , VD0 ), where VD0 =
VDj (1 ≤ j ≤ ND ) is a table point and VG0 lies in the pth
segment (i.e., ṼGp < VG < ṼGp+1 ). This current I¯D (VG0 , VD0 )
can be written as
2
p,j
VG0 − ṼGp + ap,j
VG0 − ṼGp
I¯D = ap,j
1 + a2
3
3
VG0 − ṼGp
+ ap,j
(1)
4
where the coefficients (ap,j
k ) are computed to ensure continuity
of the current and its first two derivatives at the knot points [20].
For the case where VD0 does not coincide with a table point,
(1) can still be used, provided that the coefficients ap,j
k in (1)
are replaced by coefficients obtained by suitable interpolation
in the VD direction. As an example, the coefficient a1 at point
Q in Fig. 2(a) is given by
a1 = a1 (1 − vD ) + a1 vD
(2)
where vD = (VD0 − VDj )/(VDj+1 − VDj ), and a1 and a1 are
Lagrange approximations for a1 at Q using the values at A,
B, C and B, C, D [see Fig. 2(a)], respectively. Similarly a2 ,
a3 , a4 are computed at VD = VD0 . Finally, the current I¯D is
computed as
2
3
I¯D = a1 +a2 VG0 − ṼGp +a3 VG0 − ṼGp +a4 VG0 − ṼGp .
(3)
In summary, the LUT implementation consists of the following steps.
1) Computation of (ap,j
k ) (preprocessing).
a) Choose the ID –VG curve with VD = VDmax as the
template, and normalize the table data (ID ) as
ID VGi , VDmax
I¯D VGi , VDj = ID VGi , VDj
(4)
where (VGi , VDj ) is a table point.
b) Define “knot” points (ṼGp ) in the VG direction, where
p denotes the index of the knot point, as shown in
Fig. 2(b).
[see (1)] for k =
c) Compute the coefficients ap,j
k
1, . . . , 4; p = 1, . . . , N + 1; j = 1, . . . , ND .
THAKKER et al.: NOVEL TABLE-BASED APPROACH FOR DESIGN OF FinFET CIRCUITS
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with VG and VD . It is therefore possible to use the charge values
directly rather than normalizing them. The procedure followed
in preprocessing and run-time computation is the same as that
described for the drain current except that actual charge values
are used without normalizing.
C. Implementation in a Circuit Simulator
The LUT approach can be used for circuit simulation by
using [22]
dQX
dt
∂QX ∂VS
∂VD
+
∂t
∂VS ∂t
DC
(VG , VD , VS , t) +
IX (VG , VD , VS , t) = IX
dQX
∂QX ∂VG
∂QX
=
+
dt
∂VG ∂t
∂VD
Fig. 3.
(7)
Interpolation of ak in VG , VD grid.
2) Computation of ID for arbitrary VG0 , VD0 (run time).
a) Locate j and p such that VDj < VD0 < VDj+1 and
ṼGp < VG0 < ṼGp+1 (see Fig. 3).
b) For each of the segments A1 B1 , A2 B2 , A3 B3 , and
A4 B4 , compute the coefficients a1 , a2 , a3 , and a4 as
given by (2) and finally I¯D as given by (3).
c) Compute the actual drain current as
ID = I¯D × ID0 (VG0 )
(5)
where the template value ID0 (VG0 ) is obtained using Lagrange interpolation in the VG direction with
respect to the table points.
In addition to the ID values, the derivatives ∂ID /∂VG and
∂ID /∂VD are also required for circuit simulation. These are
somewhat cumbersome to write down here; however, they can
be easily incorporated in a computer program.
B. Terminal Charges
For transient analysis, tables of the terminal charges QG ,
QD , and QS for a FinFET are also required. These charges are
not available directly as device simulator output [15], but they
can be computed from the capacitance data at the table points
as follows [15], [21]:
QG
j
0
QD
i
V
VG D j
i
min
Cgg VG ,VDj dVG
VG , VD = Cgd VG ,VD dVD +
min
VG
j
i
V
VG D j
i
min
VG , VD = Cdd VG ,VD dVD +
Cdg VG , VDj dVG
0
min
VG
QS VGi ,VDj =− QG VGi , VDj +QD VGi , VDj
(6)
where (VGi , VDj ) is a table point.
Interpolation of the terminal charges is much simpler than
that of ID since the charges do not vary by orders of magnitude
where X = G, D, S. This equation is valid if the quasi-static
approximation holds [22], which is generally true for shortchannel devices. The LUT approach was implemented in the
general-purpose simulation package SEQUEL [23], [24]. The
generation of the table was done as follows.
1) Device parameters (geometry and doping densities) were
selected so that device simulation results obtained with
the SENTAURUS (TCAD) simulation tool [25] matched
closely the experimental data for a typical FinFET [26].
2) DC and ac simulations were performed using the device
simulator to obtain ID and capacitance values at the table
points. The terminal charges were computed using (6).
From the point of computational efficiency, it is best to
precompute the coefficients ap,j
k [see (1)] and store them for ID
as well as for the terminal charges. This would save substantial
amount of run time in circuit simulation. However, it calls for
additional storage, which can be assessed as follows.
As an example, we consider some typical numbers: NG =
50, ND = 18, and N = 13, where NG and ND are the numbers
of table points in the VG and VD directions, respectively, and
(N + 1) is the number of knots (in the VG direction). For this
situation, the total storage requirement is N0 real numbers,
where
N0 = NG + 12 × ND × N = 2858.
(8)
The accuracy of the LUT approximation can be enhanced
by increasing NG which would only marginally increase the
storage requirement as shown in (8). On the other hand, the
number of VG knots influences the storage significantly since
it gets multiplied by ND . However, a relatively small N has
been found to give good accuracy, and the storage requirement
is therefore much smaller than that required for a “full” LUT
approach where the table data, as well as the coefficients for all
grid points (i.e., ND × NG ), need to be stored [6], [24].
Another desirable feature of the LUT approach proposed
here is that the table points in the VG and VD directions and
the VG knots can all be chosen with uniform spacing without
affecting the accuracy. Even when there are several types of
devices in the circuit (e.g., with different channel lengths), the
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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 28, NO. 7, JULY 2009
user could simply use the same table and knot points for all the
devices.
Although the results described here are for FinFETs, which
are three-terminal devices, it can be trivially extended to the
four-terminal MOS transistor as well. This work will be presented elsewhere.
III. V ALIDATION OF THE LUT A PPROACH
Before applying the LUT approach to circuit simulation and
design, it is necessary to establish its validity. This can be done
by detailed comparison of the LUT results and TCAD results
as shown hereinafter.
The aforementioned results show the excellent accuracy of
the LUT approach. In particular, the accuracy of small-signal
gain for the op-amp circuit in Fig. 6, which requires accurate
derivative information, may be noted. We may therefore conclude that the LUT approach can be used as an effective tool
for simulation and design of FinFET circuits.
The computational advantage of using the LUT approach
instead of the TCAD (mixed-mode) approach can be seen from
Table I. Note that it is not practical to simulate larger circuits
(considered later in this paper) with the TCAD approach since
both the memory requirement and CPU time would be prohibitively large.
IV. D ESIGN E XAMPLES
A. Current and Capacitance
The following comparisons are required at the device characteristic level.
1) The LUT data and device data should match at the table
points. This is, of course, the least that can be expected
from an LUT scheme.
2) The currents and charges should also match at nontable
points.
3) Derivatives of current and charges obtained with the LUT
approach should be smooth and should match those obtained from the device data. This is particularly important
for analog circuits.
Fig. 4 shows the comparison between device data (as obtained
by TCAD, see Section II-C) and LUT-generated data. A fin
height of 1 μm has been used in this figure, which is simply
a “scaling factor” for determining the current and charges
obtained by 2-D TCAD simulation. In reality, of course, the
fin height would be much smaller, and therefore, a fin height
of 30 nm is used for the design of circuits. In all plots except
Fig. 4(h), an excellent match between the two can be observed,
which points to the accuracy of the LUT approach. The only
noticeable discrepancy is in the Cdd curve [Fig. 4(h)]. The
reason for this discrepancy is that, in the ON state, the conductive component of the drain current is orders of magnitude
larger than the capacitive component. As a result, the Cdd and
Cdg data obtained by device simulation are not expected to be
accurate. This point has also been discussed by Coughran et al.
[15]. Although the discrepancy in Cdd appears to be substantial,
it actually makes no difference in practice, once again due to
the fact that the conductive component dominates the capacitive
component in the ON state.
B. Circuits
For circuits with a small number of transistors, it is feasible
to carry out “mixed-mode” (device-circuit) simulation with the
SENTAURUS simulator and compare the results with circuit
simulation using the LUT approach. Figs. 5 and 6 show the
comparison for a FinFET buffer chain and an op-amp, respectively. The results were found to match well in all important
aspects such as bias points, transient response, and small-signal
performance.
In the context of emerging technologies, it is highly desirable
to be able to design circuits in a short time and explore the
potential of the technology. However, lack of device models for
a new technology often makes circuit design a difficult task.
To address this issue, the LUT approach can be used instead of
compact models. In order to use the LUT approach effectively
in the design process, it needs to be integrated with a suitable
automatic design technique. This would also allow the designer
to account for complexities such as process, supply, and temperature variations, and low-power architectures. Various optimization methods have been reported for automatic design of
analog circuits. In gradient-based optimization methods such as
sequential quadratic programming [27], Levenberg–Marquardt
[28], steepest descent method [29], and phase I-II-III method
of feasible directions [30], the following difficulties arise:
1) Derivatives of the objective function are to be calculated, and
2) a good initial guess is required to ensure that the algorithm
does, indeed, converge to the globally optimum solution.
Evolutionary algorithms, which can be used to solve multimodal optimization problems, do not suffer from difficulties
associated with the gradient-based methods. In most cases,
the particle-swarm-optimization (PSO) algorithm [31] has been
shown to perform better than other statistical techniques such as
genetic algorithm and simulated annealing [32], [33]. The PSO
algorithm has also been reported for circuit design applications
[32]–[34]. A modification of the PSO algorithm is the hierarchical PSO (HPSO) algorithm [35], [36] which provides better
exploration of the search space. We have adopted the HPSO
algorithm for integration with the LUT approach for design of
FinFET circuits.
A. Design Flow for the FinFET Circuit Optimizer
In circuit design, values of circuit elements, called design
variables, need to be determined such that the circuit satisfies
the desired specifications. Fig. 7 shows the steps and various
modules involved in the design flow for automatic FinFET
circuit design. The FinFET tables are generated before the
optimization process begins. The circuit simulator uses these
tables and the design variables (provided by the optimizer)
to simulate the circuit and returns the performance measures.
The optimizer compares the performance measures returned by
the simulator with the specified values and generates a new
THAKKER et al.: NOVEL TABLE-BASED APPROACH FOR DESIGN OF FinFET CIRCUITS
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Fig. 4. Comparison of LUT and TCAD results for a FinFET device with L = 20 nm. The data shown the figures are for 1-μm fin height. (a) ID –VG .
(b) gm −VG . (c) Cgg –VG . (d) Cdg –VG . (e) ID –VD . (f) gds −VD . (g) Cgd –VD . (h) Cdd –VD .
set of design variables. This sequence is repeated until the
specifications are met to an acceptable tolerance.
It may be noted that device parasitics such as overlap and
junction capacitances are already incorporated during table
generation. Parasitic components due to interconnect can be
included separately for accurate prediction of circuit perfor-
mance. In the examples considered here, the impact of interconnect parasitics on circuit performance is expected to be
insignificant compared to the gate capacitance. For circuits in
which interconnect parasitics are expected to play an important
role, the LUT approach can be trivially extended by extracting
the required parasitics.
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TABLE I
CPU TIME TAKEN BY LUT AND TCAD FOR SIMULATION OF
BUFFER CHAIN AND OP-AMP CIRCUIT EXAMPLES
Fig. 5. (a) Buffer chain circuit with Nfin shown in parentheses, L = 20 nm,
and VDD = 1 V. (b) Comparison of LUT and TCAD results.
Fig. 6. (a) Two-stage wide-band Miller op-amp circuit. Numbers in parentheses show Nfin for transistors and other component values. (b) Comparison of
LUT and TCAD results for the TT process corner, VDD = 1 V, CL = 20 fF,
and L = 50 nm for M1 –M5 and L = 250 nm for M6 –M8 .
B. FinFET Circuit Examples and Results
For circuit design, we have used 45-nm FinFET technology
with a minimum channel length (L) of 20 nm. The TCAD
Fig. 7.
LUT-HPSO-based design flow for automatic FinFET circuit design.
Fig. 8.
Schematic diagram of FinFET structure used for simulations.
simulator parameters (such as mobility and doping densities)
are first tuned to fit experimental data [37]. LUTs are then
generated using the TCAD simulator as discussed in Section II.
Similar calibration approaches are used in [12] and [26]. The
schematic diagram of FinFET structure used for simulations is
shown in Fig. 8. The minimum channel length (L) is 20 nm,
effective oxide thickness (EOT) is 0.9 nm, fin width (WFIN ) is
6 nm, and fin height (HFIN ) is 30 nm. The channel doping is
1 × 1015 cm−3 , and the source/drain doping is 1 × 1020 cm−3
with an overlap distance (LOV ) of 2 nm and a 1-nm/decade
THAKKER et al.: NOVEL TABLE-BASED APPROACH FOR DESIGN OF FinFET CIRCUITS
Gaussian doping gradient into the channel. To account for
process variations, 3σ values for LG , WFIN , EOT , LOV , and
doping used in this paper are ±2 nm, ±1 nm, ±0.1 nm,
±1 nm, and ±10% respectively [38]. Process corners such as
fast (FF), typical (TT), and slow (SS) are generated at room
temperature and 70 ◦ C. Fins that do not have the gate stack
over them are used as on-chip resistors [39]. These fin resistors
(FIN-RES) have As doping of 1 × 1020 cm−3 . The 3σ values,
mentioned earlier, are used to account for process variations in
the resistors, and it is found to generate a variation of ±20%
in resistance values. Metal–insulator–metal structure is used to
realize capacitive elements, which gives a variation of ±15% in
capacitance values for 3σ variations in process parameters, as
mentioned earlier.
All simulations are performed on a system with a 3-GHz
processor, 4-GB RAM, and 1024-kb cache.
1) Buffer Chain: The buffer chain, as shown in Fig. 5, is
commonly used for driving large capacitive loads in digital
integrated circuits. This circuit is designed using FinFETs with
L = 20 nm, VDD = 1 V, and with the same W/L for the n- and
p-FinFETs. Input transistors M1 and M2 are chosen to have
minimum size [40]. The number of fins (Nfin , an integer) of
the remaining three NMOS/PMOS transistors is considered as
design variables. The buffer chain is designed to minimize the
rise and fall propagation delay while driving a 36-fF capacitive
load. Process variations are taken into account during the design
cycle. The design obtained with the HPSO algorithm is shown
in Fig. 5 along with the simulation results at different process
corners for the rising edge of the input signal. The design given
by the optimizer gave delay values very close to the manually
designed buffer chain circuit using the logical effort theory.
This serves to verify the effectiveness of the optimizer, particularly for circuits where efficient manual design is difficult to
obtain, with process, voltage, and temperature variations taken
into account.
2) Two-Stage Wide-Band Operational Amplifier: A twostage Miller op-amp circuit is shown in Fig. 6. Process
variations (TT, FF, SS, FS, SF), supply variations (±10%
at 1.0 V), and temperature variations (27 ◦ C–70 ◦ C) are
taken into account during the design cycle. The circuit
is designed for the following specifications: Open-loop gain
≥ 80 dB, power dissipation ≤ 100 μW, phase margin ≥ 65◦ ,
unity gain frequency ≥ 1 GHz, and rise and fall slew rate ≥
100 V/μs.
The op-amp specifications have different orders of magnitudes, which require different weights to be assigned to them
during the design process. There are various schemes reported
in the literature for assignments of weights, such as constant
weights, adaptive weights, systematic weight-adjustment strategy, etc. We use the constant weight approach in our work. To
take care of stability of the designed circuit, particles in the
HPSO algorithm are considered to be leaders only if they have a
phase margin greater than 55◦ . This ensures that solutions with
a smaller error but with poor phase margin would not evolve.
The design variables of the op-amp are as follows: number of
fins (Nfin ) for each transistor, R1 , and C. The systematic offset
criterion is used during the design cycle. Only the solutions
which have the transistors operating in the proper operating
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TABLE II
PERFORMANCE MEASURES AT VARIOUS PROCESS CORNERS FOR THE
AUTOMATICALLY DESIGNED OP-AMP CIRCUIT OF FIG. 6. PM: PHASE
MARGIN; UGF: UNITY GAIN FREQUENCY; PD: POWER DISSIPATION;
SR: SLEW RATE RISE; AND SF: SLEW RATE FALL. THE DESIRED
SPECIFICATIONS ARE SHOWN IN PARENTHESES
Fig. 9. (a) Temperature-compensated current reference circuit. Numbers in
parentheses show Nfin for transistors and other component values. (b) Simulation results obtained with LUT approach for VDD = 1.0 V. L = 250 nm for
all transistors including op-amp blocks, and other component values for opamp (see Fig. 6 for schematic) blocks are Nfin = 19 for M1 , M2 ; Nfin = 6
for M3 , M4 ; Nfin = 180 for M5 , Nfin = 1 for M6 , Nfin = 15 for M7 ,
Nfin = 13 for M8 ; R1 = 17.34 kΩ; and C = 7 fF. The symbols represent
the LUT simulation results, and the curve is obtained by fitting.
regime (e.g., M1 in the saturation regime) are considered for
optimization. Fig. 6(a) shows the design obtained, and Table II
shows the performance measures at various process corners and
supply voltages, which are close to the desired specifications.
3) Current Reference: The temperature-compensated current reference circuit reported in [41] (see Fig. 9) is designed
using FinFET devices with L = 250 nm. The two-stage opamp configuration of Fig. 6 is used in the two op-amp blocks
(assumed identical) of Fig. 9. A temperature range from −25 ◦ C
to 125 ◦ C in steps of 25 ◦ C is considered, and FinFET tables
are generated at each of these temperature values using TCAD
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V. C ONCLUSION
In conclusion, a new LUT approach for simulation of
FinFET circuits is described. A novel platform combining the
new LUT approach and the HPSO algorithm is presented for
automatic design and optimization of FinFET-based circuits.
Three FinFET circuit design examples are discussed to demonstrate the effectiveness and robustness of the proposed design
environment. It has also been shown that the proposed platform
can take into account process, supply voltage, and temperature
variations during the design cycle. In addition to proposing
a new LUT approach, to our best knowledge, this paper is
the first report of integration of a table-based approach and
an evolutionary algorithm for design of circuits with novel
technologies such as FinFETs.
ACKNOWLEDGMENT
The authors would like to thank Synopsys, Inc., for providing
TCAD tools for this work and also N. Gandhi and C. R. Manoj
at IIT Bombay for their technical assistance. This work was
performed at the Centre of Excellence for Nanoelectronics, IIT
Bombay.
R EFERENCES
Fig. 10. Plots of Iref , ΔIref , and rms error versus iteration number for the
current reference circuit shown in Fig. 9.
TABLE III
TOTAL CPU TIME TAKEN BY THE HPSO OPTIMIZER FOR THE
DESIGN OF EXAMPLES CONSIDERED IN THIS PAPER
simulation. The design variables are as follows: eight Nfin
values, seven resistances, and one capacitance, which include
the components within the op-amp blocks. The total number of
design variables is 16, making this a more complex design than
the previous examples.
The design is carried out in two phases. First, the op-amp
block is designed over the required temperature range for a gain
of 100 dB. In the second phase, the remaining design variables
are determined to meet the current (Iref ) specifications of
10 μA ± 1% over the given temperature range. Fig. 9 shows the
design results and the current obtained at various temperatures,
which is well within the specified value of Iref .
A typical plot of the evolution of Iref with iteration number
(for 25 ◦ C) is shown in Fig. 10(a). Also plotted in the figure is
max
min
ave
−Iref
)/Iref
, where the
the variation in Iref (defined as (Iref
minimum, maximum, and average values of Iref are calculated
over the seven temperature values from −25 ◦ C to 125 ◦ C). For
the same example, the rms error in Iref (with respect to specified
Iref ), averaged over all temperatures, is shown in Fig. 10(b).
The total CPU time (excluding table generation) for the three
examples is shown in Table III, and it clearly points to the
practical utility of the proposed platform.
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Rajesh A. Thakker (S’06) received the B.E. degree
in electronics and communication engineering from
Gujarat University, Ahmedabad, India, in 1993, and
the M. Tech. degree in electrical engineering from
Indian Institute of Technology (IIT), Bombay, India,
in January 2002, where he has been working toward the Ph.D. degree in electrical engineering since
January 2006.
His area of research includes applications of evolutionary algorithms in the field of VLSI.
Chaitanya Sathe received the B.E. degree in
electrical engineering from Bangalore University,
Bangalore, India, in 2005, and the M.E. degree in
electrical engineering from Indian Institute of Science, Bangalore, in 2007. He is currently working
toward the Ph.D. degree at the University of Illinois.
From 2007 to 2008, he was a Research Assistant with the Department of Electrical Engineering,
Indian Institute of Technology, Bombay, India.
Angada B. Sachid received the B.Tech. degree in
electronics from the National Institute of Technology, Kurukshetra, India, in 2003. He has been working toward the Ph.D. degree in electrical engineering
at Indian Institute of Technology (IIT), Bombay,
India, since July 2005.
From 2003 to 2005, he was a Scientist with the
VLSI division of Advanced Numerical Research and
Analysis Group, Defence Research and Development Organization, India. He was a Summer Intern with IISc Bangalore, IIT Bombay, and Taiwan
Semiconductor Manufacturing Company (TSMC), in 2001, 2002, and 2007,
respectively. His research interests include technology-circuit codesign using
3-D devices, variability-aware-device design, novel devices and circuits for
ultra-low-power sub-0.5-V operation, static and dynamic RAMs, and impact
of scaling on different design styles.
Maryam Shojaei Baghini (M’00) received the M.S.
and Ph.D. degrees in electronics engineering from
Sharif University of Technology, Tehran, Iran, in
1991 and 1999, respectively.
In 1991 and 1992, she was with Saff and
Kavoshgaran companies, working on the design and
test of custom and semicustom ICs. From 1999
to 2000, she was with Emad Semiconductor Company as a Senior Analog IC Design Engineer. In
2001, she joined Indian Institute of Technology (IIT),
Bombay, India, as a Postdoctoral Fellow, where she
is currently a faculty member in the Department of Electrical Engineering.
Her current research interests include technology-aware design for emerging
technologies, high-performance analog and mixed-signal IC design, modeling
and CAD, and power management for system-on-a-chip applications. She has
been a Designer/Codesigner of several analog chips in industry and academia.
As a part of her research in IIT Bombay, she has designed one of the most
power-efficient CMOS instrumentation amplifiers for biomedical applications
in 2004. She is a Coinventor of three filed patent applications.
Dr. Shojaei Baghini is a corecipient of the best research award in circuit
design at Intel AAF08 and the third award on research and development at the
15th International Festival of Kharazmi in 2002.
1070
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 28, NO. 7, JULY 2009
V. Ramgopal Rao (M’98–SM’02) received the
M.Tech. degree from Indian Institute of Technology
(IIT), Bombay, India, in 1991, and the Dr. Ingenieur
degree from the Faculty of Electrical Engineering, Universitaet der Bundeswehr Munich, Germany,
in 1997.
During 1997–1998 and again in 2001, he was a
Visiting Scholar with the Department of Electrical
Engineering, University of California, Los Angeles.
He is currently a Professor with the Department of
Electrical Engineering, IIT Bombay. His areas of
interest include physics, technology, and characterization of silicon CMOS
devices for logic and mixed-signal application and nanoelectronics. He has over
200 publications in these areas in refereed international journals and conference
proceedings. He is the holder of three patents with seven currently pending.
He is the Chief Investigator for the Centre for Excellence in Nanoelectronics
project at IIT Bombay besides being the Principal Investigator for many
ongoing sponsored projects funded by various multinational industries and
government agencies.
Prof. Rao is a Fellow of the Indian National Academy of Engineering, the
Indian Academy of Sciences, and the Institution of Electronics and Telecommunication Engineers. He is an Editor for the IEEE TRANSACTIONS ON
ELECTRON DEVICES in the CMOS devices and technology area and is a Distinguished Lecturer for the IEEE Electron Devices Society. He was the organizing
committee Chair for the 17th International Conference on VLSI Design and
the 14th International Workshop on the Physics of Semiconductor Devices.
He serves on various Government of India committees on nanotechnology. He
has also served on the program/organizing committees of various international
conferences, including the International Electron Devices Meeting, IEEE Asian
Solid-State Circuits Conference, 2006 IEEE Conference on Nano-Networks,
ACM/IEEE International Symposium on Low Power Electronics and Design,
11th IEEE VLSI Design & Test Symposium, among others. He received the
Shanti Swarup Bhatnagar Prize in Engineering Sciences, in 2005, for his work
on electron devices. He also received the Swarnajayanti Fellowship Award
for 2003–2004, instituted by the Department of Science and Technology,
Government of India; 2007 IBM Faculty award; and 2008 “The Materials
Research Society of India (MRSI) Superconductivity & Materials Science
Prize.”
Mahesh B. Patil (SM’01) received the B.Tech. degree in electrical engineering from Indian Institute
of Technology (IIT), Bombay, India, in 1984, the
M.S. degree in electrical engineering from the University of Southern California, Los Angeles, in 1987,
and the Ph.D. degree in electrical engineering from
the University of Illinois at Urbana–Champaign,
in 1992.
From January 1994 to June 1999, he was with the
Department of Electrical Engineering, IIT Kanpur.
Since June 1999, he has been with the Department
of Electrical Engineering, IIT Bombay. His current research interests include
device simulation and circuit simulation.