Download Joint Design–Reliability Flows and Advanced Models Address IC

Joint Design–Reliability Flows and Advanced Models
Address IC-Reliability Issues (Part 3 of 3)
Cyril Desclèves, product marketing manager, Mentor Graphics
Mark Hagan, senior manager of engineering services, Vitesse Semiconductor
Wenping Wang, member of the technical staff, Vitesse Semiconductor
Benefits of a joint design–reliability flow
Using a joint design-reliability flow allows the designer to predict the behavior of the circuit
versus “wall-clock” time. Important metrics can be traced versus time and verified against the
specifications. For example, Figure 3 shows how the operating frequency of a CMOS oscillator
degrades over time. The absolute period and the relative degradation (in %) of the frequency are
shown in the upper and lower plots, respectively. The x-axis is the time in years in logarithmic
scale. The frequency is degraded by nearly 5% after only one year of operation. The rest of the
circuit may be able to accommodate such degradation, but maybe not.
Figure 3: The operating frequency of a CMOS oscillator degrades over time.
Originally published in Planet Analog, December 2009
Predicting the degradation of a key metric (here it is an oscillation frequency, but it could be
power consumption, a distortion level, or a settling time) is interesting. However, it is a
compound result that depends on many variables. The next thing a designer wants to know is
which device is primarily responsible for the degradation of the observed metric.
Joint design-reliability flows allow identification of devices that are subject to the largest
degradation. The information is typically presented in tabular format with sorting criteria. For
example, a table may show the relative degradation of the drive current, the linear current, and
also the trans-conductance (gm), Vth, or generally any quantity of interest.
The designer can choose the sorting criterion. In the example shown in Figure 4, the results are
sorted by decreasing “delta-Vth,” where the devices that have their threshold voltage degraded
the most severely are presented first. This allows the designer to immediately identify the areas
in the circuit that require extra attention.
Figure 4: Here the results are sorted by decreasing “delta-Vth.” The devices that have their
threshold voltage degraded the most severely are presented first.
The instantaneous stress pulses as experienced by the device also can be visualized during their
operation cycle to further “debug” reliability issues. For example, Figure 5 shows compared
instantaneous stress pulses caused by the HCI effect in identical devices subject to signals having
different slopes.
Originally published in Planet Analog, December 2009
Figure 5: Compared instantaneous stress pulses caused by the HCI effect in identical
devices subject to signals with different slopes.
The sharper signal (in blue) produces narrower but higher pulses than the slower signal (in
green). This information provides valuable insights to the designer when it comes to mitigating
the reliability issues in a design.
The latest tools are packed with very helpful capabilities. For example, the blocks or devices can
be selectively enabled or disabled in aging analysis. Stress computed during a simulation can be
saved and reloaded into other simulations.
IP protection
For many companies or foundries, the details of the equations and models used to predict the
HCI and NBTI degradation are not considered public information. Rather, they consider it to be
sensitive proprietary information that they are not keen to disclose in any way. For this purpose,
reliability simulation tools have developed encryption mechanisms that allow full protection of
the information. They can run the simulation using only binary non-human–readable model files.
As well, security encryption keys can be used to restrict access and control the execution of the
models by the simulators. Once encrypted and protected, only licensed partners, customers or
sub-contractors, such as design houses, can make use of the protected libraries.
Importance of flexible model definitions
As the modeling of these aging effects is under constant investigation and “reshaping,” the
ability to define arbitrary models is extremely important. The black-box models provided in
some solutions are not good enough for addressing this need.
Originally published in Planet Analog, December 2009
The flexibility of modern reliability simulation tools allows development of rather sophisticated
models to meet specific advanced needs. For example, at Vitesse Semiconductor Corp.,
engineers have developed significant expertise in the domain of reliability issues, and they are
implementing sophisticated models in response to a strong internal demand from designers who
require accurate prediction capability of reliability issues.
Vitesse is particularly active in the area of high-performance solutions for carrier and enterprise
Ethernet networks. The company focuses on gigabit Ethernet LAN, Ethernet-over-SONET, fibre
channel, optical transport, OTN, WDM, and other applications. The company’s designs and
markets for leading-edge telecommunication devices has motivated engineers to develop and
implement a joint design-reliability flow into their front-end methodology. This will ensure that
all Vitesse products can stand up to the true test of time.
Based on the physical understanding of both HCI and NBTI effects, Vitesse has developed a
complete set of aging models for different simulation purposes. These models are easily
implemented into Mentor Graphics UDRM reliability simulation flow. The transistor
degradation induced by HCI and NBTI can be monitored by Vth change, which is a function of
transistor technology information (fresh Vth, channel length, oxide thickness), and the operating
condition (biasing, temperature).
According to the operation mode of the circuit, two kinds of NBTI are considered: static NBTI
and dynamic NBTI. For static NBTI, the PMOS transistor is always under stress conditions. For
dynamic NBTI, both real-time and long-term prediction models were developed. The real-time
model accurately calculates the Vth degradation based on the operating and switching condition.
The long-term model is a function of input signal probability. If the time that the transistor is
under stress is longer than the time spent in recovery mode (which means larger input signal
probability), the long-term model predicts a larger degradation.
Conclusion
Reliability effects such as NCI and NBTI are real threats with advanced process nodes. Joint
design–reliability flows, however, can mitigate their effects, and advanced model definitions
allow designers to take those effects into account as early as possible.
References
1. Xiaojun Li, Jin Qin, and Joseph B. Bernstein, “Compact Modeling of MOSFET Wearout
Mechanisms for Circuit-Reliability Simulation,” IEEE Transactions on Device and Materials
Reliability, Vol. 8, No. 1, March 2008.
2. C. Guerin, V.Huard, A.Bravaix, M. Denais, J.M. Roux, F. Perrier, and W. Baks. “Combined
Effect of NBTI and Channel Hot Carrier Effects in pMOSFETs,” 2005 IEEE Integrated
Reliability Workshop Final Report.
Originally published in Planet Analog, December 2009
3. Neeraj K. Jha, P. Sahajananda Reddy, and V. Ramgopal Rao, “A New Drain Voltage
Enhanced NBTI Degradation Mechanism,” Proceedings of the 2005 IEEE IRPS.
4. V. Huard, “Hole Trapping Effect on Methodology for DC and AC Negative Bias Temperature
Instability Measurements in PMOS Transistors,” Proceedings of the 2004 IEEE IRPS, p. 40.
5. Mickael Denais, Vincent Huard, Chittoor Parthasarathy, Guillaume Ribes, Franck Perrier,
Nathalie Revil, and Alain Bravaix, “Interface Trap Generation and Hole Trapping Under NBTI
and PBTI in Advanced CMOS Technology With a 2-nm Gate Oxide,” IEEE Transactions on
Device and Materials Reliability, Vol. 4, No. 4, December 2004.
6. M. A. Alam, “A Comprehensive Model of PMOS NBTI Degradation,” Microelectron. Reliab.,
Vol. 45, pp. 71, January 2005.
7. S. Chakravarthi, “A Comprehensive Framework for Predictive Modeling of Negative Bias
Temperature Instability,” Proceedings of the 2004 IEEE IRPS, p. 273.
8. T. Grasser, “The Universality of NBTI Relaxation and Its Implications for Modeling and
Characterization,” Proceedings of the 2007 IEEE IRPS, p. 268.
9. C. Shen et al., “Characterization and Physical Origin of Fast Vth Transient in NBTI of
pMOSFETs with SiON Dielectric,” IEDM 2006.
10. Wenping Wang, Vijay Reddy, Anand T. Krishnan, Rakesh Vattikonda, Srikanth Krishnan,
and Yu Cao, “An Integrated Modeling Paradigm of Circuit Reliability for 65nm CMOS
Technology,” IEEE 2007 Custom Integrated Circuits Conference (CICC).
11. S. Bhardwaj, W. Wang, R. Vattikonda, Y. Cao, and S. Vrudhula, “Predictive Modeling of the
NBTI Effect for Reliable Design,” Proceedings of the IEEE Custom Integrated Circuits
Conference, pp. 189–192, September 2006.
12. Mridul Agarwal, Varsha Balakrishnan, Anshuman Bhuyan, Kyunglok Kim, Bipul C. Paul,
Wenping Wang, Bo Yang, Yu Cao, and Subhasish Mitra, “Optimized Circuit Failure Prediction
for Aging: Practicality and Promise,” IEEE 2008 International Test Conference.
13. Mikido Sode, et al. “Reliability Simulation Environment Tackles LSI Design,” Chip Design,
June 2007.
About the Authors
Cyril Desclèves is a product marketing manager for the Mentor Graphics Deep Submicron
division (DSM), in charge of the analog and mixed-signal verification solutions.
Originally published in Planet Analog, December 2009
Mark Hagan is senior manager of engineering services for Vitesse Semiconductor. He is
responsible for a multitude of mixed-signal design areas including front end reliability modeling,
with an overall expertise in ESD/latch-up modeling/implementation along with chip level
integration in submicron processes.
Wenping Wang is a member of the technical staff also with Vitesse Semiconductor. She is
responsible for front-end reliability modeling and implementation in regards to NBTI and HCI.
Originally published in Planet Analog, December 2009