Download Long Term Reliability of CMOS 65nm and 45nm

Long Term Reliability of
CMOS 65nm and 45nm
Emmanuel VINCENT
STMicroelectronics
Technology R&D, Crolles, France
Why IC Makers Are Scared About DSM…
(from Joseph B. Bernstein,
University of Maryland, 2007)
• Reliability margins decrease ? YES
• No way to design long-term reliability IC ? NO
2
65nm WLR Reliability Targets
• Standard process reliability qualification target :
Product lifetime higher than 10 years continuous
operation at
– Max Vdd = Vdd + 10%
– Worst-case temperature (T=125°C)
– 0.1% cumulative failure
– 90% confidence bound
• ST serves some customers requiring >10 years,
125°C reliability
3
65nm WLR Reliability and Tendencies
Item
Mechanism Knowledge improvements
TDDB
Core
Devices
I/O
Devices
1st soft-BD event detection –
But alive after BD
HCI
DC to AC derating factor
refined – Full HCI model
NBTI
New methodology : On-the-fly
technique (recovery)
TDDB
Very large margins
HCI
DC to AC derating factor
refined – Full HCI model
NBTI
New methodology : On-the-fly
technique (recovery)
EM
Exhaustive test structures –
acceleration effects on (Ea, n)
SM
Worst-case test structures –
investigations on test chip
Interconnects
4
65nm WLR Reliability and Tendencies
Item
Mechanism Knowledge improvements
1st soft-BD event detection –
But alive after BD
HCI
DC to AC derating factor
refined – Full HCI model
NBTI
New methodology : On-the-fly
technique (recovery)
TDDB
Very large margins
HCI
DC to AC derating factor
refined – Full HCI model
NBTI
New methodology : On-the-fly
technique (recovery)
EM
Exhaustive test structures –
acceleration effects on (Ea, n)
SM
Worst-case test structures –
investigations on test chip
TDDB
Core
Devices
I/O
Devices
Evolution
Interconnects
5
65nm WLR Reliability and Tendencies
Item
Mechanism Knowledge improvements
Evolution
Lifetime
1st soft-BD event detection –
But alive after BD
100x
HCI
DC to AC derating factor
refined – Full HCI model
5x
NBTI
New methodology : On-the-fly
technique (recovery)
1x
TDDB
Very large margins
1E4x
HCI
DC to AC derating factor
refined – Full HCI model
7x
NBTI
New methodology : On-the-fly
technique (recovery)
60x
EM
Exhaustive test structures –
acceleration effects on (Ea, n)
3x
SM
Worst-case test structures –
investigations on test chip
>>
TDDB
Core
Devices
I/O
Devices
Interconnects
6
65nm WLR Reliability and Tendencies
Item
Mechanism Knowledge improvements
Evolution
Lifetime
FIT %
1st soft-BD event detection –
But alive after BD
100x
**
HCI
DC to AC derating factor
refined – Full HCI model
5x
*
NBTI
New methodology : On-the-fly
technique (recovery)
1x
***
TDDB
Very large margins
1E4x
*
HCI
DC to AC derating factor
refined – Full HCI model
7x
*
NBTI
New methodology : On-the-fly
technique (recovery)
60x
*
EM
Exhaustive test structures –
acceleration effects on (Ea, n)
3x
*
SM
Worst-case test structures –
investigations on test chip
>>
*
TDDB
Core
Devices
I/O
Devices
Interconnects
* unsignificant ; ** marginal ; *** significant
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65nm CMOS Test Chip Strategy
TAC
FE/BE
COMPATIBILITY
LIBRARY
QUALIFICATION
FAILURE
RAPIDOs
…
…
PAD FRAME
ROW LOGIC
RYDE
QLIB65
MECHANISMS
SA
BLOCK
…
COL LOGIC
PROMO65
PAD FRAME
PROCESS
DEVELOPMENT
TESTCHIPS FOR
IP VALIDATION
PROCESS/IP MONITORING &
PROCESS QUALIFICATION
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65nm Test Chip Process Qualification
• Area = 24.5 mm2
ROM
• 75 M transistors
TAC
[BE assessment]
SRAM (sp65 512k x 4 )
12 blocks
Ring Osc GO1/GO2
[Speed assessment]
STD CELLS HS
DPRAM (dp65 128k x 8
TAC
)
ROMV
Single Port SRAM
17 x 512Kb
Dual Port SRAM
8 x 128Kb
STD CELLS HD
3 mm2
1 mm2
2 Mb
0.5 mm2
8.5 Mb
4.7 mm2
1 Mb
1.9 mm2
Stdcells : HD
SRAM (SP65 512k x 5 )
(1/3 SVT, 1/3 HVT,
1/3 LVT)
Stdcells: HS_SVT
15 blocks
1 block
3 mm2
0.3 mm2
9
Chip-Level Intrinsic Reliability Assessment
• Novel Operating Life Test strategy
– A-HTOL to generate failures
– Extrapolate back to nominal conditions
Example 2 : Memory (Static RAM)
Example 1 : Digital (critical path)
2
+40%
+20%
Zero
degradation
Probability of w orking products
VDD+50%
2
2
2
2.07um
0.525um
0.374um
0.299um
(C120)
(C065)
(C045)
(C045)
100%
80%
60%
40%
20%
Fresh
NBTI
0%
Degradation (%)
Vddmin (V)
10
DiR Definition and Objectives
• Design-in Reliability (DiR) = set of methodologies
and tools enabling quantitative reliability
assessment at design-level
• Translate device reliability information for use by
circuits
• Identify potential reliability problem conditions
– Take into account the actual operating conditions of a
design block
• mode, stimuli, ambient conditions
• Secure without over-design
11
Device DiR General Approach
NBTI, HCI stress experiments
Reliability Modeling
Multiple Vgs/Vds conditions
Model describing the degradation
Extraction of
degradation
parameters such
as Vt, gm & IV
curves during
stress
STEP 1
F(Vgs,Vds,T,L,t) – NBTI
Model SPICE
parameter evolution
Estimation of degradation
of different transistors
Evaluation of
degraded SPICE
STEP 2
F(Ids,Ib,T,L,t) – HCI
Add to Spice model
At designer end
Circuit spice
n/l + Input
stimuli
Iterative
Reliability Simulation
Running Simulation
with degraded models
Compare
12
Device Reliability Modeling Illustration
0.070
0.070
NBTI recovery
0.060
0.060
[V]
dVt
dVt [V]
[V]
0.050
0.050
0.040
0.040
V
0.030
0.030
0.020
0.020
0.010
0.010
0.000
0.000
1
10
100
100
1000
1000
Time [s]
Time
[s]
10000
10000
10000
100000
100000
100000
13
Example of Reliability Simulation Results
Buffer - Delay Increase
IO Input threshold change
14
Reliability Assessment : CAD vs. Silicon
1:1 correlation
CAD frequency degradation (%)
4.5
4
NBTI+HCI
3.5
3
2.5
2
1.5
1
0.5
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
Silicon frequency degradation (%)
• 65nm/45nm library NBTI-proof (ie NBTI-characterized)
15
Conclusion
• Reliability margins decrease…
– Relatively to others, NBTI is the most limiting
• … But
– Process reliability assessment accurately and relevantly
performed based on a well understood reliability physics
– Upstream to the process : Design-in Reliability to guide
designers in circuit design
– Downstream to the process :
• Accurate intrinsic reliability assessment on test chip
• Mission profile-based reliability assessment
Enable long term reliability IC design in DSM
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