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IEEE/CSC SUPERCONDUCTIVITY NEWS FORUM (global edition), July 2015.
Plenary Presentation PL3 given at ISEC 2015, Nagoya, Japan, July 6 – 9, 2015.
ISEC 2015, Nagoya, Japan, 6-9 July 2015
Recent Progress in Digital
Superconducting Electronics
Oleg A. Mukhanov
HYPRES, Inc.
175 Clearbrook Road,
Elmsford NY 10523
www.hypres.com
HYPRES
1
IEEE/CSC SUPERCONDUCTIVITY NEWS FORUM (global edition), July 2015.
Plenary Presentation PL3 given at ISEC 2015, Nagoya, Japan, July 6 – 9, 2015.
Acknowledgments
Thank you for providing materials, valuable discussions and
provoking new ideas
 M.Manheimer, S.Holmes, A.Kirichenko, D.Yohannes, I.Vernik, A.Inamdar,
I.Nevirkovets, N.Yoshikawa, A.Fujimaki, M.Hidaka, T.Filippov,
M.Volkmann, M.Johnson, E.Track, S.Benz, D. Olaya, P.Hopkins,
R.Rippard, L.Johnson, A.Herr, D.Miller, T.Ohki, A. Kent, B. Buhrman,
L.Rehm, G.Rowlands, A.McCaughan, Q.Zhao, K.Berggren, V.Semenov,
G.Gibson, G.Pepe, J.Clarke, S.Rylov, A.Golubov, V.Ryazanov, A.Kadin,
D.Gupta, D.Van Vechten
 Some new materials were not cleared for open presentation and
cannot be shown
2
IEEE/CSC SUPERCONDUCTIVITY NEWS FORUM (global edition), July 2015.
Plenary Presentation PL3 given at ISEC 2015, Nagoya, Japan, July 6 – 9, 2015.
Outline: Scaling to High Complexity
 Introduction
 Progress in Logic and Memory:
 Energy-efficient SFQ logic – gaining complexity
 New devices for in dense memory (RAM)
 Design Tools – Enabling complex designs
 Fabrication – Implementing Integrated Circuit complexity
 Cryocooling
 Future Systems
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IEEE/CSC SUPERCONDUCTIVITY NEWS FORUM (global edition), July 2015.
Plenary Presentation PL3 given at ISEC 2015, Nagoya, Japan, July 6 – 9, 2015.
Target Application: High-Performance Computing
 Tianhe-2 is top ranked HPC
 Leverages Intel Xeon Phi:
• 16 flops per Hz, at 1.1 GHz
17.6 GFLOPs/CPU*
 50 CPUs per socket,
3 sockets per drawer,
rating updated in Nov. 2014
16,000 nodes
 54 PFLOPs is the potential computing power.
Current No.1
• The full computing power is never realized
• Top500 benchmark: 33 PFLOPs measured @17.8 MW
 ~60% efficiency on Linpack benchmark. Computing efficiency on real
tasks is much lower.
 30x improvement factor required to reach Exascale (1000x Petascale)
supercomputer
* Heterogeneous architecture, but most computing power comes from Xeon Phi
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IEEE/CSC SUPERCONDUCTIVITY NEWS FORUM (global edition), July 2015.
Plenary Presentation PL3 given at ISEC 2015, Nagoya, Japan, July 6 – 9, 2015.
Problem: Increasing Power Requirements For
Conventional Supercomputers
Power (Megawatts)
Not acceptable
K-Computer
Tianhe2
Titan
Sequoia
Ability to cool
data
processing
chips limits
performance
Mira
www.top500.org
DOE Goal:
20 MW Exascale
Supercomputer
Performance (petaFlops)
Courtesy of M. Manheimer
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IEEE/CSC SUPERCONDUCTIVITY NEWS FORUM (global edition), July 2015.
Plenary Presentation PL3 given at ISEC 2015, Nagoya, Japan, July 6 – 9, 2015.
Computing and Energy
 Starting with small – ending up with LARGE:
 Shannon-Neuman-Landauer minimum energy per
bit EBITMIN = kBT ln2 ~ 4 x 10-21 J (@ T = 300K)
 In practical CMOS: 105 - 106 EBITMIN or (1-10 µW
per gate at 3 GHz)
~108
 Modern CMOS processor
transistors
operating at ~ 3 GHz: 0.1-1 kW
Intel 22nm
transistor
 Modern supercomputers and data
centers: ~10-100 MW
Intel Core i7 Processor (Nehalem),
263 mm2 , 731 Million transistors
Supercomputer:
K-Computer (Japan), 12.7 MW
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IEEE/CSC SUPERCONDUCTIVITY NEWS FORUM (global edition), July 2015.
Plenary Presentation PL3 given at ISEC 2015, Nagoya, Japan, July 6 – 9, 2015.
The Main Metric: Energy-Efficiency
 No more default next-gen CMOS improvement:




Moore’s law is saturated (if not dead?)
CMOS is becoming a commodity technology
High power dissipation is the bottleneck - Moore’s law cannot solve it
Successor technology(s) are needed
 Wide-open opportunity to introduce new technologies
 Room temperature operation is a must for mobile applications, smallplatform embedded applications
 Cryogenic technologies (superconductors,…) are acceptable for large
computing systems (data centers, supercomputers, etc.)
 Quantum Computing luster broke down the “4K scare” – even milliKelvin
systems are acceptable: Google, Lockheed, NASA bought D-Wave mK
cryogenic system. IBM, Google are building their own QC systems
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IEEE/CSC SUPERCONDUCTIVITY NEWS FORUM (global edition), July 2015.
Plenary Presentation PL3 given at ISEC 2015, Nagoya, Japan, July 6 – 9, 2015.
Speed and Power of SFQ Circuits
V
∫ Vdt = Φ 0
tSFQ
Constant area Single Flux
Quantum (SFQ) pulse
2IcR
t
 SFQ pulse energy ~ ¾ Φ0Ic ~ 2 x10-19 Joule (for Ic ~ 100 uA for 4K
operation)
 Superconductors have unique capability to transfer picosecond SFQ
waveforms without distortions with speed approaching speed of light (unlike
semiconductors - no RC-charging energy and delay)
 SFQ pulse width: tSFQ ~ Φ0/2IcR where 2IcR - pulse height
 For Nb junctions, ultimate limit tSFQ → 0.4 ps; for complex RSFQ circuits,
practical fclock ~ 1/(10 tSFQ)
 Maximum Clock Frequency for Very Large Scale Integration (VLSI) ~ 250 GHz
at low power
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IEEE/CSC SUPERCONDUCTIVITY NEWS FORUM (global edition), July 2015.
Plenary Presentation PL3 given at ISEC 2015, Nagoya, Japan, July 6 – 9, 2015.
Superconductivity can help
Power (Megawatts)
??
K-Computer
Not acceptable
Tianhe2
Titan
Sequoia
Mira
*
* D. S. Holmes et al., “EnergyEfficient Superconducting
Computing – Power Budgets and
Requirements,” IEEE Trans. Appl.
Supercond., vol. 23, 1701610, 2013
Performance (petaFlops)
Courtesy of M. Manheimer
Digital superconducting technology of choice – Single Flux Quantum
(SFQ) technology
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IEEE/CSC SUPERCONDUCTIVITY NEWS FORUM (global edition), July 2015.
Plenary Presentation PL3 given at ISEC 2015, Nagoya, Japan, July 6 – 9, 2015.
New IARPA Program
Cryogenic Computing Complexity (C3)
 Memory: energy-efficient, fast, dense, useful capacity
• compatible with superconducting SFQ logic for direct integration
• interface circuits of significant complexity in SFQ technology
 2 teams: Raytheon-BBN Technologies team (Hypres, universities),
Northrop-Grumman team
 Logic complexity: designing integrated circuits with far more
elements on a single chip than previously achieved
 2 teams: IBM team (the small company, universities), Northrop-Grumman
team
Manheimer, M.A., "Cryogenic Computing Complexity Program: Phase 1 Introduction," IEEE
Transactions on Applied Superconductivity, vol.25, no.3, June 2015.
See also numerous press releases
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IEEE/CSC SUPERCONDUCTIVITY NEWS FORUM (global edition), July 2015.
Plenary Presentation PL3 given at ISEC 2015, Nagoya, Japan, July 6 – 9, 2015.
Scaling (miniaturization) - Tall Pole in the Tent
 CMOS progressed due to the ability to scale down
 Dennard scaling (transistors gets smaller their power density stays
constant) – propelled CMOS from 1974 to ~2006
 Moore’s Law (transistor size reduction leads to more transistors per chip at
the cost-effective optimum) - largely responsible for financial sustainability
of CMOS technology
 Modern CMOS processor ~108 transistors per die, DRAM ~1 Gbit per die
 Modern SFQ digital circuit:
~104-5 JJs per die
 Circuit components are too large
 Gate layouts are too large
 Circuit implementations are too complex
 SFQ EDA tools are not adequate for VLSI
Intel Core i7
Processor (Nehalem),
263 mm2 , 731 Million
transistors
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IEEE/CSC SUPERCONDUCTIVITY NEWS FORUM (global edition), July 2015.
Plenary Presentation PL3 given at ISEC 2015, Nagoya, Japan, July 6 – 9, 2015.
Reduction and Elimination of Static Power Dissipation
• In conventional RSFQ, static power dissipation PS in bias resistors
is dominant.
• However for low complexity integrated circuits (ICs) with ~1,000
gates, this was not a problem
• PS will be a problem for high complexity ICs relevant for
computing applications
Conventional RSFQ
Vb
PS= Ib Vb
Ib ~ ¾ Ic
Rb
Ic
PD= Ib Φ0
Hypres
Digital-RF
receiver
(~1000 gates)
PS >> PD
SFQ
PD~ ¾ Φ0Ic ~ 2 x10-19 Joule
Ps is the problem
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IEEE/CSC SUPERCONDUCTIVITY NEWS FORUM (global edition), July 2015.
Plenary Presentation PL3 given at ISEC 2015, Nagoya, Japan, July 6 – 9, 2015.
Reduction of Ps: Low-Voltage RSFQ (LV-RSFQ)
LV-RSFQ CORE1α Microprocessor
Low-Voltage Drive
VB
 Reduction in staticand dynamic power
 Slightly slower switch
Courtesy of
A. Fujimaki
IB
≤ ICRS
J1
RB
L
RS
0.5 mm
Fabricated using AIST ADP2
Specifications of Superconductor Microprocessors
Standard RSFQ (2003)
Low-Voltage RSFQ (2013)
Mixed-Voltage RSFQ (Designed)
Fabrication
ISTEC 2.5-kA/cm2 STP
AIST 10-kA/cm2 ADP
AIST 20-kA/cm2
Bias Voltage
2.5 mV
0.5 mV
5 mV for data paths
0.5 mV for control unit
Clock Freq.
15 GHz
35 GHz
100 GHz
167 MIPS
333 MIPS
800 MIPS
1.6 mW
0.23 mW
1.0 mW
9.6 pJ/instruction
0.69 pJ/instruction
1.3 pJ/instruction
Performance
Power
Efficiency
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IEEE/CSC SUPERCONDUCTIVITY NEWS FORUM (global edition), July 2015.
Plenary Presentation PL3 given at ISEC 2015, Nagoya, Japan, July 6 – 9, 2015.
Elimination of PS: ERSFQ and eSFQ
 ERSFQ and eSFQ achieves the fundamental SFQ energy dissipation related to
magnetic flux crossing Josephson junction ESFQ ~ IbiasΦ0 ~ 10-19 Joule
 Eliminates static dissipation from bias resistors (dominating dissipation)
 Retains all advantages of conventional RSFQ:




dc-powered, amendable for serial biasing to reduce total dc bias current
ballistic interconnects (no extra power for intergate connections)
high speed operation (can work at 100s of GHz)
largely preserves already developed cell libraries
Conventional RSFQ
ERSFQ
Vb = Φ0⋅ƒclk
Vb
PS= Ib Vb
PD= Ib Φ0
PS= 0
Rb
Ic
SFQ
eSFQ
Ib ~ ¾ Ic
PD= Ib Φ0
Icb = Ib
Icb = Ib
Lb
Lb
Ic
SFQ
Ic
SFQ
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IEEE/CSC SUPERCONDUCTIVITY NEWS FORUM (global edition), July 2015.
Plenary Presentation PL3 given at ISEC 2015, Nagoya, Japan, July 6 – 9, 2015.
Demonstrated ERSFQ and eSFQ ICs
dc to 20 GHz continuous operation
Power dissipation:
P = fclk⋅ Ib⋅Φ0
Adder designs
done in HYPRES 4and 6-layer and
MIT-LL 4-, 8-layer
processes
Demuxes, shift
registers, decoders
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IEEE/CSC SUPERCONDUCTIVITY NEWS FORUM (global edition), July 2015.
Plenary Presentation PL3 given at ISEC 2015, Nagoya, Japan, July 6 – 9, 2015.
Elimination of Ps: Reciprocal Quantum Logic (RQL)
Ps can also be eliminated by using ac power instead of dc power
• High speed (2-20 GHz operation at 1.5 µm lithography node)
• Low power (1,000x the thermal limit)
• Negligible bit-error rate (10-44)
• Scalable to VLSI
Gate delay
1000 ps
10-15J
10-16J
Power
RQL
22 nm
10-17J
100 ps
AC power
45 nm
10-18J - practical limit
Reversible
A
A
L
10 ps
IC
1
1
10-20J – practical limit
0
10-21J
1 ps
RQL
10-22 J
10-23 J
Measured
Thermal limit
ln(2) kBT at 4.2 K
100 pW
Courtesy of A. Herr, D. Miller
CMOS
10-19J
1 nW
Projected
10 nW
1 µW
100 µW
Power dissipation per gate
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IEEE/CSC SUPERCONDUCTIVITY NEWS FORUM (global edition), July 2015.
Plenary Presentation PL3 given at ISEC 2015, Nagoya, Japan, July 6 – 9, 2015.
RQL circuits demonstrated
Hypres 4 metal layer process - proof of concept experiments
Carry LookAhead Adder
Power
Timing
Clock
distribution
8 bits
6 GHz
800 junctions
500 nW power
Lincoln process 8 metal layer process - 73K JJ with 4 dB clock margin
2 mA clock amplitude
Yield enchantment circuits
Active clock cancellation circuits
output drivers
73K JJs!
From 20 to 50000 JJs per RQL shift register
Courtesy of A. Herr, D. Miller
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IEEE/CSC SUPERCONDUCTIVITY NEWS FORUM (global edition), July 2015.
Plenary Presentation PL3 given at ISEC 2015, Nagoya, Japan, July 6 – 9, 2015.
Reduction of Dynamic Power
Dynamic power can be reduced due to Adiabatic
Switching Operation
 Circuits based on quantum parametrons are being developed
today:
 AQFPs (adiabatic quantum flux parametrons)
 nSQUIDs
 Have to work slower to achieve the ultimate low power
 Practical speed - 5 GHz
In classical circuits, the ultimately low power dissipation
can be achieved in logically and physically reversible
circuits
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IEEE/CSC SUPERCONDUCTIVITY NEWS FORUM (global edition), July 2015.
Plenary Presentation PL3 given at ISEC 2015, Nagoya, Japan, July 6 – 9, 2015.
Adiabatic Quantum Flux Parametron (AQFP)
Comparison of bit energy and
clock period of logic gates
AQFP
Adiabatic potential change of AQFP
Bit energy of AQFP is six orders of magnitude smaller than
that of CMOS.
ISEC2015 DS-P09
2πLq I c
2πL1I c
βL =
= 0.2, β q =
= 1.6
Φ0
Φ0
N. Takeuchi, et. al., Supercond. Sci. Technol. 28 015003 (2015).
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IEEE/CSC SUPERCONDUCTIVITY NEWS FORUM (global edition), July 2015.
Plenary Presentation PL3 given at ISEC 2015, Nagoya, Japan, July 6 – 9, 2015.
AQFP Logic Cell Library
Cell library adopting minimalist design
Any combinational logic gates can be designed by
using just four building blocks: buffer, NOT,
constant an branch.
ISEC2015 DS-O06
Low-speed demonstration of 8-bit
AQFP carry look-ahead adder
AIST 2.5 kA/cm2 Nb process
Junction number: 1152 JJ
Estimated energy consumption@5GHz: ~12 aJ
Excitation current margin: ± 27%
Takeuchi et al. J. Appl. Phys. 117, 173912 (2015)
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IEEE/CSC SUPERCONDUCTIVITY NEWS FORUM (global edition), July 2015.
Plenary Presentation PL3 given at ISEC 2015, Nagoya, Japan, July 6 – 9, 2015.
Demonstration of 10k-Gate AQFP Circuits
Block diagram of 10k-gate AQFP circuits
AQFP AND block
Microphotograph of 10k-gate AQFP circuits
An array of ten AND blocks
We confirmed the low-speed operation of 10kgate-scale AQFP circuits whose bias margins
are larger than 20%. The total AC bias current is
4.8 mA.
Process
AIST 2.5 kA/cm2 Nb process
Area
3.80×3.89 mm2
Total AC bias current
4.80 mA
JJ number
21020
ISEC2015 DS-INV-P04
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IEEE/CSC SUPERCONDUCTIVITY NEWS FORUM (global edition), July 2015.
Plenary Presentation PL3 given at ISEC 2015, Nagoya, Japan, July 6 – 9, 2015.
Quantum & Classical Circuits for Computing
 Quantum Computing requires classical circuits for
readout, control, error correction (RCEC)
 Adiabatic QC (Quantum Annealing)
• Classical JJ circuits are being used for control and programming
– QFP shift registers
– Flux DACs
 Gate model QC
• Presently mostly CMOS circuits are used
• Classical JJ circuits can do the job
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IEEE/CSC SUPERCONDUCTIVITY NEWS FORUM (global edition), July 2015.
Plenary Presentation PL3 given at ISEC 2015, Nagoya, Japan, July 6 – 9, 2015.
•
10,960 QFP shift
register stages
•
18,304 flux DACs
Courtesy of M. Johnson
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IEEE/CSC SUPERCONDUCTIVITY NEWS FORUM (global edition), July 2015.
Plenary Presentation PL3 given at ISEC 2015, Nagoya, Japan, July 6 – 9, 2015.
Present Quantum Computing System
Gate-Model QC
manual
Not scalable ($100K per qubit)
Arbitrary Wave Generators
(AWG)
Cavity Control Electronics
Readout Analysis
Circuits
Semiconductor circuits
300 K
4K
Quantum readout
elements (quantum
noise limited amplifiers,
etc.)
30 mK
Quantum Circuits (quantum gates made of
qubits, resonators, quantum memory, etc.)
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IEEE/CSC SUPERCONDUCTIVITY NEWS FORUM (global edition), July 2015.
Plenary Presentation PL3 given at ISEC 2015, Nagoya, Japan, July 6 – 9, 2015.
Possible Quantum Computing System
Gate-Model QC
CLOCK
and
CARRIER
Data INPUT
SFQ Error Correction
Data OUTPUT
SFQ Readout
100 mK - 4 K
SFQ Cavity Control Circuits
Quantum readout
elements (quantum
noise limited amplifiers,
etc.)
30 mK
Quantum Circuits (quantum gates made of
qubits, resonators, quantum memory, etc.)
25
IEEE/CSC SUPERCONDUCTIVITY NEWS FORUM (global edition), July 2015.
Plenary Presentation PL3 given at ISEC 2015, Nagoya, Japan, July 6 – 9, 2015.
CryoMemory: Bringing Spintronics
 Conventional superconducting electronic set (materials,
devices, approaches) is not sufficient to address the memory
problem
 Lack of dense superconducting memory: 4K only for JJ RAM
• SQUID-based memory cell size limits the memory density
 Lack of gain and input/output isolation in Josephson junctions
• makes RAM design difficult and/or physically large
Decided to bring spintronic elements to
superconducting circuits
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IEEE/CSC SUPERCONDUCTIVITY NEWS FORUM (global edition), July 2015.
Plenary Presentation PL3 given at ISEC 2015, Nagoya, Japan, July 6 – 9, 2015.
Cryogenic Magnetic Memory
 Hybrid circuits with cryogenic magnetoresistive
memory elements (JJ+metal spintronics)
 Memory cell based on spintronic elements with addition of JJs
(for low impedance) or nanowire switches (for high
impedance)
 Polarized spin injection for magnetization reversal (spin
torque transfer)
 JJ periphery (address decoders, sense, etc.)
 Superconducting-Ferromagnetic (SF) Junctions
(superconducting spintronics)
 Memory cell based on Magnetic JJs (MJJ) w/ or w/o additional
JJs or SF switches
 Magnetic field for magnetization reversal (field
programmable)
 JJ periphery (address decoders, sense, etc.)
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IEEE/CSC SUPERCONDUCTIVITY NEWS FORUM (global edition), July 2015.
Plenary Presentation PL3 given at ISEC 2015, Nagoya, Japan, July 6 – 9, 2015.
Memory Cell Scalability and Energy
 Physics vs Engineering – one needs to develop a practical RAM (not just
memory element)
 Criteria:
 Scalability of memory cell (Remanent vs Exchange field)

Goal: <100 nm memory element, 200 nm pitch
 Read out scheme (Voltage (multi SFQ), SFQ pulse,…)

Goal: single SFQ (10-19 Joule), ~5ps per cell
 Write scheme
• Field programmable (density is limited)
• Spin Torque, Spin-Orbit Transfer (delivers higher density RAM, scalable)
 Goal: 10 SFQs (10-18 Joule), ~50-100ps per cell
 Resiliency to Half-Select (resiliency to sub-threshold currents)
 For Read and Write operations
 Goal: no-disturb
Memory Element vs Memory Cell: Scalability of magnetic memory elements is only
relevant, if it limits the size of memory cell and sets the RAM capacity limitations.
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IEEE/CSC SUPERCONDUCTIVITY NEWS FORUM (global edition), July 2015.
Plenary Presentation PL3 given at ISEC 2015, Nagoya, Japan, July 6 – 9, 2015.
Cryo Metal Spintronics: Spin Torque Transfer CryoMRAM
Orthogonal Spin transfer (OST) devices show a
promise for cryogenic memory compatible with eSFQ
digital circuits.
100 ps pulses, E<= 200 aJ/switch
Courtesy of T. Ohki
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IEEE/CSC SUPERCONDUCTIVITY NEWS FORUM (global edition), July 2015.
Plenary Presentation PL3 given at ISEC 2015, Nagoya, Japan, July 6 – 9, 2015.
Cryo Metal Spintronics: Spin Orbit MRAM
Spin Hall Effect (SHE) materials yields a 4-terminal device for Cryogenic MRAM which
has large magneto-resistance and maintains low write energy
Park, Ralph and Buhrman, APL 2014
Courtesy of T. Ohki
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IEEE/CSC SUPERCONDUCTIVITY NEWS FORUM (global edition), July 2015.
Plenary Presentation PL3 given at ISEC 2015, Nagoya, Japan, July 6 – 9, 2015.
Memory Element Based on a Pseudo-Spin-Valve-Barrier JJ
Device Structure:
JJ with two ferromagnetic barriers in series
Free
Spacer
Hard
Nb
“0”
“1”
Features:
•Demonstrated scalable switching of Jc
•Josephson phase can also switch between 0 & π
•Nonvolatile (at a cryogenic temperature)
•Demonstrated ∆Jc/Jc up to 500 %
•Write: similar to MRAM (field or current)
Challenges:
•Write efficiency and speed
•Control circuit designs and implementation
•Electrical properties not compatible to SIS JJs
Courtesy of B. Baek, S. Benz
IcAP
Magnetization States
Ic P
PSV
Nb
Principle:
Exchange field effect on Josephson coupling
Jc(parallel) ≠ Jc(anti-parallel)
Also Phase(0 state) ≠ Phase(π state)
Large ∆Jc
0-π phase shift
0-JJ
0-JJ
π-JJ
π-JJ
Baek, B. et al. Nat. Commun. 5:3888 (2014)
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IEEE/CSC SUPERCONDUCTIVITY NEWS FORUM (global edition), July 2015.
Plenary Presentation PL3 given at ISEC 2015, Nagoya, Japan, July 6 – 9, 2015.
JMRAM devices and main characteristics
free SAF
fixed SAF
fixed
Increase write margin
Eliminate internal field
MRAM stack
Spin triplet +
toggle
Spin triplet
π
0
Spin toggle
π
0
Spin valve
π
0
free
JMRAM MJJs
In test
Demonstrated
free
polarizer
SAF
fixed
polarizer
Increase read margin
polarizer
free SAF
fixed SAF
polarizer
Highest performance
•
High density
two Josephson junctions per cell
108/cm2
•
Low energy write
reduced switching energy at 4.2 K
fJ per bit
•
Ultra-low energy read
low energy Josephson junctions
aJ per bit
•
Fast access time for read
time-of- flight in Nb line
0.4 ps per cell
Courtesy of A. Herr, D. Miller
32
IEEE/CSC SUPERCONDUCTIVITY NEWS FORUM (global edition), July 2015.
Plenary Presentation PL3 given at ISEC 2015, Nagoya, Japan, July 6 – 9, 2015.
JMRAM is a superconducting MRAM
Room-Temp. Toggle MRAM
Write Line 2
I
H
Magnetic Tunnel Junction
Top
Electrode
Bottom
Electrode
H
Isense
I
Write Line 1
ON for
sensing,
OFF for
programming
I Ref
www.everspin.com
www.freescale.com
Memory cell is a magnetic tunnel junction with superconducting electrodes:
underlining physics demonstrated on SFS Josephson junction
memory state – critical current magnetic hysteresis
write – spin reversal
read – Josephson effect
33
IEEE/CSC SUPERCONDUCTIVITY NEWS FORUM (global edition), July 2015.
Plenary Presentation PL3 given at ISEC 2015, Nagoya, Japan, July 6 – 9, 2015.
Fast Magnetic Josephson Junction (MJJ)
2.5
Memory Element Operation
Ic0 = 2.35 mA
Iread = 2.1 mA
2.0
Ic1 = 1.88 mA
Ic (mA)
1.5
1.0
0.5
0.0
-10
Hext (Oe)
0
Magnetization curve for SIsFS MJJ
10
SIsFS
Electrical Switching of SIsFS MJJs
Memory retention for SIsFS MJJ
•
SIsFS MJJs have high IcRN - electrically
compatible to conventional JJs
•
No need for readout SQUIDs, can be use to
build SFQ circuits similar to JJs
•
Can enable very small memory cell size
Appl. Phys. Lett., vol. 100, 222601, 2012
Courtesy of I. Vernik
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IEEE/CSC SUPERCONDUCTIVITY NEWS FORUM (global edition), July 2015.
Plenary Presentation PL3 given at ISEC 2015, Nagoya, Japan, July 6 – 9, 2015.
nTron: Nanowire 3-terminal Device
Can be used for RAM as line drivers
and memory cell selector
Courtesy of K. Berggren, T. Ohki
Bias range
for operation
Current (uA)
• Planar NbN or Nb, simple to
fabricate
• SFQ compatible
Demonstrated:
• Comparator; 66nA grey zone
• Digital Logic, half adder
• 20x gain
• Good In/Out isolation
• High Z drive
Voltage (V)
50 ps risetime pulses, potential
of 100s of MHz rep rate
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IEEE/CSC SUPERCONDUCTIVITY NEWS FORUM (global edition), July 2015.
Plenary Presentation PL3 given at ISEC 2015, Nagoya, Japan, July 6 – 9, 2015.
Superconductor-Ferromagnet Transistor
• Superconductor-Ferromagnet Transistor (SFT)
- Superconducting 3-terminal device with good
input/output isolation, capable of amplifying
signal, and working at 4.2 K is useful for
superconducting memory as a memory cell
selector
SISFIFS-based SFT
Acceptor (SIS)
Injector
Injector (SFIF)
Va
Ia
Ia
Ii
10 µm
acceptor
Ii
injector
Nb
Ni
Al/AlOx
Courtesy of I. Nevirkovets
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IEEE/CSC SUPERCONDUCTIVITY NEWS FORUM (global edition), July 2015.
Plenary Presentation PL3 given at ISEC 2015, Nagoya, Japan, July 6 – 9, 2015.
Control of Josephson current in SISFIFS devices
Ii
4
3
2
Device structure and biasing
injector
1
0
1.5
-1
-2
-3
6
δIc/δIi>1
δIc/δIi>1
5
Ic (mA)
Typical I-V
curves
acceptor
Ic (mA)
Ia
S
F
I
F
S
I
S
Current (mA)
Ii
-4
Ic(H)
1.0
0.5
0.0
-400 -200 0 200 400
H (mA of solenoid current)
-8
-6
-4
-2 0 2
Voltage (mV)
4
6
8
4
3
Typical Ic vs. Ii
dependence
2
1
-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0
Ii (mA)
ISEC2015-P0100
δIc/δIi increases with Rti/Rta
(Rti and Rta are specific tunneling
resistances of the injector and
acceptor, respectively)
Courtesy of I. Nevirkovets
37
IEEE/CSC SUPERCONDUCTIVITY NEWS FORUM (global edition), July 2015.
Plenary Presentation PL3 given at ISEC 2015, Nagoya, Japan, July 6 – 9, 2015.
Achieving Integrated Circuit Complexity
To go beyond simple device, gates and small circuit
demonstration one needs:
 Adequate design tools (Electronic Design Automation
(EDA) tools) capable of
• Simulating complex circuits
• Adopting new physical device models (e.g. spintronic
devices)
• Adequate parameter extraction (3D solvers)
• Layout vs Schematic tools
• Synthesis
 High-yield, high density fabrication process
• 6-10 superconducting layers with via plugs
• Integration of new devices (SFQ+ spintronic, nanowire, etc.)
• Scalable for high circuit density
38
IEEE/CSC SUPERCONDUCTIVITY NEWS FORUM (global edition), July 2015.
Plenary Presentation PL3 given at ISEC 2015, Nagoya, Japan, July 6 – 9, 2015.
2015 EDA Tools
 Circuit Simulators/Optimizers




Old-proven workhorse, but not extendible: PSCAN/COWBoy
Also used for small circuits: WR Spice/MALT
Being introduced: Cadence Spectre/COWBoy-like optimizer
Sometimes used: JSIM,…
 Logic Simulators: Verilog, VHDL
 Layout Editors
 Cadence Virtuoso
 XIC
 AutoCAD, Ledit, LASI…
 Verification
 Parameters extraction
• Works well for legacy processes, not adequate for >4 layer fab: Lmeter
• Works well, but slow and not convenient: FastHenry, Khapaev
• Current #1 choice: InductEx (with post-FastHenry solver)
 DRC, LVS: Cadence DIVA: works on gate and circuit level, chip-level being developed
39
IEEE/CSC SUPERCONDUCTIVITY NEWS FORUM (global edition), July 2015.
Plenary Presentation PL3 given at ISEC 2015, Nagoya, Japan, July 6 – 9, 2015.
Typical Legacy Superconductor Design Flow
Graphical Design Tool
~ 500 JJs
PSCAN or
WRSPICE
Schematic
Symbol
COWBoy
or MALT
Opti
miz
er
Circuit Simulation
Stimulus
Behavioral
Hierarchical
circuit
analyzer
SFQHDL
Schematic#1
Schematic#2
Schematic#n
(with few cells)
(with few cells)
(with few cells)
Layout
 Error identification simplified by
comparing behavioral description
with circuit simulation
 Efficient circuit optimizer for
simple cells
 PSCAN limits circuit complexity to
PSCAN
LAYOUT
(interconnection of
library cells and fully
customized cells)
Lmeter
PSCAN
PSCAN
~ 500 JJs
 Complex schematics broken into
several sub-schematics
 Layout is not tightly coupled to a cell schematic
Floor
Planning
 A customized cell layout may combine functionality from few
schematic cells
 LVS and Post-layout simulation is extremely laborious
and is routinely skipped
Courtesy of A. Inamdar
40
IEEE/CSC SUPERCONDUCTIVITY NEWS FORUM (global edition), July 2015.
Plenary Presentation PL3 given at ISEC 2015, Nagoya, Japan, July 6 – 9, 2015.
Advanced Design Flow
Parametric
Sweeps
Cadence Basic
Cell
Corners
Simulation
Post
Processing
Results
Viewer
Analog Design Environ.
Schematic
(supports multi-analysis
test benches)
Opti
mizer
Symbol
>> 5,000 JJs
Behavioral
SPECTRE
(state-of the-art
circuit simulator)
Layout
Optimized
Stimulus
Extracted
Component
models
Medium
Complexity
(Verilog A)
Post-Layout
Scaled Symbol
Check
Margins
Monte-Carlo
Analysis
Statistical
Variations
(from Diagnostics
Database)
JJ
Ind
Circuit
Schematic
Cell Library
LVS &Postlayout Sim
Layout
(interconnection
of library cells)
Hierarchical
circuit
analyzer
Floorplan
Cell Library minimizes design effort and errors
 layout eased to interconnecting library cells
reuses proven and well characterized cells
 LVS and Post-layout simulation possible as layout is tightly
coupled to schematic
Timing
(back-annotation)
Behavioral
High
Complexity
Res
Flux Offset
Return
Current
HDL
(static timing
analysis)
 Spectre — a state-of-the-art simulator supports high
complexity circuit simulation
 Facilitates Monte-Carlo simulations to improve yield
 HDL simulation used for extremely high complexity
Courtesy of A. Inamdar
41
IEEE/CSC SUPERCONDUCTIVITY NEWS FORUM (global edition), July 2015.
Plenary Presentation PL3 given at ISEC 2015, Nagoya, Japan, July 6 – 9, 2015.
Layout Extraction Tools
Stellenbosch
University
InductEx gives valuable extraction results for
difficult design scenarios [1]
•
•
Layouts with skyplanes, holes and coupling, parasitic coupling, inductors
threading multiple ground planes, large and complicated coils
Especially useful for eSFQ or ERSFQ gates, AQFP gates, layouts in 6+ layer
advanced processes
Several features/improvements added last 2 years
•
•
•
Full-circuit extraction (L, R, JJ area) from schematic netlist and layout files
Optimised solvers for faster calculations (x100 compared to old FastHenry)
New tetrahedral solver for Q4 2015: full impedance, hybrid meshes, chiplevel modelling for bias current distribution and ground return currents.
Rendering of full eSFQ cell meshed with
InductEx for full-circuit extraction.
InductEx
FastHenry
standalone
Lmeter
3D-MLSI
Elements
Rectangular & tetrahedral
Rectangular
Triangular
Triangular
Complexity
3D, holes, vias, multiple
ground/sky planes
3D, holes, vias, multiple
ground/sky planes
Quasi-3D, vias, no sky planes
Quasi-3D (thin layer
assumption), holes,
trapped flux, no vias.
Circuit netlist
extraction
Full circuit, with coupling and
resistance
No
Superconductive only, coupling
not certain, R separately
No
Support
Active, continued development
No
No
Active, continued
development
Speed
Fastest
Slowest
Faster
Slower
CAD integration
Cadence, LayoutEditor, custom
No
Cadence
No
Extras
Magnetic fields, current
density, outputs to MATLAB
Current density
None
Current density
Courtesy of C. Fourie
[1] C. J. Fourie, “Full-gate verification of superconducting integrated circuit layouts with InductEx,” IEEE Trans. Appl. Supercond., vol. 25, 1300209, 2015
.
42
IEEE/CSC SUPERCONDUCTIVITY NEWS FORUM (global edition), July 2015.
Plenary Presentation PL3 given at ISEC 2015, Nagoya, Japan, July 6 – 9, 2015.
Layout Versus Schematic: ERSFQ Confluence Buffer
Layout Netlist
Layout Netlist
The bias JJ is
netlisted as a resistor
Schematic Netlist
The current source is
netlisted as a resistor

Features automated connectivity and parameter
verification at the cell and block levels.


Verification at the chip level is currently being tested.
Limitation: Inductances are estimated from inductor
geometry and sheet inductance value. Proper
extraction of inductances should be performed
separately with InductEx.
Courtesy of A. Inamdar
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
d
i
i
i
i
i
i
i
d
i
d
i
i
i
i
i
t
t
t
t
t
Schematic Netlist
0 GND!
1 /21
2 /20
3 /19
4 /18
5 /17
6 /16
7 /15
8 /14
9 /13
10 /VDD!:2
11 /VDD!:3
12 /bin:1
13 /ain:2
14 /bin:2
15 /ain:1
16 /VDD!
17 /bin
18 /cbout
20 /ain
21 /VDD!:1
inductor UP DOWN (p DOWN UP) "L 1"
0 inductor 18 21 "L 0.864169"
1 inductor 21 10 "L 1.93339"
2 inductor 10 11 "L 0.245658"
3 inductor 12 14 "L 0.0773146"
4 inductor 15 13 "L 0.0665014"
5 inductor 14 17 "L 0.872166"
6 inductor 13 20 "L 0.784862"
resistor UP DOWN (p DOWN UP) "R 1"
7 resistor 10 16 "R 2.44264"
jjunction UP DOWN (p DOWN UP) "Ic 1"
8 jjunction 21 0 "Ic 2.07127"
9 jjunction 14 0 "Ic 2.07127"
10 jjunction 13 0 "Ic 2.07127"
11 jjunction 12 11 "Ic 1.9593"
12 jjunction 15 11 "Ic 1.9593"
0
"GND!"
inputOutput
16
"VDD!"
inputOutput
20
"ain"
input
17
"bin"
input
18
"cbout"
output
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
d
i
i
i
i
d
i
i
i
i
i
d
i
i
i
i
i
i
i
d
i
t
t
t
t
t
1 VDD!
0 GND!
2 /net022
3 /net9
4 /net35
5 /net026
6 /net36
7 /net030
9 /net16
10 /ain
11 /bin
12 /net32
13 /cbout
14 /net26
15 /net19
17 /net024
inductorp UP DOWN (p DOWN UP) "L 1"
0 inductorp 2 0
"L 0.05"
1 inductorp 5 0
"L 0.05"
2 inductorp 7 0
"L 0.05"
3 inductorp 17 3
"L 0.05"
jjunction UP DOWN (p DOWN UP) "Ic 1"
4 jjunction 4 5
"Ic 2.01"
5 jjunction 15 7
"Ic 2.01"
6 jjunction 14 12
"Ic 1.9"
7 jjunction 14 9
"Ic 1.9"
8 jjunction 6 2
"Ic 2.01"
inductor UP DOWN (p DOWN UP) "L 1"
9 inductor 12 4
"L 0.33"
10 inductor 15 9
"L 0.33"
11 inductor 4 10
"L 0.75"
12 inductor 11 15
"L 0.75"
13 inductor 3 14
"L 0.45"
14 inductor 13 6
"L 0.75"
15 inductor 6 3
"L 1.32"
resistor UP DOWN (p DOWN UP) "R 1"
16 resistor 17 1 "R 2.476185"
11
"bin"
input
13
"cbout"
output
10
"ain"
input
0
"GND!"
global
1
"VDD!"
global
Result: matching netlists
43
IEEE/CSC SUPERCONDUCTIVITY NEWS FORUM (global edition), July 2015.
Plenary Presentation PL3 given at ISEC 2015, Nagoya, Japan, July 6 – 9, 2015.
2015 Fabrication Processes
 Higher integration density:
 reduce all circuits elements (JJs, inductors, JJ shunts, vias)
• Better lithography
• Adding specialty layers: high L layers, high and low R layers
 use vertical direction to layout circuit
• more superconducting layers
• via plugs
 integrated process (JJs + Spintronic elements)
• Integration of SFQ JJ+nanowire
• Integration of SFQ JJ+spintronic devices
• Integration of SFQ JJ+spintronics+nanowire
44
IEEE/CSC SUPERCONDUCTIVITY NEWS FORUM (global edition), July 2015.
Plenary Presentation PL3 given at ISEC 2015, Nagoya, Japan, July 6 – 9, 2015.
Courtesy of M. Johnson
45
IEEE/CSC SUPERCONDUCTIVITY NEWS FORUM (global edition), July 2015.
Plenary Presentation PL3 given at ISEC 2015, Nagoya, Japan, July 6 – 9, 2015.
MIT-LL Fully-Planarized SFQ Process
IARPA C3 Program
SFQ5ee 8-Nb-layer Process
(Fall 2015)
SFQ4ee 8-Nb-layer Process
HSR Resistor
Mo
milliohm
Resistor
Stud
via
2 µm
SFQ4ee Process Features
• Primary 2015 process node
• 10 kA/cm2 (100 µA/µm2)
HKI (bias
inductor)
• Wafer size: 200-mm
• Min wiring feature size: 500 nm
• Min JJ size: 700 nm
To date, test circuits with 72K+ JJs per chip have
been successfully demonstrated in the SFQ4ee
process node.
MIT-LL SFQ46
19 June 2015
• High Kinetic Inductance (HKI) layer: 8 pH/sq
• High Sheet Resistance (HSR) option: 6 Ω/sq
• mΩ resistor
• Min wiring feature size: 350 nm
• Min JJ size: 700 nm
Courtesy of L. Johnson
46
IEEE/CSC SUPERCONDUCTIVITY NEWS FORUM (global edition), July 2015.
Plenary Presentation PL3 given at ISEC 2015, Nagoya, Japan, July 6 – 9, 2015.
Digital chips fabricated by CRAVITY-AIST
Name
# of Nb
layers
Jc
(kA/cm2)
Minimum JJ
(µm2)
Minimum
line width
(µm)
Chip
size
(mm)
Fabrication
period
(week)
# of mask
releases
in FY2014
# of
delivered
chips in
FY2014
ADP2
9
10
1.0
1.0
7.1×
7.1
4∼6
4
1007
HSTP
4
10
1.0
1.0
7.1×
7.1
1∼2
4
840
STP2
4
2.5
4.0
1.5
5×5
1∼2
4
1554
ADP2
STP2
HSTP device structure
is almost same as STP2
one except the JJ
surround area (specific
JJ implementation)
Courtesy of M. Hidaka
47
IEEE/CSC SUPERCONDUCTIVITY NEWS FORUM (global edition), July 2015.
Plenary Presentation PL3 given at ISEC 2015, Nagoya, Japan, July 6 – 9, 2015.
Developing process in CRAVITY-AIST
To higher Jc and smaller JJ
MF-P01-INV
2
JJ areas less than 1 µm using i-line stepper were achieved
by accurate control of shrinkage
To larger scale SFQ circuits
We experimentally demonstrated
that fine particles underneath
Nb/AlOx/Nb JJs produce leakage
current in the JJs.
MF-P06
To double JJ layer device
CMP polishing conditions were optimized
to fabricate better quality under-layer JJs
supplementary planarization
supplementary planarization
GP2
CTL2
CC2
COU2
GC2
CC2
SiO2
BAS2
RES2 RC2
CG
BC1
BAS1
RC1
RES1
SiO2
AlOx
JJ1
RC1
RC1
GP1
Si / SiO2 Substrate
RES1
RES1
RC1
BC1
BAS1
SiO2
AlOx
JJ1
RC1
RC1
RES1
RC1
BC1
BAS1
Si / SiO2 Substrate
CG
COU1
JC1
RC1
CG
COU1
JC1
GP1
GC2
GC2
CG
GC1
GC1
SiO2
BAS2
GP2
COU1
BC1
BC2
BC2
AlOx
JJ2
RC2
CG
COU1
BAS1
COU2
COU2
JC2
BC2
CG
CTL2
wafer 1
wafer 2
0.3
Current (mA)
CTL2
DS-P19
0.2
0.1
0.0
0.0
1.0
2.0
3.0
Voltage (V)
Courtesy of M. Hidaka
The number of leak JJs with 20×20 µm area.
Measured JJs in a wafer is about 7,000.
48
IEEE/CSC SUPERCONDUCTIVITY NEWS FORUM (global edition), July 2015.
Plenary Presentation PL3 given at ISEC 2015, Nagoya, Japan, July 6 – 9, 2015.
HYPRES Processes since 2014 and beyond
ALL process including the legacy process are now offered on the 248 nm, deepUV photo-lithography on a 5x reduction stepper
 Critical dimensions:
 Josephson junction, lines and spaces ≥ 0.5 µm
 Via size ≥ 1.0 µm
Number of Layer
Process
LP-3
LP-2
LP-1
RIPPLE-1
RIPPLE-2
RIPPLE-4
RIPPLE-6
Max Realized Max planned
4
5
4
5
4
6
5
6
6
8
planned
10
planned
12
Critical current density
Max Realized
< 100 A/cm2
1 kA/cm2
4.5 kA/cm2
4.5 kA/cm2
10 kA/cm2
planned
planned
Max planned
500 A/cm2
1.0 kA/cm2
10 kA/cm2
>20 kA/cm2
>20 kA/cm2
>20 kA/cm2
>20 kA/cm2
49
IEEE/CSC SUPERCONDUCTIVITY NEWS FORUM (global edition), July 2015.
Plenary Presentation PL3 given at ISEC 2015, Nagoya, Japan, July 6 – 9, 2015.
Integrated Memory Process
Based on the currently available optimized processes
JJs
R3
M3 = 600 nm
M2
M1
M0 = 200 nm
MN1
TE / MN2
Nano-wire
BE
Memory
array
Substrate
50
IEEE/CSC SUPERCONDUCTIVITY NEWS FORUM (global edition), July 2015.
Plenary Presentation PL3 given at ISEC 2015, Nagoya, Japan, July 6 – 9, 2015.
Integrated Memory Process Progress
M3, 600 nm
M2, 300 nm
nTron+SFQ
R2, 40 nm
M1, 135 nm
M0, 100 nm
Courtesy of D. Yohannes
51
IEEE/CSC SUPERCONDUCTIVITY NEWS FORUM (global edition), July 2015.
Plenary Presentation PL3 given at ISEC 2015, Nagoya, Japan, July 6 – 9, 2015.
Self-Shunted JJs: Co-sputtering NbxSi1-x
Vary Composition:
Changes barrier
resistivity
x≈9%
• In-situ co-sputtered in high
vacuum
• Control composition and
thickness
• Tune Barriers
• Ic and Rn independently
• Barriers are several to tens
of nanometers thick
Underdamped
Critically damped
Overdamped
Courtesy of S. Benz, D. Olaya
52
IEEE/CSC SUPERCONDUCTIVITY NEWS FORUM (global edition), July 2015.
Plenary Presentation PL3 given at ISEC 2015, Nagoya, Japan, July 6 – 9, 2015.
Vertical NbSi JJ Stacks
8-JJ Stack Test structure
1
μm
3-JJ stacks used in voltage standard circuits
400 nm
Non-planarized process
(s)
Precise control of etch
with laser endpoint
C4F8/SF6 ICP/RIE etch yields vertical profile → Uniformity of JJs in stack
1. Self-shunted NbSi JJs eliminate
need for shunt resistors
2. Relatively thick barriers allow for
uniform high-Jc JJs
3. Josephson kinetic inductance of



Substantial increase in circuit density
Eliminate parasitic inductances
Increase operating margins and yield
NbSi JJ stacks can replace inductors
Courtesy of S. Benz, D. Olaya
53
IEEE/CSC SUPERCONDUCTIVITY NEWS FORUM (global edition), July 2015.
Plenary Presentation PL3 given at ISEC 2015, Nagoya, Japan, July 6 – 9, 2015.
Cryocooling
 Different Use – different cryosystem options:
 Testing
• Device R&D
– Liquid He, single-chip cryocoolers setup is acceptable
• Circuit Development and optimization
– Multi-chip cryocooler setup, rapid reloading is a priority
• Product Development and production
– Wafer-scale cryoprober is required
 Application
• Small scale (Digital-RF receivers, sensors, etc.)
– Circuit performance is a priority, cryocooler lower energy-efficiency is
acceptable
• Large scale (high-end computing)
– Cryocooler energy-efficiency is a priority
54
IEEE/CSC SUPERCONDUCTIVITY NEWS FORUM (global edition), July 2015.
Plenary Presentation PL3 given at ISEC 2015, Nagoya, Japan, July 6 – 9, 2015.
Rapid Testing: ICE-T
ICE-T: Integrated Cryo-Electronic Testbed
 ICE-T with one or two electrical inserts and optional accessories provides
complete infrastructure for testing superconductor ICs
• ICE-T accommodates two
independent interchangeable
Electrical Inserts
 Universal inserts with 40 and 80 coaxial
cables for superconductor IC testing
 Universal insert with 120 low-speed
lines for three 5mm x 5mm ICs
 Custom inserts
1st insert (custom-made
for a US University)
• Turn-key operation with two
native temperature stages at 4K
and 40K and controlled variable
temperature test capability in
custom Electrical Inserts.
 Sumitomo SRDK-415D Cryocooler with
1.5W heat lift at 4.2 K
First ICE-T delivered in
May 2015
Commercially available: [email protected]
55
IEEE/CSC SUPERCONDUCTIVITY NEWS FORUM (global edition), July 2015.
Plenary Presentation PL3 given at ISEC 2015, Nagoya, Japan, July 6 – 9, 2015.
Small-scale Application: Size and Power
Sumitomo RDK-101D
Input: 1.2 kW
Heat Lift @4.2K: 100 mW
Digital-RF receiver cryosystem
Based on 1.5 kW Sumitomo cryocooler (efficiency is ~10,000 W/W)
Still preferred for the application – Size and Absolute Power are priorities
56
IEEE/CSC SUPERCONDUCTIVITY NEWS FORUM (global edition), July 2015.
Plenary Presentation PL3 given at ISEC 2015, Nagoya, Japan, July 6 – 9, 2015.
Large-scale Application: Cryocooling Efficiency
Heat Lift
No Precool
Wall Power
45000
55000
75000
90000
110000
132000
160000
200000
250000
Heat Lift W/W
W/W
W/W
Precool No Precool
Precool Carnot @ 4.2K
0
0
70.43
100
130
450
346
70.43
125
160
440
344
70.43
145
190
517
395
70.43
210
255
429
353
70.43
250
325
440
338
70.43
290
400
455
330
70.43
445
560
360
286
70.43
510
640
392
313
70.43
640
900
391
278
70.43
1000
70.43
25000
70.43
3500
70.43
For large cryocoolers, the
efficiency is improving to
become better than 400 W/W
Large Cooler Efficiency - Linde
Large 4K cryocoolers
are available
commercially from
Linde and Air Liquide
Coefficient of Performance
(COP) W/W
600
500
400
No-PreCool
300
PreCool
200
Carnot @4.2K
100
0
0
Courtesy of E. Track
200
400
600
800
1000
Heat Lift (W) at < 4.4K
57
IEEE/CSC SUPERCONDUCTIVITY NEWS FORUM (global edition), July 2015.
Plenary Presentation PL3 given at ISEC 2015, Nagoya, Japan, July 6 – 9, 2015.
Ultimate Energy-Efficiency
System Comparison (~20 PFLOP/s)
same scale comparison
2’ x 2’
Supercomputer Titan at ORNL - #2 of Top500
Superconducting Supercomputer
Performance
17.6 PFLOP/s (#2 in world*)
20 PFLOP/s
~1x
Memory
710 TB (0.04 B/FLOPS)
5 PB (0.25 B/FLOPS)
7x
Power
8,200 kW avg. (not included: cooling, storage memory)
80 kW total power (includes cooling)
0.01x
Space
4,350 ft2 (404 m2, not including cooling)
~200 ft2 (includes cooling)
0.05x
Cooling
additional power, space and infrastructure required
All cooling shown
* #1 in TOP500, 2012-11 (17.6 PFLOP/s)
From ASC14
Courtesy of M. Manheimer
58
IEEE/CSC SUPERCONDUCTIVITY NEWS FORUM (global edition), July 2015.
Plenary Presentation PL3 given at ISEC 2015, Nagoya, Japan, July 6 – 9, 2015.
Ultimate Performance (Computing Efficiency)
Future supercomputer with superconducting fast nodes, quantum
computing nodes, combined with conventional CMOS nodes.
CMOS
SFQ
QC
SFQ
SFQ
QC
SFQ
QC
CMOS
CMOS
SFQ
CMOS
CMOS
SFQ
Classical superconducting (SFQ) computing node – similar to conventional CMOS node, but faster (@20-60 GHz)
connected to CMOS nodes using optics.
Quantum computing (QC) node – a nested system, in which the QC core is readout, controlled, loaded/unloaded,
corrected using superconducting classical computing circuits, which in turn connected to SFQ and/or CMOS
nodes using optics.
Note: Needs high data rate energy efficicent optical data network
59
IEEE/CSC SUPERCONDUCTIVITY NEWS FORUM (global edition), July 2015.
Plenary Presentation PL3 given at ISEC 2015, Nagoya, Japan, July 6 – 9, 2015.
2015 Digital Superconducting Electronics
1. Lower-power SFQ logic:
• Energy-Efficient Logic (eSFQ, ERSFQ, RQL, LV-RSFQ, AQFP)
2. New memory devices:
• Circuit hybrids with cryospintronic elements
• Superconducting spintronics: superconducting-ferromagnetic Josephson
junctions
• New 3-terminal devices
3. EDA Tools
• High JJ count simulators and optimizers
• Models of new devices (spintronic, nanowire, etc.)
• InductEx – leading inductance extractor tool
4. Fabrication processes complexity
• Optimization for high density: new specialized layers
• Integration of new devices with SFQ circuits
• Multiple JJ layer, stacked JJs
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