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CSICS 26 Oct. 2004
A 49-Gb/s , 7-Tap Transversal Filter
in 0.18 mm SiGe BiCMOS for
Backplane Equalization
Altan Hazneci and Sorin Voinigescu
Edward S. Rogers, Sr. Department of
Electrical & Computer Engineering,
University of Toronto
10 King’s College Rd., Toronto, Ontario,
M5S 3G4, Canada
Outline
• Motivation
• Transversal Filter Block Diagram
• System Simulations
• Design Implementation
• Test and Measurement Results
• Conclusion
Motivation
• backplane applications present demanding design
challenges for data rates exceeding 10 Gb/s
• frequency dependent losses in the backplane limit
broadband communication systems
– the skin effect and dielectric losses dominate
– Intersymbol Interference (ISI)
• enabling chip-to-chip communication over 30-cm of
backplane at 40 Gb/s and over 12-cm long controlled
impedance lines at 100 Gb/s (future)
• enabling intercabinet communication over inexpensive cable
Transversal Filter
• analog Finite Impulse Response (FIR) filter
• Feed Forward Equalizer (FFE)
• continuous time implementation (high speed
operation)
System Simulations
• the following FFE configurations were evaluated
using MATLAB:
– 2 to 7 taps
– baud rate spaced a tap spacing = T (symbol
period)
– fractionally spaced a tap spacing = T/2 or T/4
• 40 Gb/s operation over (a) 30-cm long 50-W
microstrip transmission line on MICROLAM substrate
(b) 9-ft section of cable (RG-174)
• assume TEM mode operation (i.e. no modal
dispersion)
9-ft Cable Insertion Loss
Simulated FFE Output
Number of Taps vs Tap Spacing
• in simulation 2 taps enough to open the eye for the 3
different tap spacings
• 25-ps tap spacing did not appear to benefit from
more than 2-taps
• additional taps, for 12.5-ps & 6.25-ps tap spacing,
increased the recovered eye amplitude
• 7-tap, 6.25-ps tap spacing most versatile
– can be configured as a 2-tap FFE w/ 25-ps tap
spacing
– can be configured as a 4-tap FFE w/ 12.5-ps tap
spacing
SiGe HBTs
• fabricated in Jazz Semiconductor's SBC18,
0.18 µm SiGe BiCMOS technology
• SiGe HBTs with fT and fMAX values of 160 GHz
• peak fT bias current density: 1.2-mA/mm
(IC/le), VBE = 0.9-V
Gain Stage
• core of each gain
stage is a Gilbert
cell
• tail current of the
differential pair
controls the tap
weight (gain pad)
• sp/n pads control
the tap sign
FFE Circuit Layout
Test & Measurement
• the circuit was biased from a single 5-V power supply
and drew 150 mA at the nominal tap settings suitable
for operation as a distributed amplifier
• a custom board provided bias and control signals to
set the tap signs and weights
– 7 programmable current sources (tap weights) + 1
current sink (emitter follower bias)
– 9 programmable voltage sources; tap sign (7),
sign reference (1), input bias (1)
• the board was controlled via a laptop running a
Matlab GUI.
Measured Input & Output Return Loss
Measured Tap Spacing
• phase response of each tap to a 10 GHz sinusoidal signal
• average tap spacing 8-ps, 48-ps total delay
Measured FFE Output
40-Gb/s
43-Gb/s
48-Gb/s
49-Gb/s
• equalization over 9-ft SMA cable (3 x 3-ft)
49-Gb/s FFE
• measured 49 Gb/s input eye after 6.5-ft SMA cable
(left) and equalized output eye (right)
Conclusion
• described the design and experimental
characterization of a 7-tap feed forward equalizer
operating above 40 Gb/s
• the circuit architecture is based on a transversal filter
topology with on-chip microstrip transmission lines
• the performance was verified up to 49 Gb/s (upper
data rate limit of the BERT) using a 231-1 PRBS
signal over a 6.5-ft SMA cable
• the FFE significantly reduces ISI and produces an
open eye at the output despite having a totally closed
input eye at 40 and 49 Gb/s
Acknowledgements
• Timothy Dickson for his invaluable help with
setting up measurements
• Quake Technologies for access to their
43.5 Gb/s BERT and characterization lab
• Marco Racanelli and Paul Kempf of Jazz
Semiconductor
• This work was financially supported by Jazz
Semiconductor, Gennum Corporation, and by
Micronet
Backup Slides
Gain Stage Features
• the cascode differential pair is buffered by two emitter-follower
(EF) stages
• tail currents of the emitter-follower stages are partially controlled
by the diff pair tail current
• resistive padding and local bias decoupling carefully designed to
avoid any negative resistance in the emitter-follower stages and
in the cascode stage
• 6-mA diff pair tail current a peak fT current density of a single
transistor in the diff pair
• EF stages biased at 0.5-0.75 times peak fT current density to
prevent instability
• 5-V supply voltage, 21-mA nominal bias current (max gain)
On-Chip Microstrip Delay Lines
• top-metal lines over metal-2 ground planes
– 12-mm wide a Z0= 50-W
– 500-mm long a 3-ps; one section in input path and one in
output path for a total delay of 6-ps
– input and output end sections are 250-mm long
• why metal-2 ground planes? answer: metal-1 used to route
control signals; ground plane provides isolation
• multi-metal ground planes between adjacent transmission lines
improves isolation; also ensures simultaneous single-ended and
differential matching is maintained
• serpentine microstrip layout to minimize the area
• microstrip transmission lines in the output path also combine the
weighted outputs of each tap
Eye Diagram Measurements
• the circuit was operated single-endedly and the
unused ports were terminated off chip
• equalization was obtained by manually adjusting the
gain and sign of the 7 taps through the Matlab GUI
• eye diagrams were measured on die, using an
Anritsu MP1801A 43.5-Gb/s BERT and an Agilent
786100A DCA with the 86118A 70-GHz dual remote
sampling head and external timebase
• operation up to 49-Gb/s (beyond the factory-specified
range of the BERT) was verified by applying a 231-1
PRBS signal to the input of the equalizer through a
16-dB power attenuator and a section of SMA cable