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CHAPTER 1
INTRODUCTION
All real world signals are analog. The processing is, however, done in
the digital domain for most applications. Hence a good interface, an Analog
to Digital Converter (ADC) is very much essential.
There are 2 types of data converters: Nyquist Rate converters and
Oversampling data converters (ODC). The difference is that, while the
former samples the input signal at the Nyquist frequency, the latter samples
it at a very high frequency. The multiplicative factor is called the over
sampling ratio. The Delta Sigma Modulator (DSM) falls under the second
category. The advantage is that, a single bit ADC put in a feedback loop can
simulate the performance of a 16 bit ADC. This reduces the number of
components on the chip and thus the area.
The idea behind the DSM is that the signal and the noise are made to
see different transfer functions. The non linear ADC is modeled as a linear
ADC with uniformly distributed white noise added to it. The signal sees a
unity gain while the noise is high pass filtered. When the output is passed
through a low pass filter, the SNR increases; while the signal is unchanged,
the noise in the signal band has decreased.
A second order loop filter consisting of two integrators have been
used, in order to get a high SNR. Timing issues are crucial for the correct
1
implementation of the DSM difference equations and therefore, the
functioning of the circuit. Finally, Boser-Wooley feedback architecture has
been used since stability will not be affected for the second order modulator,
even if the coefficient at the input of the 2nd integrator is slightly altered. The
entire system has been implemented in 180nm technology.
A complete MATLAB simulation was done. The MATLAB
coefficients were translated to capacitor ratios by solving difference
equations, in order to be implemented in the circuit. It was followed by the
design of the individual blocks such as the first and the second integrator,
the operational amplifier and latched comparator. The design was verified by
plotting the impulse response of the loop filter. The complete ideal DSM
simulation was done and the Power Spectral Density (PSD) was calculated
and plotted.
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CHAPTER 2
OVERVIEW OF ADC’S
2.1 TYPES OF ADC

FLASH ADC

PIPELINED ADC

SUCCESSIVE APPROXIMATION ADC

INTEGRATING ADC

RAMP-COMPARE ADC

TIME INTERLEAVED ADC

SIGMA-DELTA ADC
2.2 FLASH ADC
The flash ADC is the fastest type available in the world. A flash ADC
uses comparators, and a string of resistors. A 4-bit ADC will have 16
comparators, an 8-bit ADC will have 256 comparators. Generally N-bit
ADC will have 2N comparators. All of the comparator outputs connect to a
block of logic that determines the output based on which comparators are
low and which are high.
The conversion speed of the flash ADC is the sum of the comparator
delays and the logic delay (the logic delay is usually negligible). Flash
ADCs are very fast, but the disadvantage is that they consume enormous
amounts of area and power.
3
2.3 SUCCESIVE APPROXIMATION CONVERTER
A successive approximation converter uses a comparator and counting
logic to perform a conversion. The first step in the conversion is to check
whether the input is greater than half the reference voltage. If it is, the most
significant bit (MSB) of the output is set. This value is then subtracted from
the input, and the result is checked for one quarter of the reference voltage.
This process continues until all the output bits have been set or reset. A
successive approximation ADC takes as many clock cycles as there are
output bits to perform a conversion.
2.4 PIPELINED ADC
Pipeline ADC (also called sub ranging quantizer) uses two or more
steps of sub ranging. First, a coarse conversion is done. In a second step, the
difference to the input signal is determined with a digital to analog converter
(DAC). This difference is then converted finer, and the results are combined
in a last step. This can be considered a refinement of the successive
approximation ADC wherein the feedback reference signal consists of the
interim conversion of a whole range of bits (for example, four bits) rather
than just the next-most-significant bit. By combining the merits of the
successive approximation and flash ADCs this type is fast, has a high
resolution, and only requires a small die size.
2.5 INTEGRATING ADC
Integrating ADC (also dual-slope or multi-slope ADC) applies the
unknown input voltage to the input of an integrator and allows the voltage to
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ramp for a fixed time period (the run-up period). Then a known reference
voltage of opposite polarity is applied to the integrator and is allowed to
ramp until the integrator output returns to zero (the run-down period). The
input voltage is computed as a function of the reference voltage, the constant
run-up time period, and the measured run-down time period. The run-down
time measurement is usually made in units of the converter's clock, so longer
integration times allow for higher resolutions. Likewise, the speed of the
converter can be improved by sacrificing resolution. Converters of this type
(or variations on the concept) are used in most digital voltmeters for their
linearity and flexibility.
2.6 RAMP-COMPARE ADC
Ramp-compare ADC produces a saw-tooth signal that ramps up, then
quickly falls to zero. When the ramp starts, a timer starts counting. When the
ramp voltage matches the input, a comparator fires, and the timer's value is
recorded. Timed ramp converters require the least number of transistors. The
ramp time is sensitive to temperature because the circuit generating the ramp
is often just some simple oscillator. There are two solutions: use a clocked
counter driving a DAC and then use the comparator to preserve the counter's
value, or calibrate the timed ramp. A special advantage of the ramp-compare
system is that comparing a second signal just requires another comparator,
and another register to store the voltage value. A very simple (non-linear)
ramp-converter can be implemented with a microcontroller and one resistor
and capacitor. Vice versa a filled capacitor can be taken from an integrator,
time-to-amplitude converter, phase detector, sample and hold circuit, or peak
5
and hold circuit and discharged. This has the advantage that a slow
comparator cannot be disturbed by fast input changes.
2.7 TIME INTERLEAVED ADC
Time-interleaved ADC uses M parallel ADCs where each ADC
sample data every Mth cycle of the effective sample clock. This result is that
the sample rate is increased M times compared to what each individual ADC
can manage. In practice the individual differences between the M ADCs
degrade the overall performance. However, technologies exist to correct for
these time-interleaving mismatch errors.
2.8 SIGMA-DELTA ADC
The sigma-delta circuits are used in applications requiring very high
resolution at low speeds bits at 500Hz and audio converters (16 or more bits
at 44 KHz), and they often work with very modest power budgets (2.3mW
for an audio coder. For high resolution and/or low power at fairly low speeds
(up to a few hundred KHz), Delta-Sigma Modulators (DSM) is the best
ADC architecture choice.
The vast majority of delta sigma modulators have been built with
Discrete-Time (DT) circuitry, very often switched-capacitor circuits. If
circuit waveforms are to be allowed adequate settling time, the speed at
which DT circuits are clocked must be restricted. These restrictions can be
relaxed by employing Continuous-Time (CT) circuitry in place of DT
circuitry. DSM has resolution and power advantages over ADCs. DSM
6
could retain these advantages even while operating at higher speed, this has
been given increasing attention in the last few years as the need for highresolution ADC at ever-higher speeds grows.
Delta sigma modulation is well suited for high-resolution analog-todigital conversion since only modest demands are made on the accuracy of
passive devices. Oversampling is used to shape the quantization noise from a
coarse quantizer outside the signal band. The reasons why Continuous-Time
Delta Sigma Modulators (CT-DSMs) are attractive are the following. The
bandwidth requirements of the active elements are greatly reduced when
compared with a switched-capacitor implementation, thereby resulting in
significant power savings. CT-DSMs also offer implicit anti-aliasing. Power
reduction is a key motivator for using DSMs for digitizing low-frequency
analog signals. Several implementations targeting the audio range have been
reported recently. The first three of these designs use a single-bit quantizer.
2.9 APPLICATIONS OF DELTA-SIGMA MODULATORS
 Pulse Width Modulation (PWM)
 Music reproduction Technology (DOLBY)
 Microcontrollers
 Digital Oscilloscopes
 Digital Video Cameras
 Video Capture Cards
 Voltage Monitor
 A part of low-speed on-chip calibration engine
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CHAPTER 3
BASICS OF SIGMA-DELTA CONCEPTS
3.1 DELTA SIGMA MODULATOR
Delta sigma modulator uses the concept of oversampling and
noise
shaping. In delta sigma ADCs the sampling is done at a higher rate than the
Nyquist rate to achieve higher resolution. Noise shaping is done by using a
ADC in feedback to reduce the in band quantization noise and increase the
out of band quantization noise thereby resulting in high SNR.
3.2 OPERATING PRINCIPLES
A delta-sigma ADC has three important components, depicted in
Figure.3.1
1. A loop filter or loop transfer function H (z).
2. A clocked quantizer.
3. A feedback digital-to-analog converter (DAC).
fs
x
H(Z)
U
Y
DAC
Figure.3.1 Components of a basic delta-sigma modulator
8
The basic idea of delta sigma modulation is that the analog input
signal is modulated into a digital word sequence with a spectrum that
approximates that of the analog input well in a narrow frequency range and
has the quantization noise “shaped” away from this range. Linearising the
circuit the quantizer is replaced by an adder as shown in Figure.3.2
e
x
H(Z)
U
Y
DAC
Figure.3.2 Linearising the ADC in delta sigma modulator
The quantization noise is generated by an input e which is
independent of the circuit input u. The output y may now be written in terms
of the two inputs u and e as
H(z) .U(z)
1
.E(z)
+
1 + H(z)
1 + H(z)
= STF(z) .U(z) + NTF(z) .E(z)
Y(z) =
Where STF(z) and NTF(z) are the Signal Transfer Function and Noise
Transfer Function. The poles of H(z) become the zeros of NTF(z) for any
frequency where H(z) >> 1,
Y (z) ≈ U(z):
In other words, the output resembles the input most closely at frequencies
where the gain of H(z) is large.
9
3.3 OVERSAMPLING
A delta-sigma ADC is also known as an oversampling data converter.
All other ADCs are sampled at the Nyquist rate. Hence they are called as
Nyquist rate ADCs. In sigma-delta ADCs, however, the sampling is
performed at a much higher rate than the Nyquist rate. The ratio of the
sampling rate to the Nyquist rate is called the Over Sampling Ratio (OSR).
Doubling the oversampling ratio reduces the quantization noise power
resulting in 3dB SNR improvement.
In a given application, the signal bandwidth fin is usually fixed.
Sampling faster than the Nyquist rate is always beneficial for improving the
signal-to-noise ratio (SNR) in an ADC because the quantization noise inside
the signal band is reduced by 3dB per octave of oversampling; in an delta
sigma modulator, this improvement can be shown to be 6m + 3dB/oct
(where m is the number of bits used for quantization) because the noise is
shaped by the loop filter. Thus, a high-order modulator is desirable because
of the huge increase in converter dynamic range (DR) obtained from each
doubling of the OSR[8].
Antialaising
filter
|X(f)|
Fb
Fs/2
Fs
Fig.3.3 Oversampling
10
F
Using a high-order modulator has drawbacks. First, the stability of the
overall system with H(z) above order two becomes conditional: input signals
whose amplitudes are below but close to full scale can cause overload at the
output of the integrators closer to the quantizer. As well, the placement of
the poles and zeros of H(z) becomes a complicated problem. Finally, the
design of the decimator increases in complexity and area for larger
oversampling ratios. Typical values of OSR lie in the range 32–256[8].
3.4 ADVANTAGES OF OVERSAMPLING
 Sample at fs >> 2fin.
 Oversampling ratio OSR = fs/2fin.
 Filter the noise using a filter of bandwidth fb = fs/(2*OSR).
2
 Mean squared value of error = VLSB
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OSR
 Increased signal to quantization noise ratio.
 Lower order anti-aliasing filter can be used
3.5 QUANTIZER RESOLUTION
It is possible to replace the single-bit quantizer with a multibit
quantizer, e.g., a flash converter. This has two major benefits: it improves
overall delta sigma modulators resolution and it tends to make higher-order
modulators more stable. Furthermore, nonidealities in the quantizer (e.g.,
slightly misplaced levels or hysteresis) don’t degrade performance much
because the quantizer is preceded by several high-gain integrators, hence the
input-referred error is small. Its two major drawbacks are the increase in
complexity of a multibit versus a one-bit quantizer, and that the feedback
DAC nonidealities are directly input-referred so that a slight error in one
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DAC level corrupts converter performance greatly[7]. There exist methods
to compensate for multibit DAC level errors. These aren’t needed in a
single-bit design because one-bit quantizers are inherently linear. Even if
these two levels are imprecise, the result is only offset and gain which is
tolerable in DSM.
3.6 NOISE SHAPING
In Delta Sigma Modulator the noise is shaped so that most of the
noise is concentrated only in the high frequency region. By noise shaping the
in band quantization noise is minimized and the out of band quantization
noise is maximized. If the noise is not shaped then when sampling is done,
the noise gets added and the signal component becomes difficult to be
differentiated from noise. So the noise is shaped such the in band noise is
very small and when filtered using a low pass filter the signal component
can be obtained with very low noise. This increases the SNR ratio.
Ideal digital low pass filter
Noise
Shaping
function
Fb
frequency
Fs/2
Figure.3.4 First order noise shaping
The quantization noise spectrum of a typical Nyquist type converter
and the theoretical SNR of such a converter is given in Figure 3.5. Figure.3.6
12
shows the effects of oversampling, fs/2 is much greater than 2fin and the
quantization noise is spread over a wider spectrum. The total quantization
noise is still the same but the quantization noise in the bandwidth of interest
is greatly reduced. Figure.3.6 illustrates the noise shaping of the over
sampled sigma delta modulator. Again the total quantization noise of the
converter is the same as in Figure.3.6, but the in-band quantization noise is
greatly reduced[9].
SNR= (6.02N+1.76)dB
N=Number of bits
fc=Maximum frequency of interest
fs= Sampling frequency
Quantization
noise
fc
Fs/2
Frequency
Figure.3.5 Nyquist converter quantization noise spectrum
SNR= (6.02N+1.76)dB + 10 log(fs/fc)dB
Frequency
of interest
N=Number of bits
fc=Maximum frequency of interest
fs= Sampling frequency
Quantization
noise
fc
fs
Frequency
Figure.3.6 Over sampled quantization noise spectrum
13
3.7 NOISE SHAPING USING FEEDBACK
E(Z)
A(Z)
X(Z)
Y(Z)
DAC
Fig.3.7 Second order modulator
Y(z) = E(z) + A(z) X(z) - A(z) Y(z)
X(z) (A(z)
1
= E(z)
+
1 + A(z)
1 + A(z)
= E(z) He(z) + X(z) Hx(z)
NOISE TRANSFER FUNCTION:
H(z) =
1
1 + A(z)
SIGNAL TRANSFER FUNCTION:
H(z) =
A(z)
1 + A(z)
If the frequency band of interest is around DC (0 , …. , fb), then by
making A(z) >> 1 , we have :
STF(z) ≈ 1 ; NTF(z) < < 1
14
3.8 MATLAB RESULTS:
Quantizer output
Input signal
Low pass filtered signal
Figure.3.8 Output of DSM
It can be seen that the number of transitions in the output is more
when the instantaneous frequency of the sine wave increases ( i.e. the rising
and falling portions of the sine wave ). Similarly, the number of transitions is
less at the output in the maximum and minimum portions of the sine wave
since the instantaneous frequency is less. Hence it can also be said that Delta
Sigma ADC can also be used for Pulse Width Modulation (PWM).
FFT of input signal
Figure.3.9 FFT plot of the input signal
15
FFT of output signal
Figure.3.10 FFT plot of the low pass filtered signal
The quantized output is sent through a low pass filter for checking
purposes. The FFT plot of both the input fig.3.9 and the low pass filtered
signal fig 3.10 shows that both have the same frequency component in the
frequency bin.
Spectrum
Shaped noise
Figure.3.11 Signal and the noise spectrum
16
From Figure.3.11 it can be seen that the in band quantization noise is
reduced and the out of band quantization noise is increased thereby shaping
the noise as high pass filtered and increasing the SNR. SNR of 98.08dB
(actual SNR of 16 bit ADC) is achieved by using a 1 bit ADC using DSM
techniques.
3.9 MATLAB COEFFICIENTS
U
V
Figure.3.12 Block diagram of second order Delta Sigma modulator
The coefficients a1, a2, b1, c1, c2 has to be designed carefully to
maintain the system to be a stable one. The values have been found using
MATLAB simulation. All the coefficients has to be low for the system to be
stable. c3 is found to be high since it is present at the end of the system and
also it is the input to the comparator, it does not affect the system stability.
17
Using these coefficients as poles and zeros, the signal transfer
function and the noise transfer function is calculated.
The signal transfer is the ratio of the output to input signal and the
noise transfer function is the ratio of output to input white noise. The
sampling time has been normalized to 1 so that the desired frequency can be
obtained just by multiplying the normalized value and the frequency.
18
CHAPTER 4
SECOND ORDER DELTA-SIGMA ADC
4.1 DESIGN SPECIFICATIONS OF DSM
The design of a 16-bit Delta-Sigma Modulator (DSM) for audio
applications is described. The modulator has bee designed using 0.18 micro
meter technology with 1.8 V supply and achieves a SNR of 98.06 dB for a
signal bandwidth of 4 KHz. The modulator operates with an oversampling
ratio (OSR) of 128. The DSM employs several strategies to reduce power
consumption. A large input signal swing (1.8 V peak-to-peak differential ) is
used to reduce noise requirements of the op-amps and telescopic cascoded
operational amplifier.
4.2 FIRST INTEGRATOR
A differential circuit with a single-ended input is assumed. Since
a1=b1, the same physical capacitor C1 can be used to implement both
coefficients. As shown in Figure.4.1 the input signal is sampled onto the
upper C1 input capacitor on phase 2, and then the difference between the
input and reference is integrated onto the upper C2 integrating capacitor on
the next phase 1. The lower path feeds the inverted signal to the integrating
capacitor also in phase 1, but samples the input on phase 1 and the reference
on phase 2 in order to accomplish the inversion. The fact that the input is
sampled twice per period adds a (1+z-1/2)/2 factor to the STF, which creates a
zero at fs but has little impact on two clock phases, so we have to ensure that
the feedback signal(v) has the same value in both phases. Fortunately, the
flip flop which holds v constant from phase 2 to phase 1 realizes the required
timing[8].
19
Figure.4.1 First integrator
4.3 SECOND INTEGRATOR
In the first integrator, the input and reference feedback capacitors
were shared since the associated coefficients (b1 and a1) were equal.
However, the two input coefficients (c1 and a2) associated with the second
integrator are not equal, and so are implemented with separate branches as
shown in Figure 4.2
Figure.4.2 Second integrator
Figure 4.3 and Figure 4.4 shows the output of the loop filter for two
different values of Vd, where Vd is the output from D Flipflop. Figure 4.3 is
the output for the Vd sequence {0, 1, 0, 1} and Figure 4.4 is the output for
the Vd sequence {1, 1, 0, 1}.
20
Vd
V[1]
V[2]
V[v(x2a+)-v(x2a-)]
V[v(x1+)-v(x1-)]
Figure.4.3. Loop filter output for Vd = {0, 1, 0, 1}
Vd
V[1]
V[2]
V[v(x1+)-v(x1-)]
V[v(x2b+)-v(x2b-)]
Figure.4.4. Loop filter output for Vd = {1, 1, 0, 1}
Figure 4.5 shows the impulse response. It is obtained by subtracting
the output values obtained for two sequence of Vd.
21
V[v(x2a+)-v(x2a-)] - V[v(x2b+)-v(x2b-)]
Figure.4.5. Impulse response
4.4 CAPACITOR SCALING
Another common source of the error in the translation of a block
diagram into practical circuit is the process of denormalisation and scaling.
The default scaling for integrator states occupy [-1,1 ] range.
Figure.4.6 capacitor scaling of first integrator
X1 
Vx1
1V
,U
Vin  1.5V
1.5V
, V  2Vd  1
The difference equation that have to be implemented is
X 1(n  1)  X 1(n)  b1U (n)  a1V (n)
where a1 =b1 =1/4. In terms of the circuit variables, the desired
difference equation becomes
22
Vx1(n  1) Vx1(n) 
= vx1(n) 
b1Vin(n)  1.5V 
 a12Vd (n)  1.1V
1.5
Vin(n)
 0.5V .Vd (n)
6
If Vin is assumed to be unchanged from phase 2 to phase 1, the
equation implemented is
Vx1(n  1)  Vx1(n) 
2C1
2C1
Vin(n) 
VDD.Vd (n)
C2
C2
Thus in order for the previous 2 equations to be equivalent, the ratio
of the input and integrating capacitances needs to be
C1
C2
1
12
Figure.4.7 capacitor scaling of second integrator
With VDD= 1.8V, the common mode voltage is 0.9V so the capacitor
values are in the ratio C1:C2:C3 is 5:12:36
4.5 NON OVERLAPPING CLOCK GENERATOR:
In general we assume that CLK bar is a perfect inversion of CLK, or
in other words, that the delay of the generating inverter is zero. But
practically variations can exist in the wires used to route the two clock
signals, or the load capacitances can vary based on data stored in the
connecting latches. This causes both clock and clock bar to be high (1-1)
23
overlap or low (0-0) overlap for a momentary period of time. This effect is
known as clock skew. Clock skew is a major problem which is not desirable
in a circuit as static power dissipation is more, and causes the two clock
signals to overlap[2]. Non overlapping clock generator has been shown in
Figure.4.8
Figure.4.8 Non overlapping clock generator
V[1]
V[2]
Figure.4.9 waveform of non overlapping clock
4.6 TIMING
The most common source of error in switched-capacitor modulator
design is proper timing[3]. It is imperative that the timing of the quantization
and feedback operations be such that the loop filter follows the desired
difference equations, otherwise the modulator will not function as desired.
To verify that the timing diagram is correct, the loop filter implementing the
desired difference equations should be verified. Starting at the end of phase
2, x2(n) has just settled and thus strobing the comparator as phase 2 falls will
24
implement the quantization operation implied by the third equation. The next
rising edge of phase 2 causes x2(n+1) to be generated using x1(n) and v(n) as
dictated by the difference equation. The subsequent phase 1 interval is used
to generate x1(n+1) in accordance with the first difference equation. Since
v(n) is needed for both of these operations, a flip-flop clocked on falling
phase 1 holds v(n) over a phase-2/phase-1 interval and thus the timing
shown is consistent with the desired difference equations[8]. The advantage
of this timing diagram is that the comparator and both the integrators have
an entire clock phase or nearly half of the clock period.
Figure.4.10. Timing diagram for second order DSM
4.7 LATCHED COMPARATOR AND D FLIPFLOP:
To understand its working, consider the V+ input to be greater
than V-. In figure 4.11, when clock 2 is high, both R and S are low.
Meanwhile, MOSFET M1 is off and M4 is on. Hence the node B goes high
and node A remains at low voltage. During the other half of the clock cycle,
i.e. when 2 bar goes high, the voltage at nodes R and S are that of the nodes
A and B respectively. Hence Set is high and Reset is low for (V+) > (V-). For
25
(V+) < (V-), Set is low and Reset is high. The D flip flop is used in order to
store the value at R and S outputs for a clock cycle and also to remove the
jitters.
Vm
Vp
R
S
S
R
To D flipflop
Figure.4.11. Latched comparator and D flipflop
V(qm)
V(vp)
V(vm)
V(2)
Figure.4.12. Output of latched comparator
Figure.4.12 shows the output of the latch comparator. When V[2] is
high and V(vp) is also high the output is also high.
26
Input to
Dff
V(qm)
V(R)
V(S)
V(2)
Figure.4.13. Output of RS latch and D flipflop
Figure.4.13 shows the output of the RS latch and D flipflop. The
output of the RS latch is passed as input to the D flipflop to remove the
glitches present in the output of RS latch.
4.8 COMPLETE SCHEMATIC:
Vin2-
Vin2
VDD
1
clk Non
2
overlapping
clock
1
2
vd
vin
1bar
1
1bar
2
2bar
vin2
Loop
filter
clk
vin
comparator
VSS
VDD
Vd
VSS
2bar
2
Figure.4.14. Complete schematic of the second order Delta-Sigma ADC
27
CHAPTER 5
OP-AMP
5.1 OP-AMP ARCHITECTURES
There are many op-amp architectures available. Some of the
commonly used architectures are compared below.
Table 5.1 Comparison of various op-amp architectures
Topology
Gain
Output Swing Speed
Power
Consumption
Telescopic
Medium Medium
Highest
Lowest
Folded Cascode
Medium Medium
High
Medium
Two Stage
High
Highest
Low
Medium
Gain Boosted
High
Medium
Medium
High
Cascode
5.2 NEED FOR FULLY DIFFERENTIAL AMPLIFIER
1. Increased noise immunity, invariably, when signals are routed
from one place to another, noise is coupled into the wiring. In a
differential system, keeping the transport wires as close as
possible to one another makes the noise coupled into conductor
appears as a common mode voltage. Noise that is common to
the power supplies also appears as a common-mode voltage.
Since the differential amplifier rejects common-mode voltages,
the system is more immune to external noise[6].
28
2. Increased output voltage swings, due to change in phase
between the differential outputs, the output voltage swing
increases by a factor of 2 over a single ended output with the
same voltage swing. This makes them ideal for low voltage
applications.
3. Reduced even order harmonics, expanding the transfer
functions of circuits into a power series is a typical way to
quantify the distortion products.
4. Fully differential amplifier has large output dynamic range, due
to its noise immune property[5].
5. The differential pair provides a built-in level shift that allows
for all NMOS devices in the signal path. This would allow for a
rough 2X increase in speed for the same power, or a decrease in
power for the same speed.
6. Fully differential telescopic op-amp consumes much less power
than their counter folded cascode fully differential op-amp.
5.3 APPLICATIONS OF FULLY DIFFERENTIAL AMPLIFIER
1. Digitally programmable voltage gain amplifier.
2. Fully differential amplifier can be used as pipeline ADC stage.
3. Telescopic fully differential op-amp is employed as main stage
of CMOS ADC.
4. Switched-capacitor filter.
5. Radio frequency modulator and audio systems.
6. Fully differential op-amp use in Delta-Sigma modulator.
29
5.4 TELESCOPIC CASCODE OPAMP
Cascode configurations may be used to increase the voltage gain of
CMOS transistor amplifier stages. This structure has been called a
telescopic-cascode op-amp because the cascode are connected between the
power supplies in series with the transistors in the differential pair, resulting
in a structure in which the transistors in each branch are connected along a
straight line. The main potential advantage of telescopic cascode op-amps is
that they can be designed so that the signal variations are entirely handled by
the fastest-polarity transistors in a given process[5].
The disadvantage of a telescopic op-amp is severely limited output
swing. It is smaller than that of folded cascode because the tail transistor
directly cuts into the output swing from both sides of the output. In the
telescopic op-amp, all transistors are biased in the saturation region.
The voltage swing is low due to the stacking of the transistors.
Common source amplifier is used as second stage to increase the output
voltage swing to 600mv.
5.5 TWO STAGE OP-AMP:
In order to increase the voltage swing, a second stage is used. The
second stage is configured as a simple common-source stage so as to allow
maximum output swings. In two stage op-amps, the first stage provides high
gain and the second stage produces larger voltage swings[1].
Vin
Stage1
High gain
Stage2
High swing
Figure.5.1. Two stage op-amp
30
Vout
Figure.5.2. Two stage op-amp: first stage telescopic cascoded, second stage
common-source stage
Figure.5.3. Output voltage swing of 2 stage op-amp
31
5.6 BIASING CIRCUIT
Cascode transistors (common source in series with common gate)
have been used for biasing. The common gate transistor shields its drain
terminal from the source terminal. Hence the variations in the voltages
would be less and thus a stable biasing would be achieved in the circuit.
Figure.5.4. Biasing circuit
32
5.7 COMMON MODE FEEDBACK CIRCUIT
Since the common mode output voltage cannot be defined for fully
differential circuits, the technique of CMFB is used.
Figure.5.5. CMFB technique in op-amp
A simple feedback topology utilizing this technique is shown in the
figure5.5. where Ron7|| Ron8 adjusts the bias current of M5 and M6. The ouput
CM level sets Ron7|| Ron8 such that ID5 and ID6 exactly balance ID9 and ID10
respectively[1]. Assuming ID9 = ID10 = ID, results in
Vb- VGS5 = 2 ID (Ron7|| Ron8) and hence
Ron7|| Ron8 = (Vb- VGS5)/ (2 ID).
33
The CM level can thus be obtained by noting that
VGS5=
2I
D



 w 
u
ncox 
 



 L 5 

 VTH
The drawbacks of CMFB networks are: first, the value of the output
CM level is a function of device parameters. Second, the voltage drop across
Ron7|| Ron8 limits the output voltage swings. Third, to minimize this drop, M7
and M8 are usually quite wide devices, introducing substantial capacitance at
the output.
The task of CMFB is divided into three operations: Sensing the output
CM level, comparison with a reference and returning the error to the
amplifier’s bias network[1].
In order to sense the output CM level, Vout= ( Vout1+Vout2)/2, where
Vout1 and Vout2 are the single ended outputs. R1 and R2 should be chosen such
a way that when R1= R2, Vout =( R1 Vout2 + R2 Vout1) / (R1+R2) the equation
should reduce to Vout=( Vout1+Vout2)/2. The difficulty is that R1 and R2 must
be greater than the output impedance of the op-amp so as to avoid lowering
the open loop gain.
To eliminate the resistive loading, source followers should be placed
in between each output and its corresponding resistor. The shift produced is
lower than the output CM level. R1 and R2 or I1 and I2 must be large enough
to ensure that M7 or M8 is not starved when a large differential swing
appears at the output. The sensing method drawback is that it limits the
differential output swings[1].
34
5.8 OP-AMP SPECIFICATIONS
Table.5.2 Op-amp specifications
SPECIFICATIONS VALUE
Gain
70.76dB
Phase margin
64 deg
Voltage swing
600mv
PSRR+
54dB
PSRR-
54 dB
CMRR
72.73 dB
Loop gain
64dB
5.9 GAIN AND PHASE PLOT
Figure.5.6 Gain and phase plot
35
CHAPTER 6
SIMULATION RESULTS
6.1 ADC OUTPUT
Input signal
ADC output
Figure 6.1. Output of delta sigma ADC
It can be seen that the number of transitions in the output is more
when the instantaneous frequency of the sine wave increases ( i.e. the rising
and falling portions of the sine wave ). Similarly, the number of transitions is
less at the output in the maximum and minimum portions of the sine wave
since the instantaneous frequency is less. Hence it can also be said that Delta
Sigma ADC can also be used for PWM (Pulse Width Modulation).
6.2 SIMULATING THE POWER SPECTRAL DENSITY
1) For a 214 point FFT with sampling period Ts, the time duration required
for the simulation will be 214 * Ts seconds.
36
2) The input signal frequency must fall on an FFT bin. That is, the signal
frequency should be k*fs/N. Where, fs = sampling frequency, N= Desired
number of FFT points and k is any integer.
6.3 PSD GRAPH(3V)
Power spectral density of ADC output for 3V supply
Figure.6.3. Power spectral density graph
Figure 6.3 is the Power Spectral Density of the output of the DSM
when a -3dBFS sine wave was given as the input. A 214 point FFT was taken
and Hanning Window has been used. It can be seen that a peak exists at the
signal frequency. Also a 3rd harmonic is evident, which is due to the inherent
characteristic of the Delta Sigma ADC. Since the output is single ended and
centered around the common mode voltage, a peak is seen in the first bin.
Noise shaping (high pass filtering of the quantization noise) can also be seen
clearly in the Figure.6.3.
37
6.4 PSD GRAPH (1.8V)
Power supply density of ADC output for 1.8 V supply
Figure.6.4 Power spectral density graph
Figure.6.4 is the Power Spectral Density of the output of the DSM
when a -3dBFS sine wave was given as the input. A 214 point FFT was taken
and Hanning Window has been used. It can be seen that a peak exists at the
signal frequency. However, noise shaping in the signal band is not as perfect
as the previous case.
38
CONCLUSION
Analog to Digital Converters are the prime components required for
interfacing the real world analog signals with the digital signal processing
blocks. A lot of research has been done in designing ADCs that has high
speed, occupies minimum area and gives high precision outputs. Delta
Sigma ADC has all the aforesaid characteristics.
A 16 bit 2nd order Delta Sigma Analog to Digital Converter has thus
been designed using only a 1 bit ADC that comprises of a novel latched
comparator, in the feedback loop. Since minimum transistors are used, there
are no issues related to mismatch in the mosfet parameters. The area
occupied is also very less. The loop filter, in conjunction with the 1 bit ADC
in the feedback loop, facilitates noise shaping. The signal sees a unity gain
while the quantisation noise of the nonlinear ADC is high pass filtered. This
causes a tremendous increase in the Signal to Noise ratio within the signal
band.
From the time domain waveform of the output shown, it can be seen
that the DSM can also be used for pulse width modulation as the number of
transitions at the output is proportional to the instantaneous frequency. Thus
a SNR of 90 dB has been achieved using an oversampling ratio of 128 and a
clock frequency of 1.024 MHz.
39
REFERENCES
1) Design of Analog CMOS Integrated Circuits by Behzad Razavi
2) B.E.Boser and B.A.Wooley. “The design of sigma-delta modulation
analog-to-digital converters,” IEEE Journal of Solid State Circuits,
Vol 23, December 1988.
3) B.P.Brandt, D.E.Wingard and B.A.Wooley, “2nd-order sigma-delta
modulation for digital audio signal acquisition”, IEEE Journal of Solid
State Circuits, Vol 26, April 1991.
4) Theory, Practice, and Fundamental Performance Limits of HighSpeed Data Conversion Using Continuous-Time Delta-Sigma
Modulators. PhD Dissertation, James A Cherry,1975.
5) A High Swing telescopic operational amplifier,IEEE paper by Kush
Gulati and Hae-Seung Lee,Dec 98.
6) Design of a fully Differential Operational Amplifier with High Gain,
Large Bandwidth, and with High Dynamic Range by Manish Kumar,
Thapar University, Patiala, July 2009.
7) S. Pavan, N. Krishnapura, R. Pandarinathan and P. Sankar, “A Power
Optimized Continuous-time Delta-Sigma Modulator for Audio
Applications,” IEEE Journal of Solid State Circuits, February 2008.
8) Understanding Delta Sigma Data Converters , Richard Schreier ,
Gabor.C.Temes, Wiley IEEE Press, 2005
9) V. Srinivas, S. Pavan, A. Lachhwani and N. Sasidhar, ” A Distortion
Compensating Flash Analog to Digital Conversion Technique,” IEEE
Journal of Solid State Circuits., Vol 41, No.9, September 2006
10)
Y.Yang, A.Chokhalwa, M.Alexander, J. Melanson and D.
Hester, “ A 114 dB 68 mW chopper-stabilized stereo multi-bit audio
A/D Converter”, ISCCC Digest of Technical Papers, Feb 2003.
40