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Faculty Of Computer Studies
T103
Computer architecture, logic and information
FINAL EXAM- ANSWER KEY (A)
Summer – 2011
Sunday 14, August 2011
Number of MTA Pages:
( 4 ) Time Allowed:
(including this cover sheet)
( 2.5 ) Hour
Instructions:
1- Write all your answers on the answer booklet.
2 - Electronic devices (especially calculators) are not allowed
Question
No.
Part 1
Total
marks
20
Part 2
14
Part 3
16
Part 4
50
100
Total
Quality
Assurance
Responsible
Signature
Earned
Points
First Marker’s Second Marker’s
Signature
Signature
Reviewer’s
Signature
T103
Final Exam
Summer 2010-2011
PART 1 ALL QUESTIONS ARE REQUIRED [20 Marks]
Question 1: Choose the correct answer and write it on the answer sheet on page 2: (15 marks)
1)
a)
b)
c)
d)
The CPU shares data with other system components by way of
a data pulse.
a data sharing.
a data bus.
Not applicable.
2)
a)
b)
c)
d)
0111 7 MARIE instruction is used to
Input a value from the keyboard
load the value in PC
terminate a program
resume executing a program
3)
a)
b)
c)
d)
4)
e)
f)
g)
h)
A direct addressing mode means
the address of the operand is explicitly stated in the instruction
the address of the operand is implicitly stated in the instruction
the address of the operand is explicitly stated in the CPU
None
A Boolean function has :
At least one Boolean variable
At least one Boolean operator
At least one input from the ser {0,1}
All mentioned above .
5)
a)
b)
c)
d)
Using the basic identities of Boolean algebra , x(x'+y)= ____
xy'
xy
x+y
x'+y
6)
a)
b)
c)
d)
Simplify the following function (x+y)(x’+y) to get :
x
y
xy
x'+y
7)
a)
b)
c)
d)
Parallel ports send data as :
Single pulse along at least eight data lines .
A triple pulses along at least eight lines .
A series of pulses along at least eight data lines.
It depends on the status of the used port .
8)
a)
b)
c)
d)
Transfer resistor is
Transistor
Buses
Chips
All above
9)
a)
b)
c)
d)
Add 010011112 to 011000112 using the signed magnitude arithmetic.
50
51
49
99
10)
a)
b)
c)
d)
We can improve CPU throughput when
reduce the number of cycles per instruction
we reduce the number of instructions in a program
reduce the number of nanoseconds per clock cycle
Any of what mentioned above
Form A
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T103
Final Exam
Summer 2010-2011
11)
a)
b)
c)
d)
MARIE, was designed for the _______ purpose of illustrating basic computer system concepts.
Singular
Multiple
non limited
None
12)
a)
b)
c)
d)
_________ is an intelligent serial interface that is self-configuring. (It supports “plug and play.”)
USB, Universal Serial Bus
Single port
UBS, Universal Bus
None
13)
a)
b)
c)
d)
Interrupts can be triggered by ________
I/O requests
when an invalid instruction is encountered
division by zero
All of what mentioned above
14)
a)
b)
c)
d)
15)
a)
b)
c)
d)
Computer representation of a floating-point number consists of fixed-size fields
Exponent
Significant
Sign
All
Interrupts occur when:
A user break is issued
I/O is requested by the user or a program
A critical error occurs
All what mentioned above
Question 2 . Fill the blanks 5 marks : (1 marks for each blank )
a)
_______________ is used to interrupt and execute programs The processor .
b)
_________________ addresses issues such as control signals ( how the computer is controlled ) computer
organization
c)
Suppose a program generates the address 1AA, in 14 bit binary this number is 00000 110101010 . The first
7 bits of this address go in the ________ , the next 4 go in the ________ and the final 3 bits indicate the ___________
within the block.
Tag field , block field and the word
PART 2 : 2 questions only are required . [ 14 Marks ]
1) Describe the fetch-code-execute cycle for one iteration [ 7 MARKS ] .
1) The control unit fetches the next program instruction from the memory , using the program counter to determine
where the instruction is located .
2) The instruction is decoded into a language the ALU can understand .
3) Any data operands required to execute the instruction are fetched from memory and placed into registers within
CPU.
4) The ALU executes the instruction an dplaces the results in registers or memory .
2) How many bits would have been used to address a 2M X 32 Memory if [ 7 MARKS] :
a) The memory is byte addressable
There are 2M X 4 BYTES = 2 x 220 x 22 = 2
Form A
23
, so 23 bits
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T103
Final Exam
Summer 2010-2011
b) The memory is word addressable.
2M words which equals to 2 x 220 = 221 so 21 bits
3) Convert the following hexadecimal numbers 02CA to binary, Explain : ( 7 marks)
0
0000
2
C
A
0010 1100 1010
PART 3 : 2 question are required [16 marks ]
1)
Given the following function [ 8 MARKS] :
F(X,Y,Z) = (XY) + (NOT(X) Z) + ( Y NOT(Z))
Find the complement of F(X,Y,Z).
Not (F(X,Y,Z)) = NOT ( (XY) + (NOT(X) Z) + ( Y NOT(Z)))
= NOT(XY) + NOT(NOT(X)Z) + NOT (Y NOT (Z))
= (NOT (X) + NOT (Y) ) ( X+ NOT(Z) ) ( NOT(Y) + Z)
2)
Find the sum of 2310 and -910 in binary using two’s complement arithmetic [ 8 MARKS]:
1  111
111
000 1 0111
(23)
111 1 0111 +(-9)
__________ ___
0000 1110
14 10
3) Simplify the following expressions in sum of products .Explain your answer [ 8 MARKS]:
i)
F= AC’+B’D+A’CD+ABCD
STEPS LEFT TO STUDENTS
ii)
S = (A + B) ⋅ (A + B)
S = (A ⋅ B) + (A ⋅ B)
PART 4 : ALL QUESTIONS ARE REQUIRED
1)
Draw the logic circuit for
a) A + BC + D’. [ 5 Marks ]
[ 50 MARKS ]
:
b) (A + B)’(C + D)C’ [ 5 marks ]
Form A
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T103
Final Exam
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2) Suppose a computer uses 4- bit one’s complement numbers. Ignoring overflows , what value
will be stored in the variable j after the following pseudocode routine terminates ? Explain your
steps [ 10 marks ] .
0  j // store 0 in j
-3  k // store -3 in k
while k 0
J = j+1
K= k -1
end while
J
0
1
2
3
4
5
( binary)
0000
0001
0010
0011
0100
0101
K (binary )
- 3 1100
-4 1011 ( 1100 + 1110) (where last carry is added to sum doing 1’s complement addition)
-5 1010 ( 1011 + 1110)
-6 1001 ( 1010 + 1110)
-7 1000 ( 1001 + 1110)
7 0111 (1000 +1110) this is overflow that can be ignored .
3)
Suppose we have two racers that have just completed a 10 mile race. Car A finished in 3
minutes and Car B finished in 4 minutes. Measure the system performance taking point of view
Car A. [ 5 marks ]
4) a) Write down the RTL for the ADD instruction given value X [ 5 marks]
MAR <- X
MBR <-[MAR]
AC <- AC + MBR
b) After the Add instruction is fetched , X is in the most right 12 bits of IR and the IR’s datapath
address is 7, so you need to raise all three datapath read signals to place IR bits 0 through 11 on
the bus , Write down the Signal patterns to the above RTN [ 8]
P0P1P2P3T0 : MAR <- X
Form A
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T103
Final Exam
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P3P4T1: MBR <-M[MAR]
A0p0p1p5t2 : AC <- AC + MBR
CrT3 : RESET THE CLOCK CYCLE COUNTER
c) Draw the timing Diagram for the Micro operations of MARE’S Add instruction [ 8]
Similar to book page Figure 4.16 page 217
5) Suppose we have instructions LOAD 1000 , given that memory and register R1 contain the
values below [4 marks ] :
1000
1400
1100
400
1200
1000
1300
1000
1400
1300
Assuming R1 = 200 and is implied in the indexed addressing mode determine the actual value loaded into the
accumulator and fill in table below :
Mode
Value Loaded into AC
Immediate
Direct
Indirect
Indexed
Form A
Mode
Value Loaded into AC
Immediate
1000
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T103
Final Exam
Form A
Summer 2010-2011
Direct
1400
Indirect
1300
Indexed
1000
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