Download VLSI design 2 marks

Course Name: VLSI Design
Course Code: BEICEI 604R02/MICCEI604R01
UNIT-I
1.
What are the steps involved in twin tub process?
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Tub formation
Thin oxide construction
Gate formation
Source & drain implantations
Contact cut definitions
Metallization
Passivation
When the channel is said to be pinched-off?
For a MOSFET when VGS is greater than Vt, a channel is induced. As we increase VDS current
starts flowing from Drain to Source (triode region). When we further increase VDS, till the voltage
between gate and channel at the drain end to become Vt, i.e. VGS - VDS = Vt, the channel depth at
Drain end decreases almost to zero, and the channel is said to be pinched off. This is where a
MOSFET enters saturation region.
3.
What are the two components of Power dissipation in CMOS inverter?
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Static dissipation due to leakage current or other current drawn continuously from
power supply.
Dynamic dissipation due to switching transient current charging and discharging of
load capacitances.
What is noise margin?
It represents the amount of noise voltage present in the circuit without affecting normal
operation of circuit.
NMH = VOH-VIH and
NML = VIL-VOL
5.
What are the advantages of Silicon-on-Insulator process?
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Higher Performance at equivalent VDD
Reduced Temperature sensitivity
Latch up Eliminated
Reduced Antenna issues
No Body or Well Taps needed
Small transistor saves lot of Area
Power savings
Why NMOS technology is preferred more than PMOS technology?
The mobility of electrons, which are carriers in the case of an n-channel device, is about two
times greater than that of holes, which are the carriers in the p-channel device. Thus an n-channel
device is faster than a p-channel device.
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7.
Compare between CMOS and Bipolar technologies.
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CMOS
Low static power dissipation
High input impedance
High noise margin
High packing density
High delay sensitivity to load(fan –out
limitations)
Low output drive current
Low Gm
Bidirectional capability
Define threshold voltage in CMOS.
Bi-CMOS
High power dissipation
Low input impedance
Low voltage swing logic
Low packing density
Low delay sensitivity to load
High output drive current
High Gm
Essentially unidirectional
It is defined as voltage applied between gate and source of MOS transistor below which drain
to source current IDS effectively drops to zero.
9.
What is pull up and pull down devices?
Pull-up:
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A pull-up device when energized will pull the output to supply ie..1
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Generally PMOS is used as pull up device
Pull-down:
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pull -down device when energized will pull the output to ground
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NMOS is used as pull down device
What are the three operating regions of MOSFET?
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Cut off region
Linear
Saturation
11.
Write various fabrication methods in CMOS.
12.
 P-well
 N-well
 Twin-tub
 SOI
What is lateral diffusion?
Lateral diffusion refers to the lateral movement of lipids and proteins found in the membrane.
Membrane lipids and proteins are generally free to move laterally if they are not restricted by certain
interactions. Lateral diffusion is a fairly quick and spontaneous process.
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Draw the MOSFET capacitive device model.
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14.
What are the advantages of the CMOS technology over the NMOS technology?
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CMOS has relatively high performance and cost effective than NMOS technology.
CMOS shows lower static power dissipation compared to NMOS.
CMOS provides high noise immunity.
Draw the DC transfer characteristics of CMOS inverter.
What is meant by NMH and NML?
HIGH noise margin: is defined as the difference in magnitude between minimum High
output voltage of the driving gate and minimum input High voltage recognized by the receiving gate.
NMH=|VOH – VIH|
LOW noise margin: is defined as the difference in magnitude between the maximum
Low output voltage of the driving gate and the maximum input Low voltage recognized by the driven
gate. NML=|VIL – VOL|
17.
Define rise time, delay time and fall time.
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Rise time (tr) :time required for a node to charge from the 10% point to 90% point.
Fall time (tf) : time required for a node to discharge from 90% to 10% point .
Delay time (td) : delay from the 50% point on the input to the 50% point on the output .
Define the terms SSI, MSI, LSI and VLSI.
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SSI: Small Scale Integration:- (10-100) transistors => Example: Logic gates .
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MSI: Medium Scale Integration:- (100-1000) => Example: counters .
LSI: Large Scale Integration:- (1000-20000) => Example:8-bit chip .
VLSI: Very Large Scale Integration:- (20000-1000000) => Example:16 & 32 bit up.
ULSI: Ultra Large Scale Integration:- (1000000-10000000) => Example: Special processors,
virtual reality machines, smart sensors.
Write the advantages and disadvantages of VLSI compared to other technologies.
Advantages:
 simplicity of operation
 high component density
 design flexibility
 design security
 high reliability
 high performance and high functionality
Disadvantages:
 long design and fabrication time
 higher risk to project
 high cost
20.
Write the applications of VLSI technology.
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 digital signal processing
 multimedia information system
 wireless lan
 Bluetooth
 automobiles and toys
 computer and computer graphics
State Moor’s law?
The number of transistors embedded on the chip doubles after every 11/2 years. He predicted that
semiconductor technology wills double its effectiveness every 18 months.
22.
What are the pros and cons of MOSFETs?
Pros :
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Cons:
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Small compared to BJT, easy to fabricate and space saving
Input impedance is high hence no loading effect
Operating frequency is very high
Handling is not easy
Tran conductance is lower than BJT
Mobility limitations since it depends on gate and drain voltage
Draw the V-I and transfer characteristics of n-MOSFET.
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24.
Draw the V-I characteristics of p-MOSFET.
25.
What is Enhancement type MOSFET and Depletion type MOSFET?
Enhancement-mode MOSFETs are the common switching elements in most MOS. These devices are
off at zero gate–source voltage, and can be turned on by pulling the gate voltage in the direction of the
drain voltage; that is, toward the VDD supply rail, which is positive for NMOS logic and negative
for PMOS logic.
In a depletion-mode MOSFET, the device is normally ON at zero gate–source voltage. Such devices
are used as load "resistors" in logic circuits (in depletion-load NMOS logic, for example). For Ntype depletion-load devices, the threshold voltage might be about –3 V, so it could be turned off by
pulling the gate 3 V negative (the drain, by comparison, is more positive than the source in NMOS).
In PMOS, the polarities are reversed.
26.
Write the current equations in MOSFET for three operating regions.
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27.
What are the various parameters affects the threshold voltage in MOSFET?
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gate conducting material
gate insulation material
gate insulation thickness
channel doping
impurities at silicon oxide interface and voltage between source and substrate
Define body-effect / sub threshold effect?
Vt is not constant with respect to Vsb of the transistor. This effect is called body effect or substrate
bias effect
29.
What is channel length modulation?
In practice, when VDS is further increased beyond saturation point, it does have some effect on the
characteristics of the MOSFET. When VDS is increased the channel pinch-off point starts moving
away from the Drain and towards the Source. Due to which the effective channel length decreases,
and this phenomenon is called as Channel Length Modulation.
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Define the terms Trans conductance, output conductance and Figure of merit for MOSFET?
Trans conductance:
 Relation between output current Ids and input voltage Vgs is trans conductance
I ds
atVds  cons tan t
V gs
Output Conductance:
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g ds  ds
Vds
Figure of merit:
Wo=( gm/Cg)
31.
What are the various sources for Dynamic behavior of the MOSFET?
32.
 charge and discharge capacitances between device ports
 charge and discharge capacitances of interconnecting lines
Define diffusion capacitance?
Diffusion capacitance is a nonlinear capacitance and is caused by reverse biased source bulk and the
drain bulk p-n junctions. This decreases as reverse bias increased.
33.
Write the various channel capacitances present in MOSFET operation.
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gate capacitance Cg
overlap capacitance
diffusion capacitance
capacitance between gate and source, Cgs
capacitance between gate and drain, Cgd
capacitance between gate and bulk region, Cgb
Define velocity saturation and mobility degradation?
Velocity Saturation:
vn   m E (x)
However when E(x) along the channel reaches the critical value is saturation, then velocity tends to
saturate .this is called velocity saturation.
Mobility degradation:
Mobility degradation is an effect of reducing channel length. This reduces transistor current
even at normal electric field levels. Reduction in mobility degradation is also observed by the vertical
component of electric field. This effect is called mobility degradation.
35.
Write the various secondary effects causes to vary the ideal characteristics of MOSFET.
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 threshold variations
 source drain resistance
 variation in I-V characteristics
 sub threshold conduction
What is sub threshold condition in MOSFET?
MOSFET partially conducts for voltages below the threshold voltages .this effect is called sub threshold conduction.
37.
What are the pros and cons of CMOSFETs?
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Advantages:
low static power consumption
high noise immunity
reduce complexity of the circuit
low wafer cost and mature technology
Disadvantages:
no bipolar
secondary effects present
mismatch of CMOS devices is high
peak inverse voltage is high
What is p well and n well?
These two are CMOS technologies used to provide lower power delay product than comparable
design rule of bipolar, NMOS or GaAs technologies
P-well process:
p-well is implanted in a n substrate
n-well process:
same as p-well process ,here n-well implanted in p-substrate
39.
Define oxidation?
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Oxidation is defined as the interaction between oxygen molecules and all the different substances they
may contact, from metal to living tissue. But there are meanings for oxidation as in the following
 oxidation is gain of oxygen
 oxidation is loss of hydrogen
 oxidation is loss of electrons
40.
What is photo lithography?
Photolithography is the process of transferring geometric shapes on a mask to the surface of
a silicon wafer. The steps involved in the photolithographic process are wafer cleaning; barrier layer
formation; photo resist application; soft baking; mask alignment; exposure and development; and
hard-baking.
41.
What is ion implantation?
Ion Implantation is an alternative to deposition diffusion As the impurity atoms enter the
crystal; they give up their energy to the lattice in collisions and finally come to rest at some average
penetration depth, called the projected range expressed in micro meters. Depending on the impurity
and its implantation energy, the range in a given semiconductor may vary from a few hundred
angstroms to about 1micro meter
42.
What is negative resist and positive resist?
Positive resists:
The resist is exposed with UV light wherever the underlying material is to be removed. In
these resists, exposure to the UV light changes the chemical structure of the resist so that it becomes
more soluble in the developer. The exposed resist is then washed away by the developer solution,
leaving windows of the bare underlying material.
Negative resist:
It behaves in just the opposite manner. Exposure to the UV light causes the negative resist to
become polymerized, and more difficult to dissolve. Therefore, the negative resist remains on the
surface wherever it is exposed, and the developer solution removes only the unexposed portions.
43.
Why depletion load NMOS inverter is preferred over enhancement load NMOS inverter?
In integrated circuits, depletion-load NMOS is a form of digital logic family that uses only a
single power supply voltage, unlike ea nMOS logic families that needed more than one different
power supply voltage
. Although manufacturing these integrated circuits required additional processing steps, elimination of
the extra power supply, and improved switching speed, made this logic family the preferred choice for
many microprocessors and other logic elements.
44.
Draw the transfer characteristics of CMOS inverter.
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45.
Draw the transfer characteristics of NMOS inverter.
46.
What are advantages and limitations of CMOS inverter over NMOS inverter?
Limitation:
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Since N MOS &PMOS transistor must be fabricated on the same chip side by side,
CMOS process is more complex than the standard NMOS.
Formation of parasitic bipolar transistor due to the close proximity of N and P MOS
transistor causes CMOS latch up condition .Addition guard rings must be built around
NMOS and PMOS transistor to prevent from undesirable effects.
Advantages:
 Steady state power dissipation of the CMOS inverter is negligible
 voltage transfer characteristics exhibits the full output voltage swing between 0 &VDD.This
results in high noise margin, also VTC transistor is usually very sharp and hence CMOS
inverter resembles in ideal inverter characteristics
47.
What are the various operating regions of CMOS inverter?
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48.
What are the various design parameters to be considered while designing the CMOS inverter?
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Threshold voltage & Trans conductance ratio (KR)
symmetrical CMOS inverter
noise margin
temperature dependence
supply voltage scaling
power and area consideration
49.
What is CMOS gate transistor sizing?
50.
• Load Capacitance
• Fall and rise time analysis.
• Analytical models.
• Propagation delay analysis.
• Fall and rise time formulas
• Transistor sizing
• Multi-input
Define symmetric CMOS inverter?
51.
CMOS is also sometimes referred to as complementary-symmetry metal–oxide–
semiconductor (or COS-MOS). The words "complementary-symmetry" refer to the typical design
style with CMOS uses complementary and symmetrical pairs of p-type and n-type metal oxide
semiconductor field effect transistors (MOSFETs) for logic functions.
Define stage ratio in CMOS inverter?
The ratio by which each stage is increased in size is called the stage ratio.
52.
A MOS transistor has a threshold voltage of 0.75V, while the body effect coefficient equals to
0.54. Compute the threshold voltage for VSB=5V and Fermi level= -0.6V.
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For the CMOS inverter circuit with VDD=3.3V, VTn= 0.6V, VTp= -0.7V, kn=200 uA/V2, kp=80
uA/V2. Calculate the noise margins of the circuit.
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For a CMOS inverter with VTn= 0.6V,unCox=60uA/V2, (W/L)n=8, VTp= -0.7V,upCox=25uA/V2,
(W/L)n=12, and VDD= 3.3V. Calculate the noise margin and the switching threshold voltage of
this circuit.
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An abrupt junction has doping densities of NA=1015 atoms/cm3 and ND=1016 atoms/cm3.
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Calculate the built in potential at 300K.
56.
Why low power has become an important issue in the present day VLSI circuit realization?
In deep submicron technology the power has become as one of the most important issue because of:
 Increasing transistor count; the number of transistors is getting doubled in every 18 months
based on Moore’s Law.
 Higher speed of operation; the power dissipation is proportional to the clock frequency.
 Greater device leakage currents; In nanometer technology the leakage component becomes a
significant percentage of the total power and the leakage current increases at a faster rate than
dynamic power in technology generations.
57.
How reliability of a VLSI circuit is related to its power dissipation?
It has been observed that every 10ºC rise in temperature roughly doubles the failure rate
because various failure mechanism such as silicon interconnect fatigue, electro migration diffusion,
Junction diffusion and thermal runaway starts occurring as temperature increases.
58.
How environment is affected by the power dissipation of VLSI circuits?
Generally the power is dissipated mostly in the form of heat. The cooling techniques, such as
AC transfers the heat to the environment.
59.
What is the latch up problem that arises in bulk CMOS technology? How is it overcome?
Latch-up can be defined as the formation of a low-impedance path between the power supply
and ground rails through the parasitic n-p-n and p-n-p bipolar transistors.
Some of the important techniques to overcome are Latch-up are:
 use guard ring around p- and/or n-well with frequency contacts to the rings.
 To reduce the gain product B1XB2.
 Moving the n-well and the n+ source/drain further apart.
 Buried n+ layer in well to reduce gain of Q1.
 Higher substrate doping level to reduce R-sub.
 Reduce R-well by making low resistance contact to GND.
60.
The following parameters are given for an nMOS process: tox=500Å, NA = 1x1016cm-3, ND =
1x1020cm-3, NOX = 2x1010cm-1.
(i) Calculate Vt for an un implanted transistor,
(ii) What type and what concentration must be implanted to achieve Vt = +1.5V and Vt = 2.0V?
61.
Explain the behavior of a NMOS transistor as a switch.
62.
The input of a lightly loaded transmission gate is slowly changes from HIGH level to LOW level.
How the currents through the two transistors vary?
In this case, the output closely follows the input. In this case the transistors operate in three
regions depending on the input voltage as follows:
 Region I: NMOS non-saturated, PMOS cut-OFF.
 Region II: NMOS non-saturated, PMOS non-saturated.
 Region III: NMOS cut off, PMOS non-saturated.
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63.
What is the inversion voltage of an inverter?
The inversion voltage Vinv is defined as the voltage at which the output voltage Vo is equal to the
input voltage Vin. For a CMOS inverter it can be expressed in terms of the threshold voltages of
the MOS transistors and other parameters
64.
How the inversion voltage is affected by the relative sizes of the NMOS and PMOS transistors of
the CMOS transistors of the CMOS inverter?
In a CMOS process kn/kp=un/up=2.5
To make one may choose (W/L)p=2.5 (W/L)n to get the Vinv=Vdd/2
65.
How the noise margin is affected by voltage scaling?
As the supply voltage is reduced, the margin also decreases as shown in the figure.
66.
What are the various ways to reduce the delay time of a CMOS inverter?
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The width of the MOS transistors can be increase width of the MOS transistors can be
increased to reed to reduce the duce the delay. This is known as gate sizing, which will be
discussed later in more details.
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The load capacitance can be reduced to reduce d load capacitance can be reduced to reduce
delay. This is achieved by using transistors of smaller and smaller dimensions as
provided by future generation technologies.
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Delay can also be reduced by increasing the sup can also be reduced by increasing the supply
voltage ply voltage Vdd and/or reducing the threshold voltage and/or reducing the threshold
voltage Vt of the MO of the MOS transistors. S transistors.
67.
Why do the present VLSI circuits use MOSFETs instead of BJTs?
Compared to BJTs, MOSFETs can be made very small as they occupy very small silicon area
on IC chip and are relatively simple in terms of manufacturing. Moreover digital and memory ICs can
be implemented with circuits that use only MOSFETs i.e. no resistors, diodes, etc.
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