Download Verilog HDL Implementation of USB to Ethernet Converter

Verilog HDL Implementation of USB to Ethernet
Converter
______________________________________________________________________________
Abstract--Universal Serial Bus is a fast and reliable serial
interface standard, where as Ethernet MAC is widely used
networking standard. USB to Ethernet converter is one of
the most widely used protocol converter in several PC based
and embedded applications. The Verilog HDL
implementation of USB to Ethernet converter is useful either
for ASIC implementation or for FPGA based applications.
The three main blocks of this converter are Ethernet MAC,
USB device and the protocol converter between these two
interfaces.Generally used Ethernet MAC standard data rates
are 10/100/1000 Mbps. In this project Ethernet MAC
controller block will be implemented in Verilog HDL,
conforming to IEEE 802.3 specification. The Ethernet MAC
shall have optional half-duplex support for 10/100 Mbps
mode, and uses FIFO interface to user application. The
source MAC address insertion for transmitting frames, and
address filter for receiving frames destination MAC address,
will be implemented as optional features. The receiving
broadcast frames throughout constraint will also be
implemented as optional feature. The Ethernet MAC shall
also support Jumbo frame size of 9.6K, along with standard
MTU. The USB controller block handles the details of USB
communications. This block is responsible for responding to
requests to send and receive configuration data, and for
reading and writing other data. The controller chip has to
know how to detect and respond to events at a USB port and
it has to provide a way for the device to store data to be sent
and retrieve data that have been received. The interface
block between USB and Ethernet protocols manages a two
way handshake between these two controllers. This block
handles different synchronization aspects with proper clock
and control circuitry between USB and Ethernet
interfaces.Verilog HDL will be used for implementing all
these blocks. ModelSim Simulator tool will be used for
functional simulation of the design. The broad class of
applications of the implemented soft USB to Ethernet MAC
protocol converter will be studied.
1. INTRODUCTION
Ethernet was originally developed by Digital, Intel and
Xerox (DIX) in the early 1970's and has been designed as a
'broadcast' system, i.e. stations on the network can send
messages whenever and wherever it wants. All stations may
receive the messages, however only the specific station to
which the message is directed will respond.The original
format for Ethernet was developed in Xerox Palo Alto
Research Centre (PARC), California in 1972. Using Carrier
Sense Multiple Access with Collision Detection
(CSMA/CD) it had a transmission rate of 2.94Mb/s and
could support 256 devices over cable stretching for 1km.
The two inventors were Robert Metcalf and David Boggs.
Ethernet versions 1.0 and 2.0 followed until the IEEE 802.3
committee re-jigged the Ethernet II packet to form the
Ethernet 802.3 packet. (IEEE's Project 802 was named after
the time it was set up, February 1980.Ethernet uses Carrier
Sense Multiple Access with Collision Detection
(CSMA/CD). When an Ethernet station is ready to transmit,
it checks for the presence of a signal on the cable i.e. a
voltage indicating that another station is transmitting. If no
signal is present then the station begins transmission,
however if a signal is already present then the station delays
transmission until the cable is not in use. If two stations
detect an idle cable and at the same time transmit data, then
a collision occurs. On a star-wired UTP network, if the
transceiver of the sending station detects activity on both its
receive and transmit pairs before it has completed
transmitting, then it decides that a collision has occurred. On
a coaxial system, a collision is detected when the DC signal
level on the cable is the same or greater than the combined
signal level of the two transmitters, i.e.. significantly greater
than +/- 0.85v. Line voltage drops dramatically if two
stations transmit at the same and the first station to notice
this sends a high voltage jamming signal around the network
as a signal. The two stations involved with the collision lay
off transmitting again for a time interval which is randomly
selected. This is determined using Binary Exponential
Backoff. If the collision occurs again then the time interval
is doubled, if it happens more than 16 times then an error is
reported. A Collision Domain is that part of the network
where each station can 'see' other stations' traffic both
unicast and broadcasts. The Collision Domain is made up of
one segment of Ethernet coax (with or without repeaters) or
a number of UTP shared hubs. A network is segmented with
bridges (or microsegmented when using switches) that create
two segments, or two Collision Domains where a station on
one segment can not see traffic between stations on the other
segment unless the packets are destined for itself. It can
however still see all broadcasts as a segmented network, no
matter the number of segments, is still one Broadcast
Domain. Separate Broadcast Domains are created by
VLANs on switches so that one physical network can
behave as a number of entirely separate LANs such that the
only way to allow stations on different VLANs to
communicate is at a layer 3 level using a router, just as if the
networks were entirely physically separate.
The Universal Serial Bus (USB) is a plug-and-play interface
between computers and a wide assortment of add-on
devices, such as mice, touchpads, audio systems, printers,
and scanners. USB allows easy addition of devices to your
computer without even having to reboot. It allows up to 127
devices to run simultaneously on a single computer. The
USB peripheral bus supports a data speed of 12 megabits per
second, which is incredibly fast. This speed accommodates a
wide range of devices, including MPEG-2 video-based
products, data gloves and digitizers.USB is a likely solution
any time you want to use a computer to communicate with
devices outside the computer. Universal Serial Bus is
suitable for one-of-kind and small-scale designs as well as
mass-produced, standard peripherals. USB was designed
from the ground up to be a simple and efficient way to
communicate with many types of peripherals, without the
limitations and frustrations of existing interface. USB is
more complicated than the interfaces it replaces. Plus, the
interface is new, and by necessity, the hardware, software
drives, and development tools could not begin to be
designed until there was a specification to follow. But later
the specifications were released and the advantages offered
by a USB peripheral outweighed the difficulties for the
designer. The interface between USB to Ethernet is
implemented by using FIFO registers which are used to
transfer data between USB to Ethernet and vice versa. In this
paper we proposed to design a USB to Ethernet card, which
can match the different data rates of USB and Ethernet and
is having a many Networking and Embedded applications,
installs easily into any available USB port--without requiring
you to open your PC case and connects your PC to a
broadband modem. Exchanges data quickly between
connected PCs and notebooks; lets you share printers and
other peripherals, and communicate via e-mail
This clause defines in detail the frame structure for data
communication systems using the CSMA/CD MAC. It
defines the syntax and semantics of the various components
of the MAC frame. Two frame formats are specified in this
clause:
a) A basic MAC frame format, and
b) An extension of the basic MAC frame format for tagged
MAC frames, i.e., frames that carry Qtag Prefixes.
Figure 3–1 shows the nine fields of a frame: the preamble,
Start Frame Delimiter (SFD), the addresses of the frame’s
source and destination, a length or type field to indicate the
length or protocol type of the following field that contains
the MAC Client data, a field that contains padding if
required, the frame check sequence field containing a cyclic
redundancy check value to detect errors in a received frame,
and an extension field if required (for 1000 Mb/s half duplex
operation only). Of these nine fields, all are of fixed size
except for the data, pad, and extension fields, which may
contain an integer number of octets between the minimum
and maximum values that are determined by the specific
implementation of the CSMA/CD MAC. See 4.4 for
particular implementations.
2 . ETHERNET
The diagrams below describe the structure of the older DIX
(Ethernet II) and the now standard 802.3 Ethernet frames.
The numbers above each field represent the number of bytes.
Fig-1
2.1 MEDIA ACCESS CONTROL FRAME :
Fig-2
Preamble field: Establishes bit synchronisation and
transceiver conditions so that the PLS circuitry synchs in
with the received frame timing. The DIX frame has 8 bytes
for the preamble rather than 7, as it does not have a Start
Frame Delimiter (or Start of Frame).
Start Frame Delimiter: Sequence 10101011 in a separate
field, only in the 802.3 frame.
Destination address: Hardware address (MAC address) of
the destination station (usually 48 bits i.e. 6 bytes).
Source address: Hardware address of the source station
(must be of the same length as the destination address, the
802.3 standard allows for 2 or 6 byte addresses, although 2
byte addresses are never used, N.B. Ethernet II can only uses
6 byte addresses).
Type: Specifies the protocol sending the packet such as IP or
IPX (only applies to DIX frame).
Length: Specifies the length of the data segment, actually the
number of LLC data bytes, (only applies to 802.3 frame and
replaces the Type field).
Pad: Zeros added to the data field to 'Pad out' a short data
field to 46 bytes (only applies to 802.3 frame).
Data: Actual data which is allowed anywhere between 46 to
1500 bytes within one frame.
CRC: Cyclic Redundancy Check to detect errors that occur
during transmission (DIX version of FCS).
FCS: Frame Check Sequence to detect errors that occur
during transmission (802.3 version of CRC). This 32 bit
code has an algorithm applied to it which will give the same
result as the other end of the link, provided that the frame
was transmitted successfully. From the above we can deduce
that the maximum 802.3 frame size is 1518 bytes and the
minimum size is 64 bytes. Packets that have correct CRC's
(or FCS's) but are smaller than 64 bytes, are known as
'Runts'.
The hardware address, or MAC address is transmitted and
stored in Ethernet network devices in Canonical format i.e.
Least significant Bit (LSB) first. You may hear the
expression Little-Endian to describe the LSB format in
which Ethernet is transmitted. Token Ring and FDDI, on the
other hand, transmit the MAC address with the Most
Significant Bit (MSB) first, or Big-Endian, This is known as
Non-Canonical format. Note that this applies on a byte by
byte basis i.e. the bytes are transmitted in the same order it is
just the bits in each of those bytes that are reversed! The
storage of the MAC addresses in Token Ring and FDDI
devices however, may sometimes still be in Canonical
format so this can sometimes cause confusion. The reference
to, the distribution of MAC addresses and the OUI
desinations are always carried out in Canonical format.
2.2 I/G and U/L within the MAC address
With an Ethernet MAC address, the first octet uses the
lowest significant bit as the I/G bit (Individual/Group
address) only and does not have such a thing as the U/L bit
(Universally/Locally administered). The U/L bit is used in
Token Ring A destination Ethernet MAC address starting
with the octet '05' is a group or multicast address since the
first bit (LSB) to be transmitted is on the right hand side of
the octet and is a binary '1'. Conversely, '04' as the first octet
indicates that the destination address is an individual
address. Of course, in Ethernet, all source address will have
a binary '0' since they are always individual.
3. UNIVERSAL SERIAL BUS
The Universal Serial Bus (USB) is a plug-and-play interface
between computers and a wide assortment of add-on
devices, such as mice, touchpads, audio systems, printers,
and scanners. USB allows easy addition of devices to your
computer without even having to reboot. It allows up to 127
devices to run simultaneously on a single computer.
The USB peripheral bus supports a data speed of 12
megabits per second, which is incredibly fast. This speed
accommodates a wide range of devices, including MPEG-2
video-based products, data gloves and digitizers and
computer to communicate with devices outside the
computer. USB is a likely solution any time you want to use
a Universal Serial Bus is suitable for one-of-kind and smallscale designs as well as mass-produced, standard
peripherals.
USB was designed
from the ground up
to be a simple and
efficient way to
communicate with
many types of
peripherals, without
the limitations and
frustrations
of
existing interface.
Every new PC has a
couple of USB
ports that we can
connect
to
a
keyboard, mouse,
scanner,
external
disk drive, printer,
and standard and
custom hardware of
all kinds. Inexpensive hubs enable us to add more ports and
peripherals as needed.But one result of USB’s ambitious
goals has been challenges for the developers who design and
program USB peripherals. USB is more complicated than
the interfaces it replaces. Plus, the interface is new, and by
necessity, the hardware, software drives, and development
tools could not begin to be designed until there was a
specification to follow. But later the specifications were
released and the advantages offered by a USB peripheral
outweighed the difficulties for the designer.
3.1 USB CONTROLLER:
The USB controller has the serial data as input. Apart from
the serial data input, it also has various other inputs like
receive error (rx_error), receive active (rx_active), receive
valid (rx_valid), clock and reset. The clock input is used to
sample the input data. The rx_error indicates an error in the
reception of data. If this signal is ‘1’, then that particular
packet is ignored. Similarly, rx_active and rx_valid should
be high to process the received packet. During OUT or
SETUP data packet the data is received by packet
disassembler and data is saved in the memory. During IN
data packet, the data is read from memory and sent on to the
serial bus by packet assembler. The operation of whole USB
device is controlled by protocol engine. The configuration
information is saved in register block. There is 256 byte
memory provided for data storage. A timer is also provided
to check for the timeout condition.
USB Core Main Flowchart: Fig-5
Table -1: Configuration Register
B
A
Description
ccess
1
R
Unused
ead only
4
R
Line state
ead only
2
R
Interface
ead only
status1=Attached
1
R
Interface speed
ead only
1 = High speed
mode
0 = full speed
mode
0
R
1 = Suspend
ead only
mode
After
reset,
the
5:5
device is
initially
:3
in IDLE
state.
When
token is
received
it checks
whether
the
token is
a valid
token or
not. If the token is invalid, error is reported. After receipt of
proper token, it is decoded to find out type of data transfer.
The 4-bit PID field of token packet determines whether the
data should be sent for special token processing state, setup
cycle, IN data cycle or OUT data cycle. In all of these states
the error in CRC is always checked and if there is any error
the state machine goes back to IDLE state. The main control
signals for these operations are generated by the protocol
engine. Various blocks of USB controller are explained
below. The VHDL code for different modules is given in
Appendix.
1. Packet disassembler: This block separates the various
constituents of the packet. It checks the token packet and
initiates the corresponding cycle depending on whether the
token corresponds to SETUP, IN, OUT or special data
processing. It generates an error flag that indicates an error if
the PID or DATA received is incorrect. The error in data is
identified by CRC checking.
it no
2. Packet assembler: This block assembles the packet for
transmission on the bus. Two types of packets are possible.
They are DATA packet or ACK packet. Depending on
whether the previous data reception is correct or not,
corresponding ACK (acknowledgement) packet is
transmitted.
3. Protocol Engine: The protocol engine generates all the
control signals required for the operation of USB controller.
This block directly communicates with the memory. It
generates the various read/write control signals for the
memory. It contains the checking logic to determine whether
to save the previously received data depending on the value
of error flags. This block communicates with 16-bit timer
block. The timer can be programmed for some time duration
after which it gives a signal which is used as timeout in the
reception of data or acknowledgement.
4. Register block: A set of registers are used to save the
configuration information in the USB device. Mainly there
are two registers. The first register is called as configuration
register. The second one is device address register. The
registers and the individual bits are indicated in Table 4-1
and Table 4-2
Table-2: Device Address Register
it
5:7
:0
B
ccess
1
/W
6
/W
A
Descr
iption
R
Unus
ed
R
Devic
e address
5. Memory: A 256 byte memory is used in the USB device
to store the data which is to be transmitted and the data
which is received from host. Two signals rd_addr and
wr_addr are used to write/read a particular location. Care is
token to indicate an error, if the host tries to read more data
than available in the device.
6. Timer: A 16-bit timer is used to check for the timeout
condition in the USB device. This contains a 16-bit counter
which generates a timeout signal after the count reaches a
specific count value. This count value is programmed by
Protocol engine.
7. Serial to parallel converter: A 8-bit shifter register is used
to convert the incoming serial data bits from the USB to
parallel data. This parallel data is processed by subsequent
blocks. A separate clock which operates at 8 times slower
than the global clock is used to sample and process the
parallel data.
8. Parallel to serial converter: After assembling the data by
packet assembler, it is 8-bit parallel data. A parallel-to-serial
converter is used to get the data that is to be transmitted to
USB. The function implemented is a parallel-in, serial-out
shift register.
9. 5-bit CRC block: This block calculates the CRC value for
the token packet. The input to this block is 11-bit (7-bit
address and 4-bit endpoint number). This 5-bit CRC value is
checked against the CRC received in the token for the
detection of errors.
10. 16-bit CRC block: This block calculates a 16-bit CRC
value recursively. It accepts 16-bit crc_in and 8-bit din to
calculate CRC value. Initially crc_in is given as X”FFFF”.
Subsequently, the CRC value is generated is fed back to the
input. The output of this block after all data is received is
checked against the CRC value in the data packet for
possible errors in the transmission.
been verified using simulation tools and synthesized using
xc9500xl.
The easiest way to get your computer ready to share Internet
access is through an available USB port.In this paper the
USB to Ethernet Adapter simply plugs in to, let your PC
connect to your cable or DSL modem, as well as share files
and peripherals with computers that are connected to the
network.
4. RESULTS
4.1 Simulation results:
REFERENCES
1. Andrew S.Tanenbaum : computer Networks,PHI , Third
edition, 1996.
2. David G. Cunningham, Wiliam G.Lane: Gigabit Ethernet
Networking : Macmillan Technical publishing, USA1999.
3. Ethernet and fast Ethernet guide
http : // www.ots.utexas.edu/ethernet.
4.Gigabit Ethernet information (PAR,Drafts),
http:// www.ots.utexas.edu:8080/ Ethernet/descript- gigabitieee.html.
4.2 Synthesis report:
!.RTL Top level out put file name: usb_eth_converter.ngr
2. Top Level out put file name : usb_eth_converter
3. Out put format : NGC
4. Optimization Goal : Speed
5. Keep Hierarchy : YES
6. Target Technology : xc9500xl
7. Macro Preserve : YES
8. Clock Enable : YES
9. Total Memory Usage : 124.828 Mega bytes
5. CONCLUSION
An efficient architecture of USB to Ethernet MAC
implementation is proposed in this paper. The design was
captured using Verilog HDL hard ware description language
and implemented the correctness of the functionality has