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CMPE 325 Computer Architecture II Cem Ergün Eastern Mediterranean University Assembly Language Basics 1 Evolution of Multilevel Machines Bare hardware Microprogramming Operating system Compilers Hardware / software interface Simple ISA CISC RISC FISC CMPE 325 Ch. #3 Slide #2 Computer Organization Von Neumann Machine CMPE 325 Ch. #3 Slide #3 Classifying ISAs Accumulator (before 1960): 1 address add A acc <- acc + mem[A] Stack (1960s to 1970s): 0 address add tos <- tos + next Memory-Memory (1970s to 1980s): 2 address 3 address add A, B mem[A] <- mem[A] + mem[B] add A, B, C mem[A] <- mem[B] + mem[C] Register-Memory (1970s to present): 2 address add R1, A load R1, A Register-Register (Load/Store) (1960s to present): 3 address add R1, R2, R3 load R1, R2 store R1, R2 CMPE 325 Ch. #3 R1 <- R1 + mem[A] R1 <_ mem[A] R1 <- R2 + R3 R1 <- mem[R2] mem[R1] <- R2 Slide #4 Classifying ISAs CMPE 325 Ch. #3 Slide #5 Design Principles • CISC vs. RISC • Instructions directly executed by hardware • Maximize instruction issue rate (ILP) • Simple instructions (easy to decode) • Access to memory only via load/store • Plenty of registers • Pipelining CMPE 325 Ch. #3 Slide #6 Instruction set vs. Hardware The instruction set of a computer is For a better processor design, the atomic elements of the program, directly related to the hardware the instructions shall be “simple”, and their execution shall be fast. Properties of the MIPS instruction set instructions optimized for C and Pascal. implementation in hardware is simple. CMPE 325 Ch. #3 Slide #7 Design Principles of RISC Processor Four Underlying Design Principles: Simplicity Favors Similarity Smaller is faster Good design demands compromise Make the common case faster CMPE 325 Ch. #3 Slide #8 Programming Languages There are many programming languages, but they usually fall into two categories High-level languages are usually machine-independent and instructions are often more expressive • C, Fortran, Pascal, Basic Low-level languages are usually machine-specific and offer much finer-grained instructions that closely match the machine language of the target processor • Assembly languages for MIPS, x86 CMPE 325 Ch. #3 Slide #9 Assembly Languages Assembly languages are text representations of the machine language One statement represents one machine instruction Abstraction layer between high-level programs and machine code CMPE 325 Ch. #3 Slide #10 Machine Language Machine language is the native language of the computer The words are called instructions The vocabulary is the instruction set Bit representation of machine operations to be executed by the hardware We will focus on the MIPS instructions Other RISC-based instruction sets are similar Different instruction sets tend to share a lot of commonalities since they function similarly CMPE 325 Ch. #3 Slide #11 Fitting Languages Together temp = v[k]; High Level Language Program Compiler Assembly Language Program Assembler Machine Language Program v[k] = v[k+1]; v[k+1] = temp; lw lw sw sw $15, $16, $16, $15, 0000 1010 1100 0101 1001 1111 0110 1000 0($2) 4($2) 0($2) 4($2) 1100 0101 1010 0000 0110 1000 1111 1001 1010 0000 0101 1100 1111 1001 1000 0110 0101 1100 0000 1010 1000 0110 1001 1111 Machine Interpretation Control Signal Specification High/Low on control lines CMPE 325 Ch. #3 Slide #12 Assembly Instructions The basic type of instruction has four components: 1. 2. 3. 4. Operator name Place to store result 1st operand 2nd operand add dst, src1, src2 Simple, fixed formats make hardware implementation simpler (“simplicity favors regularity”) On most architectures, there are no restrictions on elements appearing more than once CMPE 325 Ch. #3 Slide #13 Assembly Instructions Assembly Language Instruction Format: a) [label:] operation b) Labels A symbol string associated with a specific memory address c) Operations: 1) Assembler directive 2) Machine instruction d) Operands: 1) Register names 2) Immediate value 3) Address label e) [operand1 [operand2 [operand3]]] [ # [comment]] (i.e. $0, $29, named: $a0, 0($t0)), Numeric expression (instruction or data, i.e. Loop2:, myVal:) Comments: Text string from # symbol to end of line. Ignored by assembler. CMPE 325 Ch. #3 Slide #14 Arithmetic Operators Consider the C operation for addition a = b + c; Use the add operator in MIPS add a, b, c Use the sub operator for a=b–c in MIPS sub a, b, c Since assembly code can be difficult to read, the common practice is to use # for comments CMPE 325 Ch. #3 Slide #15 Complex Operations What about more complex statements? a = b + c + d - e; Break into multiple instructions add t0, b, c add t1, t0, d sub a, t1, e # t0 = b + c # t1 = t0 + d # a = t1 - e Compilers often use temporary variables when generating code Notice all of the comments! CMPE 325 Ch. #3 Slide #16 Data Representation Bits: 0 or 1 Bit strings – sequence of bits 8 bits is a byte 16 bits is a half-word 32 bits is a word 64 bits is a double-word Characters – one byte, usually using ASCII Integer numbers – stored in 2’s complement (reviewed in the next chapter) Floating point – uses a mantissa and exponential m 2e (also covered in the next chapter) CMPE 325 Ch. #3 Slide #17 Data Storage In high-level programs we store data in variables In practice, where is this data stored? The answer is that it can be stored in many different places Registers Cache (RAM or disk) Random Access Memory (RAM) Disk CMPE 325 Ch. #3 Slide #18 Register Organization Register organization is one of the defining aspects about a particular processor architecture Three basic mechanisms for operators/operands Accumulator – architecture which uses a single register for one of the sources and the destination (ex. 8088) Stack – operands are pushed and popped (ex, Intel MP) General Purpose – a limited number of registers used to store data for any purpose (ex. most systems today) A register is a small high-speed block of memory that holds data We will focus in this course on general purpose CMPE 325 Ch. #3 Slide #19 Accumulator Example Consider the code a = b + c; In an accumulator-based architecture load addressB add addressC store addressA CMPE 325 Ch. #3 Slide #20 General Purpose Registers When using General Purpose Registers (GPRs), data can access in different ways Load-Store (L/S) – data is loaded into registers, operated on, and stored back to memory (ex. all RISC instruction sets) • Hardware for operands is simple • Smaller is faster since clock cycle can be kept short Emphasis is on efficiency Memory-Memory – operands can use memory addresses as both a source and a destination (ex. Intel) CMPE 325 Ch. #3 Slide #21 MIPS Architecture MIPS is a load-store architecture Each register is 32 bits (word) wide The MIPS has 32 general purpose registers (some reserved for specific purposes) MIPS also has 32 floating point only registers CMPE 325 Ch. #3 Slide #22 Register Naming Registers are identified by a $<num> By convention, we also give them names $zero contains the hardwired value 0 $s0, $s1, … $s7 are for save values $t0, $t1, … $t9 are for temp values The others will be introduced as appropriate Compilers use these conventions to make linking a smooth process Unlike variables, there are a fixed number of data registers (“smaller is faster”) CMPE 325 Ch. #3 Slide #23 Using registers Goals Keep data in registers as much as possible Always use data still in registers if possible Issues Finite number of registers available • Spill registers to memory when all registers in use • Data must also be stored across procedures Arrays • Data is too large to store in registers • Need to compute index Dynamic memory allocation • Dynamically allocated data structures must be loaded one word at a time CMPE 325 Ch. #3 Slide #24 Arithmetic Operators: II Consider the C operation for addition where the variables are in $s0-$s2 respectively a = b + c; The add operator using registers add $s0, $s1, $s2 # a = b + c Use the sub operator for a=b–c in MIPS sub $s0, $s1, $s2 # a = b - c CMPE 325 Ch. #3 Slide #25 Complex Operations: II What about more complex statements? a = b + c + d - e; Break into multiple instructions add $t0, $s1, $s2 add $t1, $t0, $s3 sub $s0, $t1, $s4 # $t0 = b + c # $t1 = $t0 + d # a = $t1 - e CMPE 325 Ch. #3 Slide #26 Constants Often want to be able to add a constant Use the addi instruction addi dst, src1, immediate The immediate is a 16 bit value CMPE 325 Ch. #3 Slide #27 Constant Example Consider the following C code a++; The addi operator addi $s0, $s0, 1 # a = a + 1 CMPE 325 Ch. #3 Slide #28 MIPS Simple Arithmetic Instruction Example Meaning Comments add add $1,$2,$3 $1 = $2 + $3 3 operands; Exceptions subtract sub $1,$2,$3 $1 = $2 – $3 3 operands; Exceptions add immediate addi $1,$2,100 $1 = $2 + 100 + constant; Exceptions add unsigned addu $1,$2,$3 $1 = $2 + $3 3 operands; No exceptions subtract unsign subu $1,$2,$3 $1 = $2 – $3 3 operands; No exceptions add imm unsign addiu $1,$2,100 $1 = $2 + 100 + constant; No exceptions CMPE 325 Ch. #3 Slide #29 Putting Data in Registers Data transfer instructions are used to move data to and from memory in load-store A load operation moves data from memory to a register and a store operation moves data from a register to memory One word at a time is loaded from memory to a register on MIPS using the lw instruction Load instructs have three parts 1. 2. 3. Operator name Destination register Base register address and constant offset lw dst, offset(base) Offset value is signed (use ulw for unsigned) CMPE 325 Ch. #3 Slide #30 Memory Access All memory access happens through loads and stores Aligned words, halfwords, and bytes Floating Point loads and stores for accessing FP registers Displacement based addressing Immediate Registers Base Memory + CMPE 325 Ch. #3 Data to load/ location to store into Slide #31 Loading Data Example Consider the example a = b + *c; Use the lw instruction to load lw $t0, 0($s2) add $s0, $s1, $t0 # $t0 = Memory[c] # a = b + *c CMPE 325 Ch. #3 Slide #32 Accessing Arrays Arrays are really pointers to the base address in memory Use offset value to indicate which index Remember that addresses are in bytes, so multiply by the size of the element Consider an integer array where A is the base address The data to be accessed is at index 5 Then the address from memory is A + 5 * 4 Unlike C, assembly does not handle pointer arithmetic for you! CMPE 325 Ch. #3 Slide #33 Array Example Consider the example a = b + c[9]; Use the lw instruction offset lw $t0, 36($s2) add $s0, $s1, $t0 # $t0 = Memory[c[9]] # a = b + c[9] CMPE 325 Ch. #3 Slide #34 Complex Array Example Consider the example a = b + c[i]; First find the correct offset add $t0, $s3, $s3 add $t0, $t0, $t0 add $t1, $s2, $t0 lw $t2, 0($t1) add $s0, $s1, $t2 # # # # # $t0 $t0 $t1 $t2 a = = = = = b 2 * i 4 * i c + 4*i Memory[c[i]] + c[i] Note: Multiply will be covered later CMPE 325 Ch. #3 Slide #35 Storing Data Storing data is just the reverse and the instruction is nearly identical Use the sw instruction to copy a word from the source register to an address in memory sw src, offset(base) Offset value is signed (usw for unsigned) CMPE 325 Ch. #3 Slide #36 Storing Data Example Consider the example *a = b + c; Use the sw instruction to store add $t0, $s1, $s2 sw $t0, 0($s0) # $t0 = b + c # Memory[s0] = b + c CMPE 325 Ch. #3 Slide #37 Storing to an Array Consider the example a[3] = b + c; Use the sw instruction offset add $t0, $s1, $s2 sw $t0, 12($s0) # $t0 = b + c # Memory[a[3]] = b + c CMPE 325 Ch. #3 Slide #38 Complex Array Storage Consider the example a[i] = b + c; Use the sw instruction offset add $t0, $s1, $s2 add $t1, $s3, $s3 add $t1, $t1, $t1 add $t2, $s0, $t1 sw $t0, 0($t2) # # # # # CMPE 325 Ch. #3 $t0 = b + c $t1 = 2 * i $t1 = 4 * i $t2 = a + 4*i Memory[a[i]] = b + c Slide #39 MIPS Load/Store Instruction Example Meaning Comments store word sw $1, 8($2) Mem[8+$2]=$1 Store word store half sh $1, 6($2) Mem[6+$2]=$1 Stores only lower 16 bits store byte sb $1, 5($2) Mem[5+$2]=$1 Stores only lowest byte store float sf $f1, 4($2) Mem[4+$2]=$f1 Store FP word load word lw $1, 8($2) $1=Mem[8+$2] Load word load halfword lh $1, 6($2) $1=Mem[6+$2] Load half; sign extend load half unsign lhu $1, 6($2) $1=Mem[8+$2] Load half; zero extend load byte lb $1, 5($2) $1=Mem[5+$2] Load byte; sign extend load byte unsign lbu $1, 5($2) $1=Mem[5+$2] Load byte; zero extend load float lf $f1, 4($2) $f1=Mem[4+$2] Load FP register CMPE 325 Ch. #3 Slide #40 Memory Addressing Almost all architectures support byte addressing as well as word addressing Different architectures have different ways of ordering the bits, known as the byte order Some architectures limit the way data is stored so as to improve efficiency CMPE 325 Ch. #3 Slide #41 Byte Ordering Two basic ways of ordering bits Big Endian – the “big” end comes first and the most significant bit (MSB) is the lowest memory address Little Endian – the “little end” comes first and the least significant bit (LSB) is the first address (ex. Intel) Some systems such as MIPS and PowerPC can do both, but are primarily big endian 3 2 1 Little Endian byte 0 0 msb lsb 0 1 2 3 Big Endian byte 0 CMPE 325 Ch. #3 Slide #42 Byte Ordering Example Consider the following word (32 bits) of memory Little Endian LSB Big Endian MSB Memory Address Little Endian MSB Big Endian LSB AB CD 00 00 0 1 2 3 Big endian interprets as AB CD 00 00 (2882338816) Little endian interprets as 00 00 CD AB (52651) CMPE 325 Ch. #3 Slide #43 Alignment Restrictions In MIPS, data is required to fall on addresses that are even multiples of the data size 0 1 2 3 Aligned Not Aligned Consider word (4 byte) memory access 0 4 8 12 16 0 4 8 12 16 CMPE 325 Ch. #3 Slide #44 Assembly Language Programming Environment MIPS Assembly Language Syntax: a) Numbers are base 10 b) Hex numbers are preceded “0x”. c) Special string characters: 1) newline \n 2) tab \t 3) quote \” d) Labels are followed by “:” e) Identifiers begin with letter and may contain alphanumeric, underscore, and dots. f) Keywords: Instruction opcodes can not be used as identifiers. g) Comments begin with a “#” symbols and run to end-of-line. h) Assembly language statements cannot be split across multiple lines. CMPE 325 Ch. #3 Slide #45 Assembly Language Programs Example w/basic elements: # Program name, description and comments .data # data segment item: .word 10 # define/name a variable and initial value .text .globl main main: lw # code segment # must be global; # your code goes here $t0, item li $v0, 10 syscall .end # exit to kernel CMPE 325 Ch. #3 Slide #46 Assembly Language Conventions: SPIM Assembler Directives: .data Subsequent data items stored in user(kernel) data segment(.kdata) .text Subsequent items are stored in user(kernel) text segment (.ktext) .asciiz str Store ascii string in memory and zero terminate .word w1,… Store 32 bit words in memory .half h1,… Store 16 bit half-words in memory .byte b1,… Store 8 bit bytes in memory .double d1,… Store 64 bit words in memory .space nbytes Allocate nbytes of space in current segment .globl sym, Declare label sym global. Can be referenced from other files .align n Align next datum on a 2^n boundary CMPE 325 Ch. #3 Slide #47 Assembly Language Instructions: MIPS Instruction classes and format conventions: MIPS Core Instructions Add: Add Immediate: Add Immediate Unsigned: Add Unsigned: And: And Immediate: Branch if Equal: Branch if Not Equal: Jump: Jump and Link: Jump Register: Load Byte: Load Byte Unsigned: Load Upper Immediate: Load Word: Or: Or Immediate: Set on Less Than: Set on Less Than Immediate: Set on Less Than Immediate Unsigned: Set on Less Than Unsigned: Shift Left Logical: Shift Right Logical: Subtract: Subtract Unsigned: Store Byte: Store Word: Operation add addi addiu addu and andi beq bne j jal jr lb lbu lui lw or ori slt slti sltiu sltu sll srl sub subu sb sw Operands Rd, Rs, Rt Rt, Rs, Imm Rt, Rs, Imm Rd, Rs, Rt Rd, Rs, Rt Rt, Rs, Imm Rs, Rt, Label Rs, Rt, Label Label Label Rs Rt, offset(Rs) Rt, offset(Rs) Rt, Imm Rt, offset(Rs) Rd, Rs, Rt Rt, Rs, Imm Rd, Rt, Rs Rt, Rs, Imm Rt, Rs, Imm Rd, Rt, Rs Rd, Rt, sa Rd, Rt, sa Rd, Rs, Rt Rd, Rs, Rt Rt, offset(Rs) Rt, offset(Rs) Size/Clocks 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 MIPS Arithmetic Core Instructions Divide: Divide Unsigned: Move From High: Move From Low: Multiply: Multiply Unsigned: Operation div divu mfhi mflo mult multu Operands Rs, Rt Rs, Rt Rd Rd Rs, Rt Rs, Rt Size/Clocks 1/38 1/38 1/1 1/1 1/32 1/32 CMPE 325 Ch. #3 Slide #48 Assembly Language Instruction: (cont) MIPS I Instructions (remaining) Branch if Greater Than or Equal to Zero: Branch if Greater Than or Equal to Zero and Link: Branch if Greater Than Zero: Branch if Less Than or Equal to Zero: Branch if Less Than Zero and Link: Branch if Less Than Zero: Cause Exception: Exclusive Or: Exclusive Or Immediate: Jump and Link Register: Load Halfword: Load Halfword Unsigned: Load Word Left: Load Word Right: Move to High: Move to Low: Nor: Return from Exception Shift Left Logical Variable: Shift Right Arithmetic: Shift Right Arithmetic Variable: Shift Right Logical Variable: Store Halfword: Store Word Left: Store Word Right: System Call: Operations bgez bgezal bgtz blez bltzal bltz break xor xori jalr lh lhu lwl lwr mthi mtlo nor rfe sllv sra srav srlv sh swl swr syscall Operands Rs, Label Rs, Label Rs, Label Rs, Label Rs, Label Rs, Label Rd, Rs, Rt Rt, Rs, Imm Rd, Rs Rt, offset(Rs) Rt, offset(Rs) Rt, offset(Rs) Rt, offset(Rs) Rs Rs Rd, Rs, Rt Rd, Rt, Rs Rd, Rt, sa Rd, Rt, Rs Rd, Rt, Rs Rt, offset(Rs) Rt, offset(Rs) Rt, offset(Rs) Size/Clocks 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 Operands 1) Register names Rd, Rs, Rt (d=destination, s=source, t=second source/dest) 2) Immediate value Imm, sa, offset (Numeric expr= 16 bits,shift amount, offset) 3) Address label Label(28 or 16 bits) CMPE 325 Ch. #3 Slide #49 Assembly Language Instruction: (cont) Pseudo Instructions Operations Absolute Value: abs Branch if Equal to Zero: beqz Branch if Greater Than or Equal : bge Branch if Greater Than or Equal Unsigned: bgeu Branch if Greater Than: bgt Branch if Greater Than Unsigned: bgtu Branch if Less Than or Equal: ble Branch if Less Than or Equal Unsigned: bleu Branch if Less Than: blt Branch if Less Than Unsigned: bltu Branch if Not Equal to Zero: bnez Branch Unconditional: b Divide: div Divide Unsigned: divu Load Address: la Load Double: ld Load Immediate: li Move: move Multiply: mul Multiply (with overflow exception): mulo Multiply Unsigned (with overflow exception): mulou Operands Rd, Rs Rs, Label Rs, Rt, Label Rs, Rt, Label Rs, Rt, Label Rs, Rt, Label Rs, Rt, Label Rs, Rt, Label Rs, Rt, Label Rs, Rt, Label Rs, Label Label Rd, Rs, Rt Rd, Rs, Rt Rd, Label Rd, Label Rd, value Rd, Rs Rd, Rs, Rt Rd, Rs, Rt Rd, Rs, Rt CMPE 325 Ch. #3 Size/Clocks 3/3 1/1 2/2 2/2 2/2 2/2 2/2 2/2 2/2 2/2 1/1 1/1 4/41 4/41 2/2 2/2 2/2 1/1 2/33 7/37 5/35 Slide #50 Assembly Language Instruction: (cont) Pseudo Instructions Operations Negate: neg Negate Unsigned: negu Not: not Nop: nop Remainder: rem Remainder Unsigned: remu Rotate Left: rol Rotate Right ror Rotate Left, variable: rol Rotate Right, variable ror Set on Equal: seq Set on Not Equal: sne Set on Greater Than: sgt Set on Greater Than Unsigned: sgtu Set on Greater Than or Equal: sge Set on Greater Than or Equal Unsigned: sgeu Set on Less Than or Equal: slte Set on Less Than or Equal Unsigned: slteu Store Double: sd Unaligned Load Half Word: ulh Unaligned Load Half Word Unsigned: ulhu Unaligned Load Word: ulw Unaligned Store Half Word: ush Unaligned Store Word: usw Operands Rd, Rs Rd, Rs Rd, Rs Rd, Rs, Rt Rd, Rs, Rt Rd, Rs, sa Rd, Rs, sa Rd, Rs, Rt Rd, Rs,Rt Rd, Rt, Rs Rd, Rt, Rs Rd, Rt, Rs Rd, Rt, Rs Rd, Rt, Rs Rd, Rt, Rs Rd, Rt, Rs Rd, Rt, Rs Rd, Label Rd, Label Rd, Label Rd, Label Rd, Label Rd, Label CMPE 325 Ch. #3 Size/Clocks 1/1 1/1 1/1 1/1 4/41 4/41 3/3 3/3 4/4 4/4 4/4 4/4 1/1 1/1 4/4 4/4 4/4 4/4 2/2 4/4 4/4 2/2 3/3 2/2 Slide #51 Classic Organization of a Computer: MIPS CPU Control Unit Program Counter Immediate Rd 0 . . 31 Register File ALU Arithmetic Logical Unit Hi/Lo register pair(64) Rs 32 registers (32 bit/register) Coprocessor_0 Exception Handler Status Register Cause Register Rt 32 bit address and 32 bit data buses 0x00000000 MEMORY Linear array of binary word(bytes) RAM, ROM, IO Devices 0xFFFFFFFF CMPE 325 Ch. #3 Slide #52 Assembly Language Conventions: MIPS Register Usage and Naming Conventions Register Name 0 $zero 1 $at Usage Default Reserved for assembler, pseudo-instruction 2-3 4-7 $v0,$v1 Return function values $a0-$a3 Function arguments 8-15, 24-25 16-23 $t0-$t7, Caller saved temporaries( not preserved across call) $t8,$t9 $s0-$s7 Callee saved temporaries(preserved across call) 26-27 28 29 30 31 $k0,$k1 $gp $sp $fp $ra Reserved for kernel/OS Pointer to global data area Stack pointer. SPIM initializes to 0x7FFF FFFC Frame pointer Return address Used by “link” instruction(HW) CMPE 325 Ch. #3 Slide #53 Assembly Language Memory Architecture/Organization: MIPS Memory Usage/Allocation: Address 0x0000 0000 -0x003F FFFF Memory Usage .vect Reserved by kernel 0x0040 0000 -0x1000 0000 .text User Code_section 0x1000 0000 -0x1001 0000 0x1001 0000 - .data Reserved global data $gp = 0x1000 8000 User Data_section 0x xxxx xxxx -0x7FFF FFFC $sp =0x7FFF FFFC .stack Heap <=> Stack User stack pointer 0x8000 0180 -0x9000 0000 0x9000 0000 -0x9001 0000 .ktext .kdata Reserved, kernel code Reserved, kernel data CMPE 325 Ch. #3 Slide #54 Changing Control One of the distinguishing characteristics of computers is the ability to evaluate conditions If-then-else Loops Case statements Also important to change the control flow Conditional instructions are known as branches Unconditional changes in the control flow are called jumps The target of the branch/jump is a label CMPE 325 Ch. #3 Slide #55 Conditional: Equality The simplest conditional test is the beq instruction for equality beq reg1, reg2, label Consider the code L1: if (a == b) goto L1; // Do something // Continue Use the beq instruction L1: beq $s0, $s1, L1 # Do something # Continue CMPE 325 Ch. #3 Slide #56 Conditional: Not Equal The bne instruction for not equal bne reg1, reg2, label Consider the code L1: if (a != b) goto L1; // Do something // Continue Use the bne instruction L1: bne $s0, $s1, L1 # Do something # Continue CMPE 325 Ch. #3 Slide #57 Unconditional: Jumps The j instruction jumps to a label j label CMPE 325 Ch. #3 Slide #58 If-then-else Example Consider the code if (i == j) f = g + h; else f = g – h; if (condition) clause1; else clause2; (true) i == j f=g+h if (condition) goto L1; clause2; goto L2; L1: clause1; L2: CMPE 325 Ch. #3 (false) i == j? i != j f=g-h Exit Slide #59 If-then-else Solution f g h i j => => => => => $s0 $s1 $s2 $s3 $s4 Create labels and use equality instruction True: Exit: beq $s3, $s4, True sub $s0, $s1, $s2 j Exit add $s0, $s1, $s2 # # # # Branch if i == j f = g – h Go to Exit f = g + h Compiler frequently generates many labels even if they do not appear in C code Common to reverse condition to make simpler flow control CMPE 325 Ch. #3 Slide #60