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Fast Frequency Acquisition Phase-Frequency Detectors for GSa/s PhaseLocked Loops Mozhgan Mansuri1, Dean Liu2 and Chih-Kong Ken Yang1 1University of California at Los Angeles, 2Stanford University Abstract This paper describes two techniques for designing phase-frequency detectors (PFDs) with higher operating frequencies (periods of less than 8x the delay of a fanout-4 inverter (FO-4)) and faster frequency acquisition. Prototypes designed in 0.25-µm CMOS process exhibit operating frequencies of 1.25 GHz ( = 1 ⁄ (8 ⋅ F O – 4) ) and 1.5 GHz ( = 1 ⁄ ( 6.7 ⋅ F O – 4 ) ) for two techniques respectively whereas a conventional PFD operates <1 GHz ( = 1 ⁄ ( 10 ⋅ F O – 4 ) ). The two proposed PFDs achieve a capture range of 1.7x and 1.2x the conventional design. 1. Introduction (PLLs) have been widely used in high-performance microprocessors and high-speed digital communication systems as a clock generator. As the speed of these systems is increasing, PLLs with higher operating frequency and lower jitter are in demand. A common architecture for clock generation uses a phase-frequency detector (PFD) for simultaneous phase and frequency acquisition. Applications requiring a low-jitter clock output increases the difficulty of the design of the PFDs because they prefer a high input clock frequency and minimum multiplication. As will be described in Section 2, the speed of the conventional NAND flip-flop (FF) phase-frequency detectors (PFDs) limits the operating frequency and slows the frequency acquisition. This paper describes two improved PFD designs. Section 3 presents the detail circuits of the proposed PFDs and experimental results. from an initial state to an up or down state. The state is held until the second input goes high which in turn resets the circuit and returns the FSM to the initial state. The PFD’s characteristic is ideally linear for the entire range of input phase from -2π to 2π (Figure 2-a). When the inputs differ in frequency, the phase difference changes each cycle by ∆φ = 2π ⋅ ( T CK – T CK ) ⁄ max ( T CK , T CK ) . On ref out ref out every clock cycle during frequency acquisition, the phase difference steps across the PFD transfer curve from 0 to +/-2π and repeats as the output clock cycle slips. The control voltage of voltage-controlled oscillator (VCO) is pumped monotonically toward that of the desired frequency. As the frequency error decreases, the sweep slows until the frequency difference is within the lock-in range. CKref Q DFF Up=0 Dn=1 Down State CKout CKref R Up=0 Dn=0 Reset CKref R DFF D Initial State Dn Q CKout Up State Up=1 Dn=0 CKout Figure 1: Linear PFD architecture and its state diagram Vout -2π 2π 2. Architecture Figure 1 illustrates a common linear PFD architecture using resettable D-flip-flops (DFFs) and its state diagram. The PFD generates up and dn signals that switch the current of a charge pump. The DFFs are triggered by the inputs to the PFD. Initially, both outputs are low. When one of the PFD inputs rises, the corresponding output becomes high. The state of FSM moves Up D ∆φ Up CKref PFD CKout Dn a. Ideal Vout CKref -2π 2π ∆ ∆φ CKout ∆φ b. Non-Ideal Figure 2: Linear PFD characteristic Charge Pump Vout C Note that because the voltage is integrated, the voltage accumulates quadratically between each slip of the clock cycle. Once within the lock-in range, the cycle slipping stops and the phase is acquired as a linear system. However due to the delay of the reset path, the linear range is less than 4π (Figure 2-b). Figure 3 illustrates the non-ideal behavior with the reference clock (CKref) leading the output clock (CKout) causing an up output. As the input phase difference nears 2π, the next leading edge (CKref) arrives before the DFFs are reset due to the finite reset delay. The reset overrides the new CKref and does not assert up. The subsequent CKout edge causes a dn signal. The effect appears as a negative output for phase differences higher than 2π – ∆ where ∆ = 2π ⋅ t reset ⁄ T cyc which depends on the reset path delay (treset) and the clock period (Tcyc). Note that treset is determined by the delay of logic gates in reset path and is not a function of either input frequency. thereby limiting the maximum clock period to 10.6 FO4. The first proposed design is shown in Figure 4-a. The PFD is similar to a dynamic two-phase master-slave pass-transistor flip-flop. Only single-edge clocks are used to minimize clock skew. As both outputs become high, the slave is reset asynchronously while the master is reset synchronously i.e., the reset is allowed only when the slave latch is transparent. If the master latch is reset while it is transparent, then there will be significant short-circuit current, resulting in excessive power consumption. The synchronized reset transistors (N1 and N4), must be at the bottom of the stack because rst is the late arriving signal when the nodes out and ref are reset. CKout P2 out P1 Up P2 Up N3 N2 N1 RST Missing Clock Edge CKref P4 CKref ref CKout P3 Up N5 Dn N4 a. Circuit Reset Figure 3: PFD non-ideal behavior due to non-zero reset delay During acquisition, the frequency will not monotonically approach lock-in range because the non-ideal PFD gives the wrong information periodically. The acquisition slows by how often the wrong information occurs which depends on ∆. At an input frequency ( T CK ref = 2 ⋅ t reset ) where ∆ equals π, the PFD outputs the wrong information half the time and thereby fails to acquire. The maximum operating frequency can 1 2 ⋅ t reset be expressed as f ref ≤ --------------------. The next section describes two proposed designs that significantly improves fref. 3. Circuits and Measurement A commonly used PFD design is one used in [4] using NAND-based latches to build the flip-flops.The reset path includes one 2-input NAND, one 4-input NAND and two 3-input NANDs. We characterize the reset delay by normalizing it with the delay of a fan-out of 4 inverter to remove process/voltage/temperature dependence. The design measures a delay of 5.3 FO-4 Dn P4 Dn N6 b. Reset path Figure 4: A pass-transistor DFF PFD architecture The reset circuit shown in Figure 4-b includes one pass transistor, one inverter and one NAND gate. In order to properly reset the slave, the pass-transistor output should become high before the master becomes transparent. Hence, the NAND gate delay is counted twice in delay path. The smaller gates in the reset path as compared to the previous design reduces treset to 4.4 FO-4 and Tref by 17% to 8.8 FO-4. In the second proposed design, pulsed latches are used instead of flip-flops which fundamentally changes the dependence on the reset delay. This is illustrated in Figure 5-a with the same case as before.When CKref arrives during the reset, the edge information propagates to the output as long as CKref is still high (level-sensitive) when the reset period ends. The PFD no longer loses the edge that arrives during reset and does not output the wrong direction. However, since the PFD output asserts at the end of the reset (∆), the output pulse width would be constant (2π−∆) for phase differences greater than 2π−∆. The characteristic is shown in Figure 5-b. The input pulse widths should be designed to be slightly smaller than treset so that an input that triggers the reset would not assert the output after the reset pulse ends. This results in negative output voltage for ∆φ > 2π – δ shown in Figure 5-b. Note that this PFD has faster acquisition rate compared to the first type (with the same operating frequency) because it does not output incorrect phase information. However, the PFD has a gain that saturates when the input difference is larger than 2π−∆. CKref CKout Up Dn Reset a. PFD behavior ∆ Vout −2π −π π 2π period. Therefore δ is no longer constant and grows with increasing frequency. The PFD fails as frequency 1 approaches ------------ which is potentially twice that of the t reset previously proposed PFD for the same treset. Consequently the maximum frequency is higher than the DFFbased designs despite longer treset. The higher performance is at a cost of 3x the power as compared to the first proposed circuit due to DC current and extra power consumption in the delay circuit. When the reset node and clock inputs are simultaneously low and high respectively, the DC current flows through N1, N2, N3 and P1 or (N4, N5, N6 and P2). Figure 7 illustrates the transfer curve of all three designs for reference clock of 435 MHz ( = 1 ⁄ ( 20 ⋅ F O – 4 ) ). Vout ∆φ δ b. Characteristic Figure 5: A latch-based PFD characteristic -2 -1.6 P2 0.4 0.8 1.2 -1.2 -0.8 -0.4 1.6 2 (× π) ∆φ P1 Dn Up CKref Pass Transistor DFF PFD Latch-based PFD NAND DFF PFD N1 N4 N5 N2 CKout Generates Pulsed Clock D N6 N3 Inverted Delay D Figure 7: The characteristics of three PFDs @ 435 MHz Inverted Delay a. Circuit 1.28 VCO control voltage (volt) 1.24 Latch-based PFD 1.2 Pass transistor DFF PFD b. Reset path Figure 6: A latch-based PFD architecture Figure 6-a illustrates a design of the latch-based PFD, using glitch latches[2]. The delay elements controls the pulse width of the clocks. The reset circuit shown in Figure 6-b includes two inverters and one NAND. The reset also traverses the circuit twice because the reset should return high. Therefore, treset delay is roughly 5.5 FO-4 and contains three inverters and two NANDs. As the clock period is less than twice the pulse width, the clock pulses from N2(N5) and N3(N6) are no longer constant width but reduce with the 1.16 NAND DFF PFD 1.12 1.08 1.04 1 20n 60n 100n 140n 180n 220n 260n Time (sec) Figure 8: Simulated frequency acquisition Figure 8 compares the simulated frequency acquisition for three PFDs, starting the VCO at 375 MHz and locking at 800 MHz.The PLL [1] and PFD test circuits are fabricated in a 0.25-µm CMOS technology. The first and second circuits shows a 18.5% and 41.7% improvements in maximum locking frequency compared to NAND DFF PFD respectively. The measurement results match the simulated FO-4 results. The measured frequency acquisition time of PLLs are depicted in Figure 9 for all three PFDs. To analyze the frequency acquisition, a reference clock of 1 GHz is supplied while the VCO frequency is reset to 200 MHz. Sampling circuits monitor the VCO control voltage as the PLL’s reset is disabled. The loop acquires lock with a slightly underdamped behavior. The latch-based PFD has an acquisition rate of 1.7x NAND DFF PFD and 1.4x pass transistor DFF PFD. Note that the PFD with fast acquisition has larger lock-in range. The power consumption is calculated for PFDs in the lock mode for the PLL reset VCO control voltage Latch-based PFD Pass transistor DFF PFD NAND DFF PFD reference clock of 500 MHz.The pass-transistor DFF PFD consumes the least power as predicted. Table 1 summarizes the measured and simulated performance of each PFD. 4. Conclusion This paper demonstrates two techniques for designing PFDs with operating clock period less than 8 FO-4 without using frequency division. Even for high-performance systems with clock periods greater than 8 FO-4, the proposed PFDs acquire frequency lock more quickly. Low-jitter clocks for microprocessor or digital communication can be generated. We acknowledge our industrial sponsors that are part of this Micro Project 00-111, Intel Corp. and especially National Semiconductor for fabrication. References [1] S. Sidiropoulos, et al., “Adaptive Bandwidth DLLs and PLLs using Regulated Supply CMOS Buffers,” Proceedings of 2000 IEEE Symposium on VLSI Circuits, Dig. Tech. Papers, Jun. 2000, Hawaii, pp. 124-127 [2] H. Partovi, et al., “Flow-Through Latch and Edge-Triggered Flip-Flop Hybrid Elements,” ISSCC Dig. of Tech. Papers, Feb. 1996, San Francisco, pp. 138-139 [3] H. Notani, “A 622-MHz CMOS PLL with precharge-type phase frequency detector,” in Dig. Tech. Papers, VLSI Symposium 1994 [4] H. Ebenhoech, “Make IC digital frequency comparators,” Electron. Des., vol. 15, no. 14, pp. 62-64, July 5, 1967 Figure 9: Measured frequency acquisition Table 1: PFDs performance summary NAND FF PFD (Type I) Pass Transistor FF PFD (Type I) Latch-based PFD (Type II) Maximum operating frequency (Measurement) 1.08 GHz 1.28 GHz 1.53 GHz Maximum operating frequency (Simulation) 0.945 GHz 1.14 GHz 1.5 GHz Lock-in range @ 1 GHz (Measurement) 133 MHz 160 MHz 200 MHz Power 1.65 mW 0.62 mW 1.4 mW