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IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 7, NO. 1, MARCH 2007
181
Impact of Strain or Ge Content on the Threshold
Voltage of Nanoscale Strained-Si/SiGe
Bulk MOSFETs
M. Jagadesh Kumar, Senior Member, IEEE, Vivek Venkataraman, Student Member, IEEE, and Susheel Nawal
Abstract—The impact of strain on the threshold voltage of
nanoscale strained-Si/SiGe MOSFETs is studied by developing
a compact analytical model. Our model includes the effects of
strain (Ge mole fraction in SiGe substrate), short-channel length,
source/drain junction depths, substrate (body) doping, strained
silicon thin-film thickness, gate work function, and other device
parameters. The model correctly predicts a decrease in threshold
voltage with increasing strain in the silicon thin film, i.e., with
increasing Ge concentration in SiGe substrate. The accuracy of
the results obtained using our analytical model is verified using
two-dimensional device simulations.
Index Terms—Nanoscale strained-Si/SiGe MOSFET, shortchannel effects, simulation, threshold voltage, two-dimensional
modeling.
nanoscale MOSFETs including the short-channel effects. The
effect of varying device parameters can easily be investigated
using the analytical model presented in this paper. The model
results are verified by comparing them with the 2-D simulation
results obtained using MEDICI [14].
II. E FFECT OF S TRAIN
A silicon thin film grown pseudomorphically over a relaxed Si1−x Gex substrate experiences biaxial tension leading to
changes in band structure [10], [11]. Due to strain, the electron
affinity of silicon increases and the bandgap decreases. Also,
the effective mass of carriers decreases. The effect of strain on
Si band structure can be modeled as [10], [11], [15]
I. I NTRODUCTION
S
TRAINED-SILICON devices have been receiving considerable attention owing to their potential for achieving
higher performance due to improved carrier-transport properties, i.e., mobility and high-field velocity [1], and compatibility
with conventional silicon processing [2]–[9]. Tremendous improvement in static and dynamic CMOS circuit performance
has been demonstrated using strained-Si/SiGe MOSFETs [5].
Studying the impact of strain on the threshold voltage of
nanoscale strained-Si devices becomes necessary for future
device and circuit design. Earlier works on the threshold voltage
of strained-Si/SiGe MOSFETs [10], [11] have concentrated on
the band offsets due to strain and modified the long-channel
threshold voltage model. One-dimensional Poisson equation
solution has also been considered [12], [13]; however for
short-channel devices, 2-D effects such as the influence of
source/drain (S/D) depletion widths becomes important. The
aim of this paper is, therefore, to study the impact of strain on
the threshold voltage of short-channel (sub 100 nm) nanoscale
strained-Si/SiGe MOSFETs by solving the 2-D Poisson equation in the strained-Si thin film and analyzing the dependence
of threshold voltage on various device parameters such as strain
(Ge mole fraction in SiGe), gate length, junction depth, etc.
This model thus provides an efficient tool for design
and characterization of high-performance strained-Si/SiGe
Manuscript received July 19, 2006; revised September 5, 2006.
The authors are with the Department of Electrical Engineering, Indian
Institute of Technology, Delhi, New Delhi 110 016, India (e-mail: mamidala@
ieee.org).
Digital Object Identifier 10.1109/TDMR.2006.889269
(∆Eg )s−Si = 0.4x
(∆EC )s−Si = 0.57x,
3/2
m∗h,Si
NV,Si
≈ 0.075x
VT ln
= VT ln
NV,s−Si
m∗h,s−Si
(1)
where x is the Ge mole fraction in Si1−x Gex substrate,
(∆EC )s−Si is the increase in electron affinity of silicon due
to strain, (∆Eg )s−Si is the decrease in bandgap of silicon due
to strain, VT is the thermal voltage, NV,Si and NV,s−Si are
the density of states (DOS) in the valence band in normal
and strained silicon, respectively, m∗h,Si and m∗h,s−Si are the
hole DOS effective masses in normal and strained silicon, respectively. The band structure parameters for relaxed Si1−x Gex
substrate can also be estimated as [14]–[16]
(∆Eg )SiGe = 0.467x
NV,SiGe = (0.6x + 1.04(1 − x)) × 1019 cm−3
εSiGe = 11.8 + 4.2x
(2)
where (∆Eg )SiGe is the decrease in bandgap of Si1−x Gex from
that of Si, NV,SiGe is the DOS in the valence band in relaxed
Si1−x Gex , and εSiGe is the permittivity of Si1−x Gex .
The flatband voltage of a MOSFET is thus modified due to
strain as [11]
(VFB,f )s−Si = (VFB,f )Si + ∆VFB,f
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IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 7, NO. 1, MARCH 2007
where
(VFB,f )Si = φM −φSi
∆VFB,f =
−(∆EC )s−Si (∆Eg )s−Si
+
−VT ln
q
q
NV,Si
NV,s−Si
(4)
χSi Eg,Si
+
+ φF,Si
q
2q
NA
= VT ln
.
ni,Si
φSi =
φF,Si
(5)
In the above relations, φM is the gate work function, φSi is
the unstrained Si work function, φF,Si is the Fermi potential in
unstrained Si, χSi is the electron affinity in unstrained Si, Eg,Si
is the bandgap in unstrained Si, q is the electronic charge, NA is
the body doping concentration and ni,Si is the intrinsic carrier
concentration in unstrained Si.
The built-in voltage across the source-body and drain-body
junctions in the strained-Si thin film is also affected by strain as
Vbi,s−Si = Vbi,Si + (∆Vbi )s−Si
Fig. 1. Cross-sectional view of the strained-Si/SiGe MOSFET showing the
depletion regions.
(6)
where
Vbi,Si =
(∆Vbi )s−Si
Eg,Si
+ φF,Si
2q
−(∆Eg )s−Si
+ VT ln
=
q
NV,Si
NV,s−Si
.
(7)
The built-in voltage across the source-body and drain-body
junctions in the relaxed Si1−x Gex substrate can be written as
Vbi,SiGe = Vbi,Si + (∆Vbi )SiGe
(8)
Fig. 2. Box approximation of the depletion region for solving 2-D Poisson
equation.
where
Vbi,Si =
(∆Vbi )SiGe =
Eg,Si
+ φF,Si
2q
−(∆Eg )SiGe
+ VT ln
q
NV,Si
NV,SiGe
.
(9)
III. T HRESHOLD V OLTAGE M ODEL
Fig. 1 shows the cross section of a short-channel strainedSi/SiGe nMOSFET with depletion regions also indicated. The
depletion region under the gate for short-channel MOSFETs
is not uniform, and is affected by the lateral source-body and
drain-body depletion widths (xdl ) and their respective charges,
as shown in Fig. 1. The exact solution of the 2-D Poisson
equation for such a case is too complicated and would most
probably require numerical methods and iterations. To obtain a
meaningful analytical solution, Fig. 1 is transformed to a boxtype approximation of the depletion region as shown in Fig. 2
with a uniform charge density NA,eff and a uniform depth of
depletion thickness xd . The gate-S/D charge sharing [17] and
source-body/drain-body built-in potential barrier lowering [18]
due to overlap of the lateral source-body and drain-body depletion regions (xdl in Fig. 1) become important as the channel
length reduces. To incorporate these short-channel effects, the
effective doping NA,eff is defined taking into account only the
effective charge under the influence of the gate [17] as
rj
2xdν
−1
1+
NA,eff = NA 1 −
(10)
rj
L
where
xdν =
2εSiGe (φth − Vsub )
qNA
φth = 2φF,Si + ∆φs−Si
∆φs−Si
−(∆Eg )s−Si
+ VT ln
=
q
NV,Si
NV,s−Si
xdν is the vertical depletion region depth due to gate bias only,
φth is the minimum surface potential required for inversion
[11], rj is the S/D junction depth, L is the channel or gate
length, and Vsub is the substrate bias. φth is that value of
surface potential at which the inversion electron charge density
in the strained-Si device is the same as that in unstrained-Si at
threshold [11] (i.e., ∆φs−Si = 0 for unstrained-Si). The above
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KUMAR et al.: IMPACT OF STRAIN OR Ge CONTENT ON THE THRESHOLD VOLTAGE
approach is analogous to the one used in [13], where a voltagedoping transformation [19] is used to define an effective doping
to extend the long-channel threshold voltage model to the shortchannel case.
To complete the box approximation, an average vertical
depletion region depth (xd in Fig. 2) is calculated using simple
geometry (see Appendix) from Fig. 1 as
2xdl rj + 4π xdl + (L − 2xdl ) xdν
for L ≥ 2xdl
xd ∼
=
L
(11)
2
∼ rj + x2 − L + θ xdl for L ≤ 2xdl
xd =
(12)
dl
4
2
where θ = sin−1 (L/2xdl ) and xdl = 2εSiGe Vbi,SiGe /qNA is
the lateral source-body and drain-body depletion region width.
It can be seen that in the case of large channel length, i.e.,
L 2xdl , (11) reduces to xd ≈ xdν . Also, for extremely shortchannel lengths, i.e., L 2xdl , (12) reduces to xd ≈ rj + xdl .
These results are along expected lines. For L = 2xdl , (11) and
(12) yield the same value for xd .
For the simplified structure in Fig. 2, the 2-D Poisson equation in the strained silicon thin film, before the onset of strong
inversion can be written as [20]
qNA,eff
d2 φ1 (x, y) d2 φ1 (x, y)
+
=
dx2
dy 2
εSi
for 0 ≤ x ≤ L, 0 ≤ y ≤ ts−Si
(13)
where εSi is the dielectric constant of silicon, and ts−Si is the
strained-Si thin-film thickness. The potential profile in the vertical direction in the strained-Si film (y-direction in Fig. 2) and
the depletion region in the SiGe substrate below (y -direction
in Fig. 2) can be approximated by a parabolic function, as done
in [20] as
φ1 (x, y) = φs (x) + c11 (x)y + c12 (x)y 2
for 0 ≤ x ≤ L, 0 ≤ y ≤ ts−Si
(14)
φ2 (x, y ) = Vsub + c21 (x)y + c22 (x)y 2
for 0 ≤ x ≤ L, 0 ≤ y ≤ tSiGe
183
2) Electric flux/field at the end of the depletion region (y =
0 in Fig. 2) in the SiGe substrate is zero.
dφ2 (x, y )
= 0.
(17)
dy y =0
3) Potential at the interface of strained-Si thin-film and SiGe
substrate is continuous.
φ1 (x, ts−Si ) = φ2 (x, tSiGe ).
(18)
4) Electric flux (displacement) at the interface of strained-Si
thin-film and SiGe substrate is continuous.
dφ1 (x, y)
εSiGe dφ2 (x, y )
=−
. (19)
dy
εSi
dy y=ts−Si
y =tSiGe
5) The surface potential at the source end is
φ1 (0, 0) = φs (0) = Vsub + Vbi,s−Si .
(20)
6) The surface potential at the drain end is
φ1 (L, 0) = φs (L) = Vsub + Vbi,s−Si + VDS .
(21)
where VDS is the drain-to-source bias voltage.
The coefficients c11 (x), c12 (x), c21 (x), and c22 (x) in
(14) and (15) can be deduced from the boundary conditions
(16)–(19). Substituting the values of c11 (x) and c12 (x) in
(14), we obtain the expression for φ1 (x, y). Then, substituting
φ1 (x, y) in (13) and putting y = 0, we obtain
d2 φs (x)
− αφs (x) = β
dx2
(22)
where
2 1 + 2CCf + CCSif
SiGe
α=
2
Si
ts−Si 1 + CCSiGe
Cf
Cf
2V
+
GS 2CSiGe
CSi
qNA
2V
−
sub
−
β=
C
εSi
Si
Si
t2s−Si 1 + CSiGe
t2s−Si 1 + CCSiGe
(15)
(23)
where tSiGe = xd − ts−Si , φS (x) is the surface potential and
the coefficients c11 (x), c12 (x), c21 (x), and c22 (x) are functions
of x only.
The Poisson equation is solved using the following boundary
conditions.
where Cf = εox /tf , CSi = εSi /ts−Si , CSiGe = εSiGe /tSiGe .
The above equation is a simple second-order nonhomogenous differential equation with constant coefficients which has
a solution of the form
1) Electric flux (displacement) at the gate-oxide/strained-Si
film interface is continuous.
dφ1 (x, y)
εox φs (x) − VGS
=
(16)
dy
εSi
tf
y=0
where εox is the dielectric constant of the gate oxide, tf is
= VGS − (VFB,f )s−Si , and
the gate oxide thickness,VGS
VGS is the gate-to-source bias voltage.
(24)
φs (x) = A exp(λx) + B exp(−λx) − σ
√
where λ = α and σ = β/α. Now, using boundary conditions
(20), (21) to solve for A and B, we obtain (25) and (26), found
at the bottom of the next page.
The minimum surface potential can be calculated from (24)
by putting
dφs (x)
= 0.
dx
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IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 7, NO. 1, MARCH 2007
TABLE I
DEVICE PARAMETERS USED IN THE SIMULATION
The minimum surface potential is
√
φs,min = 2 AB − σ.
(28)
The threshold voltage Vth is that value of the gate voltage
VGS at which a conducting channel is induced under the gate
oxide at the surface of a MOSFET. In a conventional unstrained
silicon MOSFET, the threshold voltage is taken to be that value
of gate-source voltage for which φS,min = 2φF,Si , where φF,Si
is the difference between the extrinsic Fermi level in the bulk
region and the intrinsic Fermi level [20]. For the strained-Si
MOSFETs, the condition for threshold is modified as [11]
φs,min = 2φF,Si + ∆φs−Si = φth
where
∆φs−Si
−(∆Eg )s−Si
+ VT ln
=
q
NV,Si
NV,s−Si
(29)
.
(30)
In (29), φth is that value of surface potential at which the
inversion electron charge density in the strained-Si device is
the same as that in unstrained-Si at threshold [11]. Therefore,
the threshold voltage is defined as the value of VGS at which the
minimum surface potential φS,min equals φth . Hence, we can
determine the value of threshold voltage by substituting (28)
into (29) and solving for VGS , as


2 − 4ξV
−Vφ1 + Vφ1
φ2

(31)
Vth = k 
2ξ
where
ξ = 2 cosh(λL) − 2 − sinh2 (λL)
(32)
Vφ1 = Vbi1 (1 − exp(λL)) + (2φth − 2u) sinh (λL)
− Vbi2 (1 − exp(−λL))
(33)
2
Vφ2 = Vbi1 Vbi2 − (φth − u)2 sinh2 (λL)
Vbi1 = (Vsub + Vbi,s−Si − u) (1 − exp(−λL)) + VDS
Vbi2 = (Vsub + Vbi,s−Si − u) (exp(λL) − 1) − VDS
Vsub
qNA
−
u=
εSi α
1 + 2CCf + CCSif
SiGe
Cf
Cf
2CSiGe + CSi −
(VFB,f )s−Si
1 + 2CCf + CCSif
SiGe
Cf
1 + CSi + 2CCf
SiGe
.
k= Cf
Cf
+
CSi
2C
SiGe
A=
B=
(34)
(35)
(36)
(37)
(38)
Fig. 3. Threshold voltage versus strain x (Ge content in SiGe substrate)
for channel lengths (L) of 50 and 30 nm. The parameters used are: VDS =
50 mV, Vsub = 0 V, NA = 1 × 1018 cm−3 , ts−Si = 15 nm, rj = 50 nm,
tf = 2 nm, φM = 4.35 eV.
IV. R ESULTS AND D ISCUSSION
To verify the proposed analytical model, the 2-D device simulator MEDICI [14] was used to simulate the threshold voltage
of strained-Si/SiGe MOSFETs for various device parameters
and compared with the values predicted by the model. The
threshold voltage is extracted from MEDICI simulations as the
gate voltage at which the surface inversion electron volume
concentration becomes equal to the body (channel) doping,
consistent with the model formulation. The parameters used in
our simulation are given in Table I.
Fig. 3 shows the variation of threshold voltage with change in
strain, i.e., Ge mole fraction of SiGe substrate, for gate lengths
of 50 and 30 nm. The threshold voltage obtained from the
model tracks the simulation values very well. It is evident that
there is a significant fall in threshold voltage with increasing
strain, and the decrease in Vth is almost linear. Vth rolls off
drastically with strain x, even going negative for Ge content of
(Vsub + Vbi,s−Si + σ + VDS ) − (Vsub + Vbi,s−Si + σ) exp(−λL)
1 − exp(−2λL)
(Vsub + Vbi,s−Si + σ) − (Vsub + Vbi,s−Si + σ + VDS ) exp(−λL)
1 − exp(−2λL)
exp(−λL)
(25)
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KUMAR et al.: IMPACT OF STRAIN OR Ge CONTENT ON THE THRESHOLD VOLTAGE
Fig. 4. Threshold voltage versus channel length L. The parameters used are:
VDS = 50 mV, Vsub = 0 V, NA = 1 × 1018 cm−3 , ts−Si = 15 nm, rj =
50 nm, tf = 2 nm, φM = 4.35 eV.
30%–40%. The threshold voltage decreases with increasing Ge
content x because of decrease in flatband voltage (3), decrease
in source-body/drain-body built-in potential barrier (4), and
earlier onset of inversion due to decrease in φth (29). Also, it
can be seen from the figure that Vth for L = 50 nm is noticeably
greater than that for L = 30 nm, indicating the on-set of the
short-channel effects.
Fig. 4 shows the variation of threshold voltage with gate
length for different values of Ge mole fraction x in the SiGe
substrate. It is observed that short-channel effects become
prevalent below 70–80-nm gate length, as predicted above, and
is marked by the sharp decrease in Vth value. The gate-S/D
charge sharing and source-body/drain-body built-in potential
barrier lowering due to overlap of the lateral source-body and
drain-body depletion regions (xdl in Fig. 1) become significant
for such short-channel lengths. Also, the threshold voltage is
lower for higher strain for the same channel length, thus confirming the results from Fig. 3. The Vth values from the analytical model are in close proximity with the simulation results.
In Fig. 5, the variation of threshold voltage with change in
strain (Ge mole fraction x in SiGe substrate) for a gate length of
50 nm is plotted for two different body doping concentrations
and corresponding gate work functions. It is evident from
the figure that the threshold voltage of the strained-Si/SiGe
MOSFETs can be controlled by using an appropriate gate
material with a suitable work function φM . A higher work
function (e.g., Mid-gap metal with φM = 4.71 eV) increases
the flatband voltage (3) thereby affording a lower doping
concentration and higher strain levels for the same Vth , as
compared to a normal n+ polysilicon gate (φM = 4.35 eV).
Thus, by using a suitable gate material, we can achieve
higher mobility of charge carriers due to larger strain and
consequently higher transconductance without affecting Vth .
There is again a close match between the analytical results and
the 2-D simulation results [14].
In Fig. 6, the variation of threshold voltage with change in
strain (Ge mole fraction x in SiGe substrate) for a gate length
of 50 nm is plotted for two different S/D junction depths. It
is observed that Vth also reduces slightly with increase in S/D
185
Fig. 5. Threshold voltage versus strain x (Ge content in SiGe substrate)
for body dopings NA = 1 × 1018 cm−3 and NA = 1 × 1017 cm−3 , and
corresponding gate work functions φM = 4.35 eV (n+ poly) and φM =
4.71 eV (Mid-gap metal), respectively. The parameters used are: VDS =
50 mV, Vsub = 0 V, L = 50 nm, ts−Si = 15 nm, rj = 50 nm, tf = 2 nm.
Fig. 6. Threshold voltage versus strain x (Ge content in SiGe substrate) for
S/D junction depths rj = 50 nm and rj = 80 nm. The parameters used are:
VDS = 50 mV, Vsub = 0 V, L = 50 nm, NA = 1 × 1018 cm−3 , ts−Si =
15 nm, tf = 2 nm, φM = 4.35 eV.
junction depth, for the same gate length. This is because of the
increase in average vertical depletion region depth (11) and
(12), and lower effective doping (10) due increased gate-S/D
sharing and overlap of the lateral source-body and drain-body
depletion regions. Thus, a lower S/D junction depth is desirable
for better performance.
The variation of threshold with the thickness of the strainedSi thin film is plotted in Fig. 7. As can be seen from the figure,
there is no discernible change in threshold voltage with change
in strained-Si film thickness from 10–15 nm. This suggests that
one can allow small variations and tolerances in the fabrication
process without affecting the Vth too much.
V. C ONCLUSION
For the first time, we have examined the impact of various device parameters like strain (Ge mole fraction in SiGe
substrate), gate length, S/D junction depths, substrate (body)
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IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 7, NO. 1, MARCH 2007
Fig. 7. Threshold voltage versus strained-Si film thickness ts−Si . The parameters used are: VDS = 50 mV, Vsub = 0 V, NA = 1 × 1018 cm−3 , L =
50 nm, rj = 50 nm, tf = 2 nm, φM = 4.35 eV.
doping, strained silicon thin-film thickness, and gate work
function on the threshold voltage of nanoscale strained-Si/SiGe
MOSFETs by developing an analytical model for the same.
The 2-D Poisson equation is solved in the strained-Si thin film
using appropriate boundary conditions. The model results are
compared with accurate 2-D simulations [14]. The calculated
values of the threshold voltage obtained from the proposed
model agree well with the simulated results. There is a significant drop in threshold voltage with increasing Ge content of
relaxed Si1−x Gex substrate and decreasing channel length. The
increase in strain, i.e., Ge content, enhances the performance
of MOSFETs in terms of transconductance and speed because
of an increase in the carrier mobility [1]–[5]. However, as
demonstrated by our results, there are undesirable side effects
with increasing Ge content such as a roll-off in Vth which may
affect the device characteristics and performance significantly.
Our compact model accurately predicts the threshold voltage
over a large range of device parameters and can be effectively
used to design and characterize nanoscale strained Si/SiGe
MOSFETs with the desired performance [21]. The model can
be easily implemented in a circuit simulator also.
A PPENDIX
The average vertical depletion region depth (xd in Fig. 2) in
(11) and (12) is calculated using the constraint that the total
depletion region area under the gate should remain the same as
before after transformation to the box approximation.
For L ≥ 2xdl , the total depletion region area (DA) under the
gate is calculated from Fig. 8(a) as DA = (Area of Region 1) +
(Area of Region 2) + (Area of Region 3). Thus
π π DA ∼
= rj xdl + x2dl + (L − 2xdl )xdν + rj xdl + x2dl .
4
4
(A1)
In the box approximation of Fig. 2, the total DA under the
gate is
DA = xd L.
(A2)
Fig. 8. Depletion region of the strained-Si/SiGe MOSFET for (a) L ≥ 2xdl
and (b) L ≤ 2xdl .
Equating (A1) and (A2), we get the expression for average
vertical depletion region depth xd as
2xdl rj + 4π xdl + (L − 2xdl )xdν
xd ∼
=
L
for L ≥ 2xdl .
(A3)
Equation (A3) is the same as (11).
Similarly, for L ≤ 2xdl , the total DA under the gate
is calculated from Fig. 8(b) as DA = (Area of Region 1) +
(Area of Region 2) = 2∗ (Area of Region 1or 2). Thus, DA can
be approximated as
L
DA ∼
=2
2
rj +
θ
L2
+ xdl
x2dl −
4
2
where θ = sin−1 (L/2xdl ).
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(A4)
KUMAR et al.: IMPACT OF STRAIN OR Ge CONTENT ON THE THRESHOLD VOLTAGE
Again, in the box approximation of Fig. 2, the total DA under
the gate is given by (A2). Equating (A4) and (A2), we get the
expression for average vertical depletion region depth xd as
xd ∼
= rj +
x2dl −
θ
L2
+ xdl
4
2
for L ≤ 2xdl .
187
[20] K. K. Young, “Short-channel effect in fully depleted SOI MOSFETs,”
IEEE Trans. Electron Devices, vol. 36, no. 2, pp. 399–402, Feb. 1989.
[21] M. J. Kumar, V. Venkataraman, and S. Nawal, “A simple analytical
threshold voltage model of nanoscale fully depleted single-layer strainedsilicon-on-insulator (SSOI) MOSFETs,” IEEE Trans. Electron Devices,
vol. 53, no. 10, pp. 2500–2506, Oct. 2006.
(A5)
Equation (A5) is the same as (12).
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M. Jagadesh Kumar (M’95–SM’99) was born in
Mamidala, Nalgonda District, Andhra Pradesh, India. He received the M.S. and Ph.D. degrees in
electrical engineering from Indian Institute of Technology (IIT), Madras, India.
From 1991 to 1994, he performed postdoctoral
research in modeling and processing of high-speed
bipolar transistors with the Department of Electrical
and Computer Engineering, University of Waterloo,
Waterloo, ON, Canada. While with the University of
Waterloo, he also did research on amorphous silicon
thin-film transistors. From July 1994 to December 1995, he was initially with
the Department of Electronics and Electrical Communication Engineering, IIT,
Kharagpur, India, and then joined the Department of Electrical Engineering,
IIT, Delhi, India, where he became an Associate Professor in July 1997 and
a Full Professor in January 2005. His research interests are in very large
scale integration (VLSI) device modeling and simulation for nanoscale applications, integrated-circuit technology, and power semiconductor devices. He
has published extensively in the above areas with more than 115 publications
in refereed journals and conferences. His teaching has often been rated as
outstanding by the Faculty Appraisal Committee, IIT Delhi.
Dr. Kumar is a Fellow of Institution of Electronics and Telecommunication Engineers (IETE), India. He is a recipient of the 29th IETE Ram Lal
Wadhwa Gold Medal for distinguished contribution in the field of semiconductor device design and modeling. He is an Editor of IEEE TRANSACTIONS ON
ELECTRON DEVICES. He is also on the editorial board of 1) Recent Patents on
Nanotechnology, 2) Journal of Nanoscience and Nanotechnology, and 3) IETE
Journal of Research as a subject area Honorary Editor for Electronic Devices
and Components. He has reviewed extensively for different journals including
IEEE TRANSACTIONS ON ELECTRON DEVICES, IEEE TRANSACTIONS ON
DEVICE AND MATERIALS RELIABILITY, IEE Proceedings on Circuits, Devices, and Systems, Electronics Letters, and Solid-state Electronics. He was
Chairman, Fellowship Committee, The Sixteenth International Conference on
VLSI Design, January 4–8, 2003, New Delhi, India. He was also Chairman of
the Technical Committee for High Frequency Devices, International Workshop
on the Physics of Semiconductor Devices, December 13–17, 2005, New Delhi.
Vivek Venkataraman (S’05) received the B.Tech
degree in electrical engineering from Indian Institute
of Technology (IIT), Delhi, New Delhi, India. He is
currently working toward the Ph.D. degree in electrical and computer engineering at Cornell University,
Ithaca, NY.
His current research interests include device
physics, optoelectronics, and nanoelectronics.
Susheel Nawal received the B.Tech degree in electrical engineering from Indian Institute of Technology
(IIT), Delhi, New Delhi, India.
His research interests include modeling and simulation for nanoscale applications.
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