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ST7LITE3XF2 中文资料
ST7LITE3xF2
8-bit MCU with single voltage Flash, data EEPROM, ADC, timers,
SPI, LINSCI?
Features
■
■
■
■
Memories
–8 Kbytes program memory: single voltage ex-tended Flash (XFlash) Program memory
withread-out protection, In-Circuit Programmingand In-Application programming (ICP
andIAP), data retention: 20 years at 55°C.–384 bytes RAM
– 256 bytes data EEPROM with read-out pro-tection. 300K write/erase cycles
guaranteed,data retention: 20 years at 55°C.
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Clock, Reset and Supply Management–Enhanced reset system
–Enhanced low voltage supervisor (LVD) formain supply and an auxiliary voltage
detector(AVD) with interrupt capability for implement-ing safe power-down procedures
–Clock sources: Internal RC 1% oscillator,crystal/ceramic resonator or external
clock –Optional x4 or x8 PLL for 4 or 8MHz internalclock
–
Five
Power
Saving
Modes:
Halt,
Active-Halt,Wait
and
Slow,
Authttp://www.wendangwang.com/doc/2c8a46421bc4f43b8223483ao Wake Up From HaltI/O
Ports
–Up to 15 multifunctional bidirectional I/O lines–7 high sink outputs5 Timers
–Configurable Watchdog Timer
–Two 8-bit Lite Timers with prescaler, 1 realtime base and 1 input capture
– Two 12-bit Auto-reload Timers with 4 PWMoutputs, input capture and output
comparefunctions
–Master/slave LINSCI? asynchronous serialinterface
–SPI synchronous serial interface■Interrupt Management
– 10 interrupt vectors plus TRAP and RESET–12 external interrupt lines (on 4
vectors)■A/D Converter–7 input channels –10-bit resolution ■Instruction Set
8-bit data manipulation
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–63 basic instructions with illegal opcode detection
–17 main addressing modes
–8 x 8 unsigned multiply instructions■Development Tools
–Full hardware/software development package–DM (Debug module)
■
Table 1. Device summary
Fehttp://www.wendangwang.com/doc/2c8a46421bc4f43b8223483aatures
Program memory - bytesRAM (stack) - bytesData EEPROM - bytesPeripherals
CPU FrequencyST7LITE30F2
ST7LITE35F2
ST7LITE39F2
8K384 (128)
--256
Lite Timer, Autoreload Timer, SPI, LINSCI, 10-bit ADC
(w/ ext OSC up to 16MHz)and int 1MHz RC 1% PLLx8/4MHz)
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Rev. 9
November 2007
1/173
ST7LITE3xF2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
1
INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 PIN
DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . 63 REGISTER & MEMORY
MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
94
FLASH
MEMORY
PROGRAM
. . . . . . . . . . .http://www.wendangwang.com/doc/2c8a46421bc4f43b8223
483a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
124.1INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . 124.24.34.44.54.64.7
MAIN
FEATURES
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12PROGRAMMING
MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12ICC
INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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PROTECTION
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13MEMORY
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14RELATED
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DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14REGISTER
DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . .http://www.wendangwang.com/doc/2c8a46421bc4f43b8223483a . 14
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DATA
EEPROM
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155.1INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . 155.25.35.45.55.65.7
MAIN
FEATURES
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15MEMORY
ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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MODES
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16POWER
SAVING
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18ACCESS
ERROR
HANDLING
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18DATA
PROTECTION
EEPROM
READ-OUT
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DESCRIPTION . . . . . . . . . . . . . . . . . . .http://www.wendangwang.com/doc/
2c8a46421bc4f43b8223483a . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6
CENTRAL
PROCESSING
UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
206.1INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . 206.26.3
MAIN
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FEATURES
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20CPU
REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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7
SUPPLY,
RESET
AND
CLOCK
MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
237.1INTERNAL
ADJUSTMENT
RC
OSCILLATOR
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PHASE
LOCKED
LOOP
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23REGISTER
DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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24MULTI-OSCILLATOR
(MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
26RESET
SEQUENCE
MANAGER
(RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27SYSTEM
INTEGRITY MANAGEMENT (SI)
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30
8
INTERRUPTS
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. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358.1NON MASKABLE SOFTWARE
INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358.28.3
EXTERNAL
INTERRUPTS
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INTERRUPTS
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35PERIPHERAL
.......................................
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http://www.wendangwang.com/doc/2c8a46421bc4f43b8223483a. . . . . . 35
9
POWER
MODES
SAVING
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399.1INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . 399.29.39.4
SLOW
MODE
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MODE
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39WAIT
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MODE
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40HALT
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9.59.6
ACTIVE-HALT
MODE
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MODE
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42AUTO
WAKE
UP
FROM
HALT
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43://www.wendangwang.com/doc/2c8a46421bc4f43b8223483a
10
I/O
PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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4710.1INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . 4710.2FUNCTIONAL
DESCRIPTION
4710.3I/O
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PORT
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IMPLEMENTATION
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PINS
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5010.4UNUSED
I/O
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5010.5LOW
POWER
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5010.6INTERRUPTS
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. . . . . . . . . . . . . . . . . . . . . . . . . . 5011 ON-CHIP
PERIPHERALS . . . . . . . . . . .http://www.wendangwang.com/doc/2c8a46421bc4f43b
8223483a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5211.1WATCHDOG
TIMER
(WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5211.2DUAL
12-BIT
AUTORELOAD
TIMER
3
(AT3)
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TIMER
2
(LT2)
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. . . . . . . . . . . . . . . 7311.4SERIAL PERIPHERAL INTERFACE
(SPI)
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SERIAL COMMUNICATION INTERFACE (LIN MASTER/SLAVE)
A/D CONVERTER (ADC)
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12112
SET
INSTRUCTION
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12512.1ST7
ADDRESSING
MODES . . . . . . . . . . . . . . .http://www.wendangwang.com/doc/2c8a46421bc4f4
3b8223483a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12512.2INSTRUCTION
GROUPS
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12813
ELECTRICAL
CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13113.1PARAMETER
CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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13113.2ABSOLUTE
RATINGS
MAXIMUM
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13213.3OPERATING
CONDITIONS
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13313.4SUPPLY
CURRENT
CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14013.5CLOCK
AND
TIMING
CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14313.6MEMORY
CHARACTERISTICS
. . . . . . . . . . . . . . . . . . . . . . . . .http://www.wen
dangwang.com/doc/2c8a46421bc4f43b8223483a . . . . . . . . . . . . . . . . . 14513.7EMC
(ELECTROMAGNETIC COMPATIBILITY) CHARACTERISTICS
. . . . . . . . . . . . 14613.8I/O
PORT
PIN
CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14813.9CONTROL
PIN
CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15313.10COMMUNICATION
INTERFACE
CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 15513.1110-BIT ADC
CHARACTERISTICS
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15714
PACKAGE
CHARACTERISTICS
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15914.1PACKAGE
MECHANICAL
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15914.2THERMAL CHARACTERISTICS
160
15 DEVICE CONFIGURATION
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http://www.wendangwang.com/doc/2c8a46421bc4f43b8223483a. . . . . . . . . . . . .
16115.1FLASH
OPTION
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BYTES
................................................
16115.2DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE . . . .
16315.3DEVELOPMENT
TOOLS
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16515.4ST7
APPLICATION
NOTES
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16616
KNOWN
LIMITATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . 16916.1CLEARING ACTIVE INTERRUPTS OUTSIDE
INTERRUPT ROUTINE . . . . . . . . . . . . 169
16.2LINSCI
LIMITATION
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16917
REVISION
HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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http://www.wendangwang.com/doc/2c8a46421bc4f43b8223483a. . . 171
To obtain the most recent version of this datasheet,please check at www.st.com
Please also pay special attention to the Section “KNOWN LIMITATIONS” on page169.
ST7LITE3xF2
1 INTRODUCTION
The ST7LITE3 is a member of the ST7 microcon-troller family. All ST7 devices are based
on a com-mon industry-standard 8-bit core, featuring an en-hanced instruction set.
The
ST7LITE3 features FLASH memory withbyte-by-byte In-Circuit Programming (ICP)
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and In-Application Programming (IAP) capability.
Under software control, the ST7LITE3 device canbe placed in WAIT, SLOW, or HALT mode,
reduc-ing power consumption when the application is inidle or standby state.
The enhanced instruction set and addressingmodes of the ST7 offer both power and
flexibility tosoftware developers, enabling the design of highlyefficient and
compact
application
code.
In
additionto
standard
8-bihttp://www.wendangwang.com/doc/2c8a46421bc4f43b8223483at data management, all
ST7 micro-controllers feature true bit manipulation, 8x8 un-signed multiplication
and indirect addressingmodes.
For easy reference, all parametric data are locatedin section 13 on page 131.
The devices feature an on-chip Debug Module(DM) to support in-circuit debugging (ICD).
For adescription of the DM registers, refer to the ST7ICC Protocol Reference Manual.
ST7LITE3xF2
2 PIN DESCRIPTION
Figure 2. 20-Pin QFN Package Pinout
OSC1/CLKIN
201918
OSC2
17
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16VDD
VSS
SCK/AIN1/PB1MISO/AIN2/PB2MOSI/AIN3/PB3CLKIN/AIN4/PB4
123456
7
8
9
10
ei2ei2
ei1
ei3
ei0
PA0 (HS)/LTICPA1 (HS)/ATICPA2 (HS)/ATPWM0PA3 (HS)/ATPWM1PA4 (HS)/ATPWM2
PA5 (HS)/ATPWM3/ICCDATA
14131211
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TDO/PA7(HS)
MCO/ICCCLKBREAK/PA6http://www.wendangwang.com/doc/2c8a46421bc4f43b8223483a
RDI/AIN6/PB6
AIN5/PB5
(HS)20mA Highsinkcapability
eixassociatedexternalinterruptvector
VSSVDDSCK/AIN1/PB1MISO/AIN2/PB2MOSI/AIN3/PB3CLKIN/AIN4/PB4AIN5/PB5RDI/AIN6/PB6
OSC1/CLKINOSC2
PA0 (HS)/LTICPA1 (HS)/ATICPA2 (HS)/ATPWM0PA3 (HS)/ATPWM1PA4 (HS)/ATPWM2
PA5 (HS)/ATPWM3/ICCDATAPA6/MCO/ICCCLK/BREAKPA7 (HS)/TDO
(HS)20mAhighsinkcapability
eixassociatedexternalinterruptvector
12345678910
ei2ei2
ei1
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ei3
ei0
201918171615131211
ST7LITE3xF2
PIN DESCRIPTION (Cont’d)
Legend / Abbreviations for Table 2:Type: I = input, O = output, S = supply
In/Output level:CT= CMOS 0.3VDD/0.7VDD with input triggerOutput level: HS = 20mA high
sink (on N-buffer only)
Port and control configuration:– Input:float = floating, wpu = weak pull-up, int
=
interrupt,
ana
=
analog–
Ouhttp://www.wendangwang.com/doc/2c8a46421bc4f43b8223483atput: OD = open drain, PP
= push-pull
The RESET configuration of each pin is shown in bold which is valid as long as the
device is in reset state.Table 2. Device Pin Description
Level
SO20/DIP20
Type
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QFN20
Input
Pin Name
Output
Port / ControlInputfloat
wpu
anaint
Main
OutputFunction
(after reset)OD
PP
Alternate Function
19201
123
VSS 1)VDD 1)
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S
X
X
Main power supply
Top priority non maskable interrupt (active low)ADC Analog Input 0 or SPI Slave Select
(active low)
Port B0 Caution: No negative current injection
allowed on this pin. For details, refer to section 13.2.2 on page 132
ADC Analog Input 1 or SPI Serial ClockCaution: No negative current injection
Port B1
allowed on thhttp://www.wendangwang.com/doc/2c8a46421bc4f43b8223483ais pin. For
details, refer to section 13.2.2 on page 132
ADC Analog Input 2 or SPI Master In/
Port B2
Slave Out Data
ADC Analog Input 3 or SPI Master Out
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Port B3
/ Slave In Data
ADC Analog Input 4 or External clock
Port B4
inputPort B5Port B6Port A7
ADC Analog Input 5
ADC Analog Input 6 or LINSCI InputLINSCI Output
CT
24T
X
ei3
XXX
35
PB1/AIN1/SCKTPB2/AIN2/MISO
PB3/AIN3/MOSI
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PB4/AIN4/CLKIN**PB5/AIN5
XXXX
456789
6789
TTTTTTHS
XXXXXX
XXei2ei2
XXXXX
XXXXXX
XXXXXX
10PB6/AIN6/RDI11PA7/TDO
ST7LITE3xF2
Level
SO20/DIP20
Type
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Output
QFN20
Input
Pin Name
Port / ControlInputfloat
wpu
://www.wendangwang.com/doc/2c8a46421bc4f43b8223483aaranaint
Main
OutputFunction
(after reset)OD
PP
Alternate Function
Main Clock Output or In Circuit Com-munication Clock or External BREAK
PA6 /MCO/
1012ICCCLK/
BREAK
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Caution: During normal operation this pin must be pulled- up, internally or
ex-ternally (external pull-up of 10k manda-tory in noisy environment). This is to
avoid entering ICC mode unexpectedly during a reset. In the application, even if the
pin is configured as output, any re-set will put it back in input pull-up.
Auto-Reload
Timer
PWM3
or
In
Circuit
Communication
DataAuto-Reload
Timer
PWM2Auto-Reload Timer PWM1Auto-Reload Timer PWM0Auto-Reload Timer Input CaptureLite
Timer Input Capture
T
X
ei1
XXPort A6
1113
PA5 /ATPWM3/
THS
ICCDATA
THSTHSTHSTHSTHSOI
XXXXXX
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Xei0
://www.wendangwang.com/doc/2c8a46421bc4f43b8223483arXXXXXX
XXXXXX
Port A5Port A4Port A3Port A2Port A1Port A0
1214PA4/ATPWM21315PA3/ATPWM11416PA2/ATPWM01517PA1/ATIC1618PA0/LTIC1719OSC21820OS
C1/CLKIN
Resonator oscillator inverter output
Resonator oscillator inverter input or External clock input
Notes:
1. It is mandatory to connect all available VDD and VDDA pins to the supply voltage
and all VSS and VSSApins to ground.
2. For input with interrupt possibility “eix” defines the associated external
interrupt vector which can be as-signed to one of the I/O pins using the EISR register.
Each interrupt can be either weak pull-up or floatingdefined through option register
OR.
ST7LITE3xF2
3 REGISTER & MEMORY MAP
As shown in Figure 4, the MCU is capable of ad-dressing 64K bytes of memories and
I/O registers.The available memory locations consist of 128bytes of register
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locations, 384 bytes ofhttp://www.wendangwang.com/doc/2c8a46421bc4f43b8223483a RAM,
256bytes of data EEPROM and 8 Kbytes of user pro-gram memory. The RAM space includes
up to 128bytes for the stack from 180h to 1FFh.
The highest address bytes contain the user resetand interrupt vectors.Figure 4.
Memory Map
0080h
The Flash memory contains two sectors (see Fig-ure 4) mapped in the upper part of
the ST7 ad-dressing space so the reset and interrupt vectorsare located in Sector
0 (F000h-FFFFh).
The size of Flash Sector 0 and other device op-tions are configurable by Option byte.
IMPORTANT: Memory locations marked as “Re-served” must never be accessed. Accessing
a re-seved area can have unpredictable effects on thedevice.
0000h007Fh0080h01FFh0200h0FFFh1000h10FFh1100h
HW Registers(see Table 3)RAM(384 Bytes)ReservedData EEPROM(256 Bytes)
00FFh0100h
Short AddressingRAM (zero page)16-bit Addressing
RAM
017Fh0180h
://www.wendangwang.com/doc/2c8a46421bc4f43b8223483a128BytesStack
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01FFh
DEE0hDEE1hDEE2hDEE3h
RCCRH0RCCRL0 RCCRH1RCCRL1
Reserved
DFFFhE000h
8KFLASH
PROGRAMMEMORY
DEE4h
see section 7.1 on page 23and Note 1)
E000h
Flash Memory
(8K)
FFDFhFFE0hFFFFh
FBFFhFFFFh
7 KbytesSECTOR11 KbyteSECTOR0
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Interrupt & Reset Vectors
(see Table 6)
1. DEE0h, DEE1h, DEE2h and DEE3h addresses are located in a reserved area but are
special bytescontaining also the RC calibration values which are read-accessible only
in user mode. If all the EEPROMdata or Flash space (including the RC calibration values
locations) has been erased (after the read outprotection removal), then the RC
calibration values can still be obtained through these addresses.
ST7LITE3xF2
Table 3. Hardware Register Map
Address0000h0001h0002h000http://www.wendangwang.com/doc/2c8a46421bc4f43b8223483a
3h0004h0005h0006h0007h0008h0009h000Ah000Bh000Ch000Dh000Eh000Fh0010h0011h0012h001
3h0014h0015h0016h0017h0018h0019h001Ah001Bh001Ch001Dh001Eh001Fh0020h0021h0022h002
3h0024h0025h0026h to002Dh002Eh0002Fh00030h
WDGFLASHEEPROM
WDGCRFCSREECSRLTCSR2LTARRLTCNTRLTCSR1LTICRATCSRCNTR1HCNTR1LATR1HATR1LPWMCRPWM0CS
RPWM1CSRPWM2CSRPWM3CSRDCR0HDCR0LDCR1HDCR1LDCR2HDCR2LDCR3HDCR3LATICRHATICRLATCSR2
BREAKCRATR2HATR2LDTGR
Block
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Register LabelPADRPADDRPAORPBDRPBDDRPBOR
Register Name
Port A Data Register
Port A Data Direction RegisterPort A Option RegisterPort B Data Register
Port B Data Direction RegisterPort B Option Register
Reserved area (2 bytes)
Lite Timer Control/Status Register 2Lite Timer Auto-reload RegisterLite Timer
Counter Register
Lite Timer Control/Status Register 1Lite Timer Input Capture RegisterTimer
Control/Status
RegisterCounter
Register
1
Hihttp://www.wendangwang.com/doc/2c8a46421bc4f43b8223483aghCounter Register 1 Low
Auto-Reload Register 1 HighAuto-Reload Register 1 LowPWM Output Control RegisterPWM
0 Control/Status RegisterPWM 1 Control/Status RegisterPWM 2 Control/Status
RegisterPWM 3 Control/Status RegisterPWM 0 Duty Cycle Register HighPWM 0 Duty Cycle
Register LowPWM 1 Duty Cycle Register HighPWM 1 Duty Cycle Register LowPWM 2 Duty
Cycle Register HighPWM 2 Duty Cycle Register LowPWM 3 Duty Cycle Register HighPWM
3 Duty Cycle Register LowInput Capture Register HighInput Capture Register LowTimer
Control/Status Register 2Break Control Register
Auto-Reload Register 2 HighAuto-Reload Register 2 LowDead Time Generator Register
Reserved area (8 bytes)
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Watchdog Control RegisterFlash Control/Status Register
Data EEPROM Control/Status Register
7Fh00h00h
R/WR/WR/W
0Fh00h00h0x00 00x0b
xxh0x00 0000b
00h00h00h00h00h00h00h00h00h00h00h00h00h0http://www.wendangwang.com/doc/2c8a46421
bc4f43b8223483a0h00h00h00h00h00h03h00h00h00h00h
R/WR/W
Read Only R/W
Read Only R/W
Read OnlyRead OnlyR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/W
Read OnlyRead OnlyR/WR/WR/WR/WR/W
Reset Status
FFh1)00h40hFFh 1)00h00h
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RemarksR/WR/WR/WR/WR/WR/W2)
Port A
Port B
LITETIMER 2
AUTO-RELOADTIMER 3
ST7LITE3xF2
Address0031h0032h0033h0034h0035h0036h0037h0038h0039h003Ah003Bh
003Fh
003Ch003Dh
to
0040h0041h0042h0043h0044h0045h0046h0047h
0048h0049h004Ah004Bh004Ch004Dh004Eh004Fh0050h0051h to007Fh
Block
Register LabelSPIDRSPICRSPICSRADCCSRADCDRHADCDRLEICRMCCSR
Register Name
SPI Data I/O RegisterSPI Control Register
SPI Control Status RegisterA/D Control Status RegisterA/D Data Register High
A/D control and Data Register LowExternal Interrupt Control RegisterMain Clock
Control/Status Reghttp://www.wendangwang.com/doc/2c8a46421bc4f43b8223483aisterRC
oscillator Control Register
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System Integrity Control/Status Register
Reserved area (1 byte)
Reset Status
xxh0xh00h00hxxhx0h00h00hFFh0110 0xx0b
RemarksR/W R/W R/WR/W
Read OnlyR/WR/WR/WR/WR/W
SPI
ADCITCMCC
Clock and RCCRResetSICSR
ITCEISRExternal Interrupt Selection Register
Reserved area (3 bytes)
00hR/W
LINSCI(LIN Mas-ter/Slave)
SCISR
SCIDRSCIBRRSCICR1SCICR2SCICR3SCIERPRSCIETPRSCI Status RegisterSCI Data Register
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SCI Baud Rate RegisterSCI Control Register 1SCI Control Register 2SCI Control
Register 3
SCI Extended Receive Prescaler RegisterSCI Extended Transmit Prescaler Register
Reserved area (1 byte)
C0hxxh00xx xxxxb
xxh00h00h00h00hRead Only R/W R/W R/W R/W R/W R/WR/W
AWU
AWUPRAWUCSRDMCRDMSRDMBK1HDMBK1LDMBK2HDMBK2L
AWU http://www.wendangwang.com/doc/2c8a46421bc4f43b8223483aPrescaler Register
AWU Control/Status RegisterDM Control RegisterDM Status Register
DM Breakpoint Register 1 HighDM Breakpoint Register 1 LowDM Breakpoint Register 2
HighDM Breakpoint Register 2 Low
Reserved area (47 bytes)
FFh00h00h00h00h00h00h00h
R/WR/WR/WR/WR/WR/WR/WR/W
DM3)
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Legend: x=undefined, R/W=read/writeNotes:
1. The contents of the I/O port DR registers are readable only in output configuration.
In input configura-tion, the values of the I/O pins are returned instead of the DR
register contents.2. The bits associated with unavailable pins must always keep their
reset value.3. For a description of the DM registers, see the ST7 ICC Reference Manual.
ST7LITE3xF2
4 FLASH PROGRAM MEMORY
4.1 Introduction
The ST7 single voltage extended Flash (XFlash) isa non-volatile memory that can be
electricallyerased
and
eihttp://www.wendangwang.com/doc/2c8a46421bc4f43b8223483ather
programmed
on
a
byte-by-bytebasis or up to 32 bytes in parallel.
The XFlash devices can be programmed off-board(plugged in a programming tool) or
on-board usingIn-Circuit Programming or In-Application Program-ming.
The array matrix organisation allows each sectorto be erased and reprogrammed without
affectingother sectors.4.2 Main Features
■■■
■■
ICP (In-Circuit Programming)
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IAP (In-Application Programming)
ICT (In-Circuit Testing) for downloading andexecuting user application test patterns
in RAMSector 0 size configurable by option byteRead-out and write protection
4.3 PROGRAMMING MODES
The ST7 can be programmed in three differentways:
–Insertion in a programming tool. In this mode,FLASH sectors 0 and 1, option byte
row anddata EEPROM (if present) can be pro-grammed or erased.
–
In-Circuit
Programming.
In
this
mode,
FLASHsectors
ophttp://www.wendangwang.com/doc/2c8a46421bc4f43b8223483ation
0
byte
and
row
1,
and
dataEEPROM (if present) can be programmed orerased without removing the device from
theapplication board.
–In-Application Programming. In this mode,sector 1 and data EEPROM (if present)
canbe programmed or erased without removing
the device from the application board andwhile the application is running.4.3.1
In-Circuit Programming (ICP)
ICP uses a protocol called ICC (In-Circuit Commu-nication) which allows an ST7 plugged
on a print-ed circuit board (PCB) to communicate with an ex-ternal programming device
connected via cable.ICP is performed in three steps:
Switch the ST7 to ICC mode (In-Circuit Communi-cations). This is done by driving a
specific signalsequence on the ICCCLK/DATA pins while theRESET pin is pulled low.
When the ST7 entersICC mode, it fetches a specific RESET vectorwhich points to the
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ST7
System
Memory
contain-ing
the
ICC
protocol
routine.
This
routine
enablesthhttp://www.wendangwang.com/doc/2c8a46421bc4f43b8223483ae ST7 to receive
bytes from the ICC interface. –Download ICP Driver code in RAM from theICCDATA pin
–Execute ICP Driver code in RAM to programthe FLASH memory
Depending on the ICP Driver code downloaded inRAM, FLASH memory programming can be
fullycustomized (number of bytes to program, programlocations, or selection of the
serial communicationinterface for downloading).
4.3.2 In Application Programming (IAP)
This mode uses an IAP Driver program previouslyprogrammed in Sector 0 by the user
(in ICPmode).
This mode is fully controlled by user software. Thisallows it to be adapted to the
user application, (us-er-defined strategy for entering programmingmode, choice of
communications protocol used tofetch the data to be stored etc.)
IAP mode can be used to program any memory ar-eas except Sector 0, which is write/erase
protect-ed
to
allow
recovery
in
case
errors
occur
duringthe
progrhttp://www.wendangwang.com/doc/2c8a46421bc4f43b8223483aamming operation.
ST7LITE3xF2
FLASH PROGRAM MEMORY (Cont’d)4.4 ICC INTERFACE
ICP needs a minimum of 4 and up to 6 pins to beconnected to the programming tool.
These pinsare:
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––VSS: device power supply ground–ICCCLK: ICC output serial clock pin–ICCDATA:
ICC input serial data pin
–CLKIN/PB4: main clock input for externalsource
–VDD: application board power supply (option-al, see Note 3)
1. If the ICCCLK or ICCDATA pins are only usedas outputs in the application, no signal
isolation isnecessary. As soon as the Programming Tool isplugged to the board, even
if an ICC session is notin progress, the ICCCLK and ICCDATA pins arenot available
for the application. If they are used asinputs by the application, isolation such
as a serialresistor has to be implemented if another deviceforces the signal. Refer
to
the
Programming
Tooldocumentation
for
recommended
resistor
values.flictshttp://www.wendangwang.com/doc/2c8a46421bc4f43b8223483a between the
programming tool and the appli-cation reset circuit if it drives more than 5mA athigh
level (push pull output or pull-up resistor1K or a reset man-agement IC with open
drain output and pull-up re-sistor>1K, no additional components are needed.In all
cases the user must ensure that no externalreset is generated by the application
during theICC session.
3. The use of Pin 7 of the ICC connector dependson the Programming Tool architecture.
This pinming Tools (it is used to monitor the applicationpower supply). Please refer
to the ProgrammingTool manual.
4. Pin 9 must be connected to the PB4 pin of theST7 when the clock is not available
in the applica-tion or if the selected clock option is not pro-grammed in the option
byte. ST7 devices withmulti-oscillator capability must have OSC2grounded in this
case.
5. With any programming tool, while the ICP optionis disabled, the external clock
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must be prohttp://www.wendangwang.com/doc/2c8a46421bc4f43b8223483avided onPB4.
6. In 38-pulse ICC mode, the internal RC oscillatoris forced as a clock source,
regardless of the se-lection in the option byte. For ST7LITE30 deviceswhich do not
support the internal RC oscillator, the“option byte disabled” mode must be used
(35-pulse ICC mode entry, clock provided by the tool).Caution: During normal
operation ICCCLK pinmust be pulled- up, internally or externally (exter-nal pull-up
of 10k mandatory in noisy environ-ment). This avoids entering ICC modeunexpectedly
during a reset. In the application,even if the pin is configured as output, any
resetputs it back in input pull-up.
ST7LITE3xF2
FLASH PROGRAM MEMORY (Cont’d)4.5 Memory Protection
There are two different types of memory protec-tion: Read Out Protection and
Write/Erase Protec-tion which can be applied individually.4.5.1 Read out Protection
Readout
protection,
when
selected
provides
agahttp://www.wendangwang.com/doc/2c8a46421bc4f43b8223483ainst
a
pro-tection
program
memory
content extrac-tion and against write access to Flash memory.Even if no protection
can be considered as totallyunbreakable, the feature provides a very high levelof
protection for a general purpose microcontroller.Both program and data E2 memory are
protected. In flash devices, this protection is removed by re-programming the option.
In this case, both pro-gram and data E2 memory are automaticallyerased and the device
can be reprogrammed.– Read-out protection selection is enabled and re-moved through
the FMP_R bit in the option byte.4.5.2 Flash Write/Erase Protection
Write/erase protection, when set, makes it impos-sible to both overwrite and erase
program memo-ry. It does not apply to E2 data. Its purpose is toprovide advanced
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security to applications and pre-vent any change being made to the memory con-tent.
Warning: Once set, Write/erase protection cannever be removed. A write-protected
flashttp://www.wendangwang.com/doc/2c8a46421bc4f43b8223483ah deviceis no longer
reprogrammable.
Write/erase protection is enabled through theFMP_W bit in the option byte.
4.6 Related Documentation
For details on Flash programming and ICC proto-col, refer to the ST7 Flash Programming
Refer-ence Manual and to the ST7 ICC Protocol Refer-ence Manual.
4.7 Register Description
FLASH CONTROL/STATUS REGISTER (FCSR)Read/Write
Reset Value: 000 0000 (00h)1st RASS Key: 0101 0110 (56h)2nd RASS Key: 1010 1110 (AEh)
70
OPT
LAT
0PGM
Note: This register is reserved for programmingusing ICP, IAP or other programming
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methods. Itcontrols the XFlash programming and erasing op-erations.
When an EPB or another programming tool isused (in socket or ICP mode), the RASS keys
aresent automatically.
ST7LITE3xF2
5 DATA EEPROM
5.1 INTRODUCTION
The Electrically Erasabhttp://www.wendangwang.com/doc/2c8a46421bc4f43b8223483ale
Programmable ReadOnly Memory can be used as a non volatile back-up for storing data.
Using the EEPROM requires abasic access protocol described in this chapter.
5.2 MAIN FEATURES
■■■■
■■
Up to 32 Bytes programmed in the same cycleEEPROM mono-voltage (charge pump)Chained
erase and programming cycles
Internal control of the global programming cycleduration
WAIT mode managementReadout protection
Figure 6. EEPROM Block Diagram
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HIGHVOLTAGE
PUMP
EECSR
000000E2LATADDRESSDECODER
4
ROWDECODER
EEPROMMEMORYMATRIX(1ROW=32x8BITS)
44
DATAMULTIPLEXER
32x8BITSDATALATCHES
ADDRESSBUSDATABUS
ST7LITE3xF2
DATA EEPROM (Cont’d)5.3 MEMORY ACCESS
The Data EEPROM memory read/write accessmodes are controlled by the E2LAT bit of the
EEP-ROM
Control/Status
register
(EECSRhttp://www.wendangwang.com/doc/2c8a46421bc4f43b8223483a). The flow-chart in
Figure 7 describes these different memoryaccess modes.
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Read Operation (E2LAT=0)
The EEPROM can be read as a normal ROM loca-tion when the E2LAT bit of the EECSR
register iscleared.
On this device, Data EEPROM can also be used toexecute machine code. Take care not
to write tothe Data EEPROM while executing from it. Thiswould result in an unexpected
code being execut-ed.
Write Operation (E2LAT=1)
To access the write mode, the E2LAT bit has to beset by software (the E2PGM bit remains
cleared).When a write access to the EEPROM area occurs,Figure 7. Data EEPROM
Programming Flowchart
the value is latched inside the 32 data latches ac-cording to its address.
When PGM bit is set by the software, all the previ-ous bytes written in the data latches
(up to 32) areprogrammed in the EEPROM cells. The effectivehigh address (row) is
determined
by
the
last
EEP-ROM
http://www.wendangwang.com/doc/2c8a46421bc4f43b8223483awrite sequence. To avoid
wrong program-ming, the user must take care that all the byteswritten between two
programming sequenceshave the same high address: only the five LeastSignificant Bits
of the address can change.
At the end of the programming cycle, the PGM andLAT bits are cleared simultaneously.
Note: Care should be taken during the program-ming cycle. Writing to the same memory
locationwill over-program the memory (logical AND be-tween the two write access data
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result) becausethe data latches are only cleared at the end of theprogramming cycle
and by the falling edge of theE2LAT bit.
It is not possible to read the latched data.This note is ilustrated by the Figure
9.
READMODEE2LAT=0E2PGM=0WRITEMODEE2LAT=1E2PGM=0
READBYTESINEEPROMAREA
WRITEUPTO32BYTESINEEPROMAREA
(withthesame11MSBoftheaddress)
STARTPROGRAMMINGCYCLE
E2LAT=1
E2PGM=1(setbyhttp://www.wendangwang.com/doc/2c8a46421bc4f43b8223483asoftware)
CLEAREDBYHARDWARE
1
ST7LITE3xF2
DATA EEPROM (Cont’d)
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Figure 8. Data E2PROM Write Operation
? Row / Byte ?
ROW
DEFINITION
01...N
Readoperationimpossible
1
2
3
...
3031
Physical Address
00h...1Fh20h...3FhNx20h...Nx20h 1Fh
Readoperationpossible
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Byte1Byte2
PHASE 1
Byte32Programmingcycle
PHASE 2
Writingdatalatches
E2LATbit
SetE2PGMandE2LATtoCleared by hardware
E2PGMbit
Note: If a programming cycle is interrupted (by a reset action), the integrity of
the data in memory is not guaranteed.
ST7LITE3xF2
DATA EEPROM (Cont’d)5.4 POWER SAVING MODES
Wait mode
The DATA EEPROM can enter WAIT mode on ex-ecution of the WFI instruction of the
mihttp://www.wendangwang.com/doc/2c8a46421bc4f43b8223483acrocontrol-ler or when
the microcontroller enters Active-HALTmode.The DATA EEPROM will immediately
enterthis mode if there is no programming in progress,otherwise the DATA EEPROM will
finish the cycleand then enter WAIT mode.Active-Halt modeRefer to Wait mode.
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Halt mode
The DATA EEPROM immediately enters HALTmode if the microcontroller executes the HALT
in-struction. Therefore the EEPROM will stop thefunction in progress, and data may
be corrupted.
5.5 ACCESS ERROR HANDLING
If a read access occurs while E2LAT=1, then thedata bus will not be driven.
If a write access occurs while E2LAT=0, then thedata on the bus will not be latched.
If a programming cycle is interrupted (by RESETaction), the integrity of the data
in memory is notguaranteed.
5.6 Data EEPROM Read-out ProtectionThe read-out protection is enabled through an
op-tion bit (see section 15.1 on page 161).
://www.wendangwang.com/doc/2c8a46421bc4f43b8223483aWhen this option is selected,
the programs anddata stored in the EEPROM memory are protectedagainst read-out
(including a re-write protection).In Flash devices, when this protection is removedby
reprogramming the Option Byte, the entire Pro-gram memory and EEPROM is first
automaticallyerased.
Note: Both Program Memory and data EEPROMare protected using the same option bit.
Figure 9. Data EEPROM Programming Cycle
READOPERATIONNOTPOSSIBLE
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INTERNAL
PROGRAMMINGVOLTAGE
ERASECYCLE
WRITEOFDATALATCHES
WRITECYCLE
READOPERATIONPOSSIBLE
tPROG
LAT
PGM
ST7LITE3xF2
DATA EEPROM (Cont’d)5.7 REGISTER DESCRIPTION
EEPROM CONTROL/STATUS REGISTER (EEC-SR)
Read/Write
Reset Value: 0000 0000 (00h)
70
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E2LATE2PGM
Bits
7:2
=
Reserved,
forced
by
hardware
to
E2http://www.wendangwang.com/doc/2c8a46421bc4f43b8223483aLAT
0.Bit
Latch
1
=
Access
Transfer
This bit is set by software. It is cleared by hard-ware at the end of the programming
cycle. It canonly be cleared by software if the E2PGM bit iscleared.
0: Read mode 1: Write mode
Bit 0 = E2PGM Programming control and statusThis bit is set by software to begin the
programmingcycle. At the end of the programming cycle, this bitis cleared by hardware.
0: Programming finished or not yet started1: Programming cycle is in progress
Note: if the E2PGM bit is cleared during the pro-gramming cycle, the memory data is
not guaran-teed
Table 4. DATA EEPROM Register Map and Reset Values
Address(Hex.)0030h
Register LabelEECSRReset Value
7
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6
5
4
3
2
1E2LAT0
0E2PGM0
ST7LITE3xF2
6 CENTRAL PROCESSING UNIT
6.1 INTRODUCTION
This CPU hashttp://www.wendangwang.com/doc/2c8a46421bc4f43b8223483a a full 8-bit
architecture
and
containssix
internal
registers
allowing
efficient
8-bit
datamanipulation.6.2 MAIN FEATURES
■■■■■■■■
63 basic instructions
Fast 8-bit by 8-bit multiply17 main addressing modesTwo 8-bit index registers16-bit
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stack pointerLow power modes
Maskable hardware interruptsNon-maskable software interrupt
6.3 CPU REGISTERS
The six CPU registers shown in Figure 10 are notpresent in the memory mapping and
are accessedby specific instructions.Figure 10. CPU Registers
7
RESET VALUE = XXh7
RESET VALUE = XXh7
RESET VALUE = XXh
15
PCH
87
PCL
0000
Accumulator (A)
The Accumulator is an 8-bit general purpose reg-ister used to hold operands and the
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results of thearithmetic and logic calculations and to manipulatedata.
Index Registers (X and Y)
In
indexed
ahttp://www.wendangwang.com/doc/2c8a46421bc4f43b8223483addressing
modes, these 8-bit registersare used to create either effective addresses ortemporary
storage areas for data manipulation.(The Cross-Assembler generates a precede
in-struction (PRE) to indicate that the following in-struction refers to the Y
register.)
The Y register is not affected by the interrupt auto-matic procedures (not pushed
to and popped fromthe stack).
Program Counter (PC)
The program counter is a 16-bit register containingthe address of the next instruction
to be executedby the CPU. It is made of two 8-bit registers PCL(Program Counter Low
which is the LSB) and PCH(Program Counter High which is the MSB).
ACCUMULATOR
X INDEX REGISTER
Y INDEX REGISTER
PROGRAM COUNTER
RESET VALUE = RESET VECTOR @ FFFEh-FFFFh
7
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111HI
0NZC
CONDITION CODE REGISTER
RESET VALUE =111X1XXX
15
87
http://www.wendangwang.com/doc/2c8a46421bc4f43b8223483a
STACK POINTER
RESET VALUE = STACK HIGHER ADDRESS
X = Undefined Value
ST7LITE3xF2
CPU REGISTERS (cont’d)
CONDITION CODE REGISTER (CC) Read/Write
Reset Value: 111x1xxx
71
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1
1
H
I
N
Z
0C
logical or data manipulation. It is a copy of the 7thbit of the result.
0: The result of the last operation is positive or null.1: The result of the last
operation is negative(that is, the most significant bit is a logic 1).This bit is
accessed by the JRMI and JRPL instruc-tions.Bit 1 = Z Zero
This bit is set and cleared by hardware. This bit in-dicates that the result of the
last arithmetic, logicalor data manipulation is zero.
0: The result of the last operation is different from zero.
1: The result of the last operation is zero.This bit is accessed by the JREQ and JRNE
http://www.wendangwang.com/doc/2c8a46421bc4f43b8223483atestinstructions.
Bit 0 = C Carry/borrow
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This bit is set and cleared by hardware and soft-ware. It indicates an overflow or
an underflow hasoccurred during the last arithmetic operation.0: No overflow or
underflow has occurred.1: An overflow or underflow has occurred.
This bit is driven by the SCF and RCF instructionsand tested by the JRC and JRNC
instructions. It isalso affected by the “bit test and branch”, shift androtate
instructions.
CPU REGISTERS (Cont’d)STACK POINTER (SP)Read/Write
Reset Value: 01FFh
15071
SP6
SP5
SP4
SP3
SP2
SP1
810SP0
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The 8-bit Condition Code register contains the in-terrupt mask and four flags
representative of theresult of the instruction just executed. This registercan also
be handled by the PUSH and POP in-structions.
These
bits
can
be
individually
andhttp://www.wendangwang.com/doc/2c8a46421bc4f43b8223483a/or
tested
con-trolled
by
specific instructions.
Bit 4 = H Half carry
This bit is set by hardware when a carry occurs be-tween bits 3 and 4 of the ALU during
an ADD orADC instruction. It is reset by hardware during thesame instructions.
0: No half carry has occurred.1: A half carry has occurred.
This bit is tested using the JRH or JRNH instruc-tion. The H bit is useful in BCD
arithmetic subrou-tines.
Bit 3 = I Interrupt mask
This bit is set by hardware when entering in inter-rupt or by software to disable
all interrupts exceptthe TRAP software interrupt. This bit is cleared bysoftware.
0: Interrupts are enabled.1: Interrupts are disabled.
This bit is controlled by the RIM, SIM and IRET in-structions and is tested by the
JRM and JRNM in-structions.
Note: Interrupts requested while I is set arelatched and can be processed when I is
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cleared.By
default
an
interruhttp://www.wendangwang.com/doc/2c8a46421bc4f43b8223483apt routine is not
interruptiblebecause the I bit is set by hardware at the start ofthe routine and reset
by the IRET instruction at theend of the routine. If the I bit is cleared by softwarein
the interrupt routine, pending interrupts areserviced regardless of the priority
level of the cur-rent interrupt routine.
Bit 2 = N Negative
This bit is set and cleared by hardware. It is repre-sentative of the result sign
of the last arithmetic,
The Stack Pointer is a 16-bit register which is al-ways pointing to the next free
location in the stack.It is then decremented after data has been pushedonto the stack
and incremented before data ispopped from the stack (see Figure 11).
Since the stack is 128 bytes deep, the 9 most sig-nificant bits are forced by hardware.
Following an
ST7LITE3xF2
MCU Reset, or after a Reset Stack Pointer instruc-tion (RSP), the Stack Pointer
contains its reset vahttp://www.wendangwang.com/doc/2c8a46421bc4f43b8223483al-ue
(the SP6 to SP0 bits are set) which is the stackhigher address.
The least significant byte of the Stack Pointer(called S) can be directly accessed
by a LD in-struction.
Note: When the lower limit is exceeded, the StackPointer wraps around to the stack
upper limit, with-out indicating the stack overflow. The previouslystored
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information is then overwritten and there-fore lost. The stack also wraps in case
of an under-flow.
The stack is used to save the return address dur-ing a subroutine call and the CPU
context duringan interrupt. The user may also directly manipulatethe stack by means
of the PUSH and POP instruc-Figure 11. Stack Manipulation Example
CALLSubroutine
@ 0180h
Interrupt Event
PUSH Y
tions. In the case of an interrupt, the PCL is storedat the first location pointed
to by the SP. Then theother registers are stored in the next locations asshown
ihttp://www.wendangwang.com/doc/2c8a46421bc4f43b8223483an Figure 11.
– When an interrupt is received, the SP is decre-mented and the context is pushed
on the stack.– On return from interrupt, the SP is incremented and the context is
popped from the stack.
A subroutine call occupies two locations and an in-terrupt five locations in the stack
area.
POP YIRET
RETor RSP
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SP
SP
CCAX
SP
PCH
@ 01FFh
PCL
PCHPCLPCHPCL
CCAXPCHPCLPCHPCL
SP
CCAXPCHPCLPCHPCL
SP
PCHPCL
SP
Stack Higher Address = 01FFhStack Lower Address =0180h
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ST7LITE3xF2
7 SUPPLY, RESET AND CLOCK MANAGEMENT
The device includes a range of utility features forsecuring the application in
critical situations (forexample in case of a power brown-out), and re-ducing the
number of external components. Main features
■
tion code. Thttp://www.wendangwang.com/doc/2c8a46421bc4f43b8223483ahis area cannot
be erased or pro-grammed by any ICC operation.
For compatibility reasons with the SICSR register,CR[1:0] bits are stored in the 5th
and 6th positionof DEE1 and DEE3 addresses.
Note:
– In 38-pulse ICC mode, the internal RC oscillator is forced as a clock source,
regardless of the se-lection in the option byte. For ST7LITE30 devic-es which do not
support the internal RC
oscillator, the “option byte disabled” mode must be used (35-pulse ICC mode entry,
clock provid-ed by the tool).
– See “ELECTRICAL CHARACTERISTICS” on page131. for more information on the
frequency and accuracy of the RC oscillator.
– To improve clock stability and frequency accura-cy, it is recommended to place
a decoupling ca-pacitor, typically 100nF, between the VDD and VSS pins as close as
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possible to the ST7 device– These bytes are systematically programmed by ST,
including
on
FASTROM
http://www.wendangwang.com/doc/2c8a46421bc4f43b8223483aConse-quently,
devices.
customers
intending to use FASTROM service must not use these bytes.
– RCCR0 and RCCR1 calibration values will not be erased if the read-out protection
bit is reset af-ter it has been set . See “Read out Protection” on page14.
Caution: If the voltage or temperature conditionschange in the application, the
frequency may needto be recalibrated.
Refer to application note AN1324 for informationon how to calibrate the RC frequency
using an ex-ternal reference signal.7.2 PHASE LOCKED LOOP
The PLL can be used to multiply a 1MHz frequen-cy from the RC oscillator or the external
clock by 4or 8 to obtain fOSC of 4 or 8 MHz. The PLL is ena-bled and the multiplication
factor of 4 or 8 is select-ed by 2 option bits.
– The x4 PLL is intended for operation with VDD in the 2.7V to 3.3V range
– The x8 PLL is intended for operation with VDD in the 3.3V to 5.5V range
Refer http://www.wendangwang.com/doc/2c8a46421bc4f43b8223483ato Section 15.1 for
the option byte descrip-tion.
If the PLL is disabled and the RC oscillator is ena-bled, then fOSC = 1MHz.
Clock Management
–1 MHz internal RC oscillator (enabled by op-tion byte, available on ST7LITE35
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andST7LITE39 devices only)
–1 to 16 MHz or 32kHz External crystal/ceramicresonator (selected by option byte)
–External Clock Input (enabled by option byte)–PLL for multiplying the frequency
by 8 or 4(enabled by option byte)Reset Sequence Manager (RSM)
System Integrity Management (SI)
–Main supply Low voltage detection (LVD) withreset generation (enabled by option
byte)–Auxiliary Voltage detector (AVD) with interruptcapability for monitoring the
main supply (en-abled by option byte)
■■
7.1 INTERNAL RC OSCILLATOR ADJUSTMENTThe device contains an internal RC oscillator
withan
accuracy
of
1%
for
a
given
device,
temperatureand
voltage
ranghttp://www.wendangwang.com/doc/2c8a46421bc4f43b8223483ae (4.5V-5.5V). It must
be calibrat-ed to obtain the frequency required in the applica-tion. This is done
by software writing a 8-bit cali-bration value in the RCCR (RC Control Register)and
in the bits [6:5] in the SICSR (SI Control Sta-tus Register).
Whenever the microcontroller is reset, the RCCRreturns to its default value (FFh),
i.e. each time thedevice is reset, the calibration value must be load-ed in the RCCR.
Predefined calibration values arestored in EEPROM for 3V and 5V VDD supply volt-ages
at 25°C, as shown in the following table.
RCCRRCCRH0RCCRL0RCCRH1RCCRL1
ConditionsVDD=5VTA=25°CfRC=1MHzVDD=3.3VTA=25°CfRC=1MHz
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ST7LITE3
Addresses
DEE0h (CR[9:2] bits)DEE1h 1) (CR[1:0] bits)DEE2h (CR[9:2] bits)DEE3h 1) (CR[1:0]
bits)
1. DEE0h, DEE1h, DEE2h and DEE3h addressesare located in a reserved area of
non-volatilememory. They are read-only bytes for the applica://www.wendangwang.com/doc/2c8a46421bc4f43b8223483aST7LITE3xF2
If both the RC oscillator and the PLL are disabled,fOSC is driven by the external
clock.
Figure 12. PLL Output Frequency TimingDiagram
LOCKED bit set
4/8 x inputfreq.
tSTAB
7.3 REGISTER DESCRIPTION
MAIN CLOCK CONTROL/STATUS REGISTER(MCCSR)Read / Write
Reset Value:
70
0000 0000 (00h)
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MCO
SMS
Bits 7:2 = Reserved, must be kept cleared.
Output freq.
tBit 1 = MCO Main Clock Out enable
This bit is read/write by software and cleared byhardware after a reset. This bit
allows to enablethe MCO output clock.
0: MCO clock disabled, I/O port free for general purpose I/O.
1: MCO clock enabled.
Bit 0 = SMS Slow Mode select
This bit is read/write by software and cleared byhardware after a reset. This bit
selects
the
inputclock
fOSC
or
fOSC/32.http://www.wendangwang.com/doc/2c8a46421bc4f43b8223483a
0: Normal mode (fCPU = fOSC 1: Slow mode (fCPU = fOSC/32)RC CONTROL REGISTER (RCCR)Read
/ Write
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Reset Value:
1111 1111 (FFh)
7CR9
CR8
CR7
CR6
CR5
CR4
CR3
0CR2
t
When the PLL is started, after reset or wakeupfrom Halt mode or AWUFH mode, it outputs
theclock after a delay of tSTARTUP.
When the PLL output signal reaches the operatingfrequency, the LOCKED bit in the
SICSCR registeris set. Full PLL accuracy (ACCPLL) is reached aftera stabilization
time of tSTAB (see Figure 12 and13.3.4Internal RC Oscillator and PLL)
Refer to section 7.6.4 on page 34 for a descriptionof the LOCKED bit in the SICSR
register.
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Bits 7:0 = CR[9:2] RC Oscillator Frequency Ad-justment Bits
These bits must be written immediately after resetto adjust the RC oscillator
frequency
and
to
obtainan
accuracy
of
applichttp://www.wendangwang.com/doc/2c8a46421bc4f43b8223483aation
1%.
can
The
store
thecorrect value for each voltage range in EEPROMand write it to this register at
start-up. 00h = maximum available frequencyFFh = lowest available frequency
These bits are used with the CR[1:0] bits in theSICSR register. Refer to section 7.6.4
on page 34Note: To tune the oscillator, write a series of differ-ent values in the
register until the correct frequen-cy is reached. The fastest method is to use a
di-chotomy starting with 80h.
ST7LITE3xF2
Figure 13. Clock Management Block Diagram
CR9
CR8
CR7
CR6
CR5
CR4
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CR3
CR2
RCCR
CR1CR0
SICSR
CLKIN/2 (Ext Clock)
8MHz
PLL 1MHz -> 8MHz
PLL 1MHz -> 4MHz4MHz
OSC Option bit
PLL Clock
Tunable 1% RCOscillator
1MHz
OSCRANGE[2:0]
Option bits
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CLKIN
CLKhttp://www.wendangwang.com/doc/2c8a46421bc4f43b8223483aIN
CLKIN
CLKIN
/2 DIVIDER
fOSC
OSCRANGE[2:0]
Option bits
CLKIN/OSC1OSC2
OSC1-16 MHZor 32kHz
/2 DIVIDER
Crystal OSC /2
8-BIT
LITE TIMER 2 COUNTER
fOSC
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/32 DIVIDER /32 DIVIDER
fOSC0
fLTIMER
OSC)
fCPU
TO CPU AND
PERIPHERALS
fMCOSMSMCCSR
fCPU
MCO
ST7LITE3xF2
7.4 MULTI-OSCILLATOR (MO)
The main clock of the ST7 can be generated byfour different source types coming from
the multi-oscillator block (1 to 16MHz or 32kHz):■an external source
■ 5 crystal or ceramic resonator oscillators■an internal high frequency RC
oscillator
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Each oscillator is optimized for a given frequencyrange in terms of consumption and
is selectablethrough the option byte. The associated hardwareconfigurations are
shown in http://www.wendangwang.com/doc/2c8a46421bc4f43b8223483aTable 5. Refer to
theelectrical characteristics section for more details.External Clock Source
In this external clock mode, a clock signal (square,sinus or triangle) with ~50% duty
cycle has to drivethe OSC1 pin while the OSC2 pin is tied to ground. Note: when the
Multi-Oscillator is not used, PB4 isselected by default as external clock.
Crystal/Ceramic Oscillators
This family of oscillators has the advantage of pro-ducing a very accurate rate on
the main clock ofthe ST7. The selection within a list of 4 oscillatorswith different
frequency ranges has to be done byoption byte in order to reduce consumption (referto
section 15.1 on page 161 for more details on thefrequency ranges). In this mode of
the multi-oscil-lator, the resonator and the load capacitors haveto be placed as close
as possible to the oscillatorpins in order to minimize output distortion andstart-up
stabilization
time.
The
loading
capaci-tahttp://www.wendangwang.com/doc/2c8a46421bc4f43b8223483ance values must
be adjusted according to theselected oscillator.
These oscillators are not stopped during theRESET phase to avoid losing time in the
oscillatorstart-up phase.
Internal RC Oscillator
In this mode, the tunable 1%RC oscillator is usedas main clock source. The two
oscillator pins haveto be tied to ground.
The calibration is done through the RCCR[7:0] andSICSR[6:5] registers.Table 5. ST7
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Clock Sources
HardwareConfiguration
ExternalClock
ST7
OSC1
OSC2
EXTERNALSOURCE
Crystal/CeramicResonators
ST7
OSC1
OSC2
CL1
LOADCAPACITORS
CL2
InternalRCOscillator
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ST7
OSC1
OSC2
ST7LITE3xF2
7.5 RESET SEQUENCE MANAGER (RSM)7.5.1 Introduction
The reset sequence manager includes three RE-SET sources as shown in Figure
15:■■Internhttp://www.wendangwang.com/doc/2c8a46421bc4f43b8223483aal LVD RESET
(Low Voltage Detection)■Internal WATCHDOG RESET
Note: A reset can also be triggered following thedetection of an illegal opcode or
prebyte code. Re-fer to section 12.2.1 on page 128 for further de-tails.
ways kept low during the delay phase.
The RESET service routine vector is fixed at ad-dresses FFFEh-FFFFh in the ST7 memory
map.The basic RESET sequence consists of 3 phasesas shown in Figure 14:
■Active Phase depending on the RESET source■256 or 4096 CPU clock cycle delay (see
tablebelow)
■RESET vector fetch
Caution: When the ST7 is unprogrammed or fullyerased, the Flash is blank and the RESET
vectoris not programmed. For this reason, it is recom-mended to keep the RESET pin
in low state untilprogramming mode is entered, in order to avoidunwanted behavior.
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The 256 or 4096 CPU clock cycle delay allows theoscillator to stabilise and ensures
that
recoveryhas
http://www.wendangwang.com/doc/2c8a46421bc4f43b8223483ataken
place from the Reset state. The shorteror longer clock cycle delay is automatically
select-ed depending on the clock source chosen by op-tion byte:
The RESET vector fetch phase duration is 2 clockcycles.
Clock Source
Internal RC Oscillator
External
clock
(connected
to
CLKIN
pin)External
Crystal/Ceramic
Oscillator(connected to OSC1/OSC2 pins)
CPU clock cycle delay
256256
4096
If the PLL is enabled by option byte, it outputs theclock after an additional delay
of tSTARTUP (seeFigure 12).
Figure 14. RESET Sequence Phases
RESET
Active Phase
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INTERNAL RESET
256 or 4096 CLOCK CYCLES
FETCHVECTOR
output with integrated RON weak pull-up resistor.This pull-up has no fixed value but
varies in ac-cordance with the input voltage. It can be pulledlow by external
circuitry
to
reset
the
device.
SeeElectrical
Chhttp://www.wendangwang.com/doc/2c8a46421bc4f43b8223483aaracteristic section for
more details.A RESET signal originating from an externalsource must have a duration
of at least th(RSTL)in inorder to be recognized (see Figure 16). This de-tection is
asynchronous and therefore the MCUcan enter reset state even in HALT mode.
ST7LITE3xF2
Figure 15. Reset Block Diagram
ST7LITE3xF2
RESET SEQUENCE MANAGER (Cont’d)plays a major role in EMS performance. In a
noisyenvironment, it is recommended to follow theguidelines mentioned in the
electrical characteris-tics section.
7.5.3 External Power-On RESET
If the LVD is disabled by option byte, to start up themicrocontroller correctly, the
user must ensure bymeans of an external reset circuit that the resetsignal is held
low until VDD is over the minimumlevel specified for the selected fOSC frequency.
A proper reset signal for a slow rising VDD supplycan generally be provided by an
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external
RC
net-7http://www.wendangwang.com/doc/2c8a46421bc4f43b8223483a.5.4
Internal Low Voltage Detector (LVD)RESET
Two different RESET sequences caused by the in-ternal LVD circuitry can be
distinguished:■Power-On RESET■Voltage Drop RESET
pulled low when VDD
7.5.5 Internal Watchdog RESET
The RESET sequence generated by a internalWatchdog counter overflow is shown in Figure
16.Starting from the Watchdog counter underflow, thelow during at least tw(RSTL)out.
Figure 16. RESET Sequences
VDD
VIT (LVD)VIT-(LVD)
LVDRESET
EXTERNALRESET
WATCHDOGRESET
RUN
RUN
ACTIVEPHASE
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RUN
PHASE
RUN
th(RSTL)in
EXTERNALSOURCE
tPIN
WATCHDOGRESET
WATCHDOGUNDERFLOW
INTERNALRESET(256 or 4096TCPU)VECTOR FETCH
ST7LITE3xF2
7.6 SYSTEM INTEGRITY MANAGEMENT (SI)The System Integrity Management block
containsthe
Low
http://www.wendangwang.com/doc/2c8a46421bc4f43b8223483aDetector
voltage
(LVD)
and
Auxiliary Volt-age Detector (AVD) functions. It is managed bythe SICSR register.
Note: A reset can also be triggered following thedetection of an illegal opcode or
prebyte code. Re-fer to section 12.2.1 on page 128 for further de-tails.
7.6.1 Low Voltage Detector (LVD)
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The Low Voltage Detector function (LVD) gener-ates a static reset when the VDD supply
voltage isbelow a VIT-(LVD) reference value. This means thatit secures the power-up
as well as the power-downkeeping the ST7 in reset.
The VIT-(LVD) reference value for a voltage drop islower than the VIT (LVD) reference
value for power-on in order to avoid a parasitic reset when theMCU starts running
and sinks current on the sup-ply (hysteresis).
The LVD Reset circuitry generates a reset whenVDD is below:
–VIT (LVD)when VDD is rising –VIT-(LVD) when VDD is falling
The
LVD
function
is
illustrated
in
Fihttp://www.wendangwang.com/doc/2c8a46421bc4f43b8223483agure 17.
The voltage threshold can be configured by optionbyte to be low, medium or high.
Provided the minimum VDD value (guaranteed forthe oscillator frequency) is above
VIT-(LVD), theMCU can only be in two modes: –under full software control–in static
safe reset
In these conditions, secure operation is always en-sured for the application without
the need for ex-ternal reset hardware.
pin is held low, thus permitting the MCU to resetother devices.
Notes:
The LVD allows the device to be used without anyexternal RESET circuitry.
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Use of LVD with capacitive power supply: with thistype of power supply, if power cuts
occur in the ap-plication, it is recommended to pull VDD down to0V to ensure optimum
restart conditions. Refer tocircuit example in Figure 99 on page154 and note4.
The LVD is an optional function which can be se-lected by option byte.
It is rechttp://www.wendangwang.com/doc/2c8a46421bc4f43b8223483aommended to make
sure that the VDD sup-ply voltage rises monotonously when the device isexiting from
Reset, to ensure the application func-tions properly.
Figure 17. Low Voltage Detector vs Reset
ST7LITE3xF2
Figure 18. Reset and Supply Management Block Diagram
WATCHDOGTIMER (WDG)
STATUS FLAG
SYSTEM INTEGRITYMANAGEMENT
RESETSEQUENCE
MANAGER(RSM)
SICSR
WDGRFLOCKEDAVDFAVDIE
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LOW VOLTAGE
VSSVDD
DETECTOR(LVD)
AUXILIARYVOLTAGE
DETECTOR(AVD)
ST7LITE3xF2
SYSTEM INTEGRITY MANAGEMENT (Cont’d)7.6.2 Auxiliary Voltage Detector (AVD)
The Voltage Detector function (AVD) is based onan analog comparison between a VIT-(AVD)
andVIT (AVD) reference value and the VDD main sup-ply voltage (VAVD). The VIT-(AVD)
reference valuefor falling voltage is lower than the VIT (AVD) refer-ence value for
rihttp://www.wendangwang.com/doc/2c8a46421bc4f43b8223483asing voltage in order to
avoid par-asitic detection (hysteresis).
The output of the AVD comparator is directly read-able by the application software
through a realtime status bit (AVDF) in the SICSR register. Thisbit is read only.
Caution: The AVD functions only if the LVD is en-abled through the option byte.
7.6.2.1 Monitoring the VDD Main Supply
The AVD voltage threshold value is relative to theselected LVD threshold configured
by option byte(see section 15.1 on page 161).
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If the AVD interrupt is enabled, an interrupt is gen-erated when the voltage crosses
the VIT (LVD) orVIT-(AVD) threshold (AVDF bit is set).
In the case of a drop in voltage, the AVD interruptacts as an early warning, allowing
software to shutdown safely before the LVD resets the microcon-troller. See Figure
19.
ST7LITE3xF2
SYSTEM INTEGRITY MANAGEMENT (Cont’d)7.6.3 Low Power Modes
Whttp://www.wendangwang.com/doc/2c8a46421bc4f43b8223483aAIT
No effect on SI. AVD interrupts cause the device to exit from Wait mode.The SICSR
register is frozen.
The AVD becomes inactive and the AVD in-terrupt cannot be used to exit from Halt mode.
set and the interrupt mask in the CC register is re-set (RIM instruction).
Interrupt EventAVD event
Enable Exit
Event
Control from
Flag
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BitWaitAVDF
AVDIE
Yes
Exit
from HaltNo
HALT
7.6.3.1 Interrupts
The AVD interrupt event generates an interrupt ifthe corresponding Enable Control
Bit (AVDIE) is
ST7LITE3xF2
SYSTEM INTEGRITY MANAGEMENT (Cont’d)
7.6.4 Register Description
SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR)Read/WriteBit 1 = AVDF Voltage
Detector flag
This read-only bit is set and cleared by hardware.Reset Value: 0110 0xx0 (6xh)
If thhttp://www.wendangwang.com/doc/2c8a46421bc4f43b8223483ae AVDIE bit is set, an
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interrupt request is gen-erated when the AVDF bit is set. Refer to Figure70
19 and to Section 7.6.2.1 for additional details.0: VDD over AVD threshold WDG
0CR1CR0LOCKEDLVDRFAVDFAVDIE
1: VDD under AVD threshold RFBit 7 = Reserved, must be kept cleared.
Bits 6:5 = CR[1:0] RC Oscillator Frequency Ad-justment bits
These bits, as well as CR[9:2] bits in the RCCRregister must be written immediately
after reset toadjust the RC oscillator frequency and to obtain anaccuracy of 1%. Refer
to section 7.3 on page 24Bit 4 = WDGRF Watchdog reset flag
This bit indicates that the last Reset was generat-ed by the Watchdog peripheral.
It is set by hard-ware (watchdog reset) and cleared by software (byreading SICSR
register) or an LVD Reset (to en-sure a stable cleared state of the WDGRF flagwhen
CPU starts).
Combined
with
the
LVDRF
flag
information,
theflag
descripthttp://www.wendangwang.com/doc/2c8a46421bc4f43b8223483aion is given by the
following table.
RESET SourcesWatchdogLVD
LVDRF
001
WDGRF
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01X
Bit 0 = AVDIE Voltage Detector interrupt enableThis bit is set and cleared by software.
It enablesan interrupt to be generated when the AVDF flag isset. The pending interrupt
information is automati-cally cleared when software enters the AVD inter-rupt
routine.
0: AVD interrupt disabled1: AVD interrupt enabled
Application notes
The LVDRF flag is not cleared when another RE-SET type occurs (external or watchdog),
theLVDRF flag remains set to keep trace of the origi-nal failure.
In this case, a watchdog reset can be detected bysoftware while an external reset
can not.
Bit 3 = LOCKED PLL Locked Flag
This bit is set by hardware. It is cleared only by apower-on reset. It is set
automatically
when
thePLL
reaches
its
operating
frequency.0:
PLL
not
lockhttp://www.wendangwang.com/doc/2c8a46421bc4f43b8223483aed1: PLL locked
Bit 2 = LVDRF LVD reset flag
This bit indicates that the last Reset was generat-ed by the LVD block. It is set
by hardware (LVD re-set) and cleared by software (by reading). Whenthe LVD is disabled
by OPTION BYTE, the LVDRFbit value is undefined.
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ST7LITE3xF2
8 INTERRUPTS
The ST7 core may be interrupted by one of two dif-ferent methods: Maskable hardware
interrupts aslisted in the “interrupt mapping” table and a non-maskable software
interrupt (TRAP). The Interruptprocessing flowchart is shown in Figure 20.
The maskable interrupts must be enabled byclearing the I bit in order to be serviced.
However,disabled interrupts may be latched and processedwhen they are enabled (see
external interruptssubsection).
Note: After reset, all interrupts are disabled.When an interrupt has to be serviced:
–
Normal
processing
is
suspended
at
the
end
of
the
current
http://www.wendangwang.com/doc/2c8a46421bc4f43b8223483ainstruction execution.
– The PC, X, A and CC registers are saved onto the stack.
– The I bit of the CC register is set to prevent addi-tional interrupts.
– The PC is then loaded with the interrupt vector of the interrupt to service and
the first instruction of the interrupt service routine is fetched (refer to the
Interrupt Mapping table for vector address-es).
The interrupt service routine should finish with theIRET instruction which causes
the contents of thesaved registers to be recovered from the stack. Note: As a
consequence of the IRET instruction,the I bit is cleared and the main program
resumes.Priority Management
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By default, a servicing interrupt cannot be inter-rupted because the I bit is set
by hardware enter-ing in interrupt routine.
In the case when several interrupts are simultane-ously pending, an hardware priority
defines
whichone
will
be
serviced
first
(see
the
http://www.wendangwang.com/doc/2c8a46421bc4f43b8223483aInterrupt Map-ping table).
Interrupts and Low Power Mode
All interrupts allow the processor to leave theWAIT low power mode. Only external
and specifi-cally mentioned interrupts allow the processor toleave the HALT low power
mode (refer to the “Exitfrom HALT” column in the Interrupt Mapping ta-ble).
8.1 NON MASKABLE SOFTWARE INTERRUPTThis interrupt is entered when the TRAP
instruc-tion is executed regardless of the state of the I bit.It is serviced according
to the flowchart in Figure20.
8.2 EXTERNAL INTERRUPTS
External interrupt vectors can be loaded into thePC register if the corresponding
external interruptoccurred and if the I bit is cleared. These interruptsallow the
processor to leave the HALT low powermode.
The external interrupt polarity is selected throughthe miscellaneous register or
interrupt register (ifavailable).
An
external
interrupt
triggered
wilhttp://www.wendangwang.com/doc/2c8a46421bc4f43b8223483al
on
belatched
edge
and
the
interrupt request automaticallycleared upon entering the interrupt service
routine.Caution: The type of sensitivity defined in the Mis-cellaneous or Interrupt
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register (if available) ap-plies to the ei source. In case of a NANDed source(as
described in the I/O ports section), a low levelon an I/O pin, configured as input
with interrupt,masks the interrupt request even in case of rising-edge sensitivity.
8.3 PERIPHERAL INTERRUPTS
Different peripheral interrupt flags in the statusregister are able to cause an
interrupt when theyare active if both:
– The I bit of the CC register is cleared.
– The corresponding enable bit is set in the control register.
If any of these two conditions is false, the interruptis latched and thus remains
pending.Clearing an interrupt request is done by:
– Writing “0” to the corresponding bit in the status register or
– Acceshttp://www.wendangwang.com/doc/2c8a46421bc4f43b8223483as to the status
register while the flag is set followed by a read or write of an associated reg-ister.
Note: The clearing sequence resets the internallatch. A pending interrupt (that is,
waiting for beingenabled) will therefore be lost if the clear se-quence is executed.
ST7LITE3xF2
INTERRUPTS (cont’d)
Figure 20. Interrupt Processing Flowchart
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FROMRESET
I BITY
N
N
Y
FETCHNEXTINSTRUCTION
N
IRET?
Y
STACKPC,X,A,CC
SETIBIT
LOADPCFROMINTERRUPTVECTOR
EXECUTEINSTRUCTION
RESTOREPC,X,A,CCFROMSTACKTHISCLEARSIBITBYDEFAULT
Table 6. Interrupt Mapping
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N°
Source BlockRESETTRAP
012345678910111213
LITETIMER
SPIAT TIMERAWUei0ei1ei2ei3
Reset
Software Interrupt7 InterruptExternal Interrupt 0External Interrupt 1External
Inhttp://www.wendangwang.com/doc/2c8a46421bc4f43b8223483aterrupt
Interrupt 3
LTCSR2SCICR1/SCICR2SICSRPWMxCSR or ATCSRATCSRLTCSRLTCSRSPICSRATCSR2
LowestPriority
nonononoyesnoyesyesno
N/A
yes
Description
Register PriorityLabelOrderN/AAWUCSR
2External
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Exit
fromHALTyes
HighestPriority
noyes
Address
VectorFFFEh-FFFFhFFFCh-FFFDhFFFAh-FFFBhFFF8h-FFF9hFFF6h-FFF7hFFF4h-FFF5hFFF2h-FF
F3hFFF0h-FFF1hFFEEh-FFEFhFFECh-FFEDhFFEAh-FFEBhFFE8h-FFE9hFFE6h-FFE7hFFE4h-FFE5h
FFE2h-FFE3hFFE0h-FFE1h
LITETIMERLITE TIMER RTC2 interruptLINSCISIAT TIMER
LINSCI InterruptAVD interrupt
AT TIMER Output Compare Interrupt or Input Capture InterruptAT TIMER Overflow
Interrupt LITE TIMER Input Capture InterruptLITE TIMER RTC1 Interrupt SPI Peripheral
InterruptsAT TIMER Overflow Interrupt 2
Note 2: These interrupts exit the MCU from “ACTIVE-HALT” mode only.
ST7LITE3xF2
://www.wendangwang.com/doc/2c8a46421bc4f43b8223483arINTERRUPTS (Cont’d)
EXTERNAL INTERRUPT CONTROL REGISTER(EICR)
Read/Write
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Reset Value: 0000 0000 (00h)
7IS31
IS30
IS21
IS20
IS11
IS10
IS01
0IS00
EXTERNAL INTERRUPT SELECTION REGIS-TER (EISR)Read/Write
Reset Value: 0000 0000 (00h)
7ei31
ei30
ei21
ei20
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ei11
ei10
ei01
0ei00
Bit 7:6 = IS3[1:0] ei3 sensitivity
These bits define the interrupt sensitivity for ei3(Port B0) according to Table 7.
Bit 5:4 = IS2[1:0] ei2 sensitivity
These bits define the interrupt sensitivity for ei2(Port B3) according to Table 7.
Bit 3:2 = IS1[1:0] ei1 sensitivity
These bits define the interrupt sensitivity for ei1(Port A7) according to Table 7.
Bit 1:0 = IS0[1:0] ei0 sensitivity
These
bits
define
thehttp://www.wendangwang.com/doc/2c8a46421bc4f43b8223483a
interrupt sensitivity for ei0(Port A0) according to Table 7.
Note: These 8 bits can be written only when the Ibit in the CC register is set.Table
7. Interrupt Sensitivity Bits
ISx1ISx00011
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0101
External Interrupt Sensitivity
Falling edge & low level
Rising edge onlyFalling edge onlyRising and falling edge
Bit 7:6 = ei3[1:0] ei3 pin selection
These bits are written by software. They select thePort B I/O pin used for the ei3
external interrupt ac-cording to the table below.
External Interrupt I/O pin selection
ei310011
ei300101
I/O PinNo interrupt *
PB0PB1PB2
* Reset State
Bit 5:4 = ei2[1:0] ei2 pin selection
These bits are written by software. They select thePort B I/O pin used for the ei2
external interrupt ac-cording to the table below.
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External Interrupt I/O pin selection
://www.wendangwang.com/doc/2c8a46421bc4f43b8223483arei210011
ei200101
I/O PinNo interrupt *
PB3PB5PB6
* Reset State
ST7LITE3xF2
INTERRUPTS (Cont’d)
Bit 3:2 = ei1[1:0] ei1 pin selection
These bits are written by software. They select thePort A I/O pin used for the ei1
external interrupt ac-cording to the table below.
External Interrupt I/O pin selection
ei110011
ei100101
I/O PinNo interrupt*
PA4PA5PA6
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Port A I/O pin used for the ei0 external interrupt ac-cording to the table below.
External Interrupt I/O pin selection
ei010011
ei000101
I/O PinNo Interrupt*
PA1PA2PA3
* Reset StateBits 1:0 = Reserved.
* Reset State
Bit 1:0 = ei0[1:0] ei0 pin selection
These bits are written by software. They select the
ST7LITE3xF2
9 POWER SAVING MODES
9.1 INTRODUCTION://www.wendangwang.com/doc/2c8a46421bc4f43b8223483aar
To give a large measure of flexibility to the applica-tion in terms of power
consumption, five main pow-er saving modes are implemented in the ST7 (seeFigure 21):
■Slow
■Wait (and Slow-Wait)■Active Halt
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■Auto Wake up From Halt (AWUFH)■Halt
After a RESET the normal operating mode is se-lected by default (RUN mode). This mode
drivesthe device (CPU and embedded peripherals) bymeans of a master clock which is
based on themain oscillator frequency divided or multiplied by 2(fOSC2).
From RUN mode, the different power savingmodes may be selected by setting the
relevantregister bits or by calling the specific ST7 softwareinstruction whose action
depends on the oscillatorstatus.
Figure 21. Power Saving Mode Transitions
9.2 SLOW MODE
This mode has two targets:
– To reduce power consumption by decreasing the internal clock in the device,
– To adapt the inhttp://www.wendangwang.com/doc/2c8a46421bc4f43b8223483aternal
clock frequency (fCPU) to the available supply voltage.
SLOW mode is controlled by the SMS bit in theMCCSR register which enables or disables
Slowmode.
In this mode, the oscillator frequency is divided by32. The CPU and peripherals are
clocked at this-lower frequency.
Note: SLOW-WAIT mode is activated when enter-ing WAIT mode while the device is already
inSLOW mode.
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Figure 22. SLOW Mode Clock Transition
ST7LITE3xF2
POWER SAVING MODES (Cont’d)9.3 WAIT MODE
WAIT mode places the MCU in a low power con-sumption mode by stopping the CPU.
This power saving mode is selected by calling the‘WFI’ instruction.
All peripherals remain active. During WAIT mode,the I bit of the CC register is cleared,
to enable allinterrupts. All other registers and memory remainunchanged. The MCU
remains in WAIT mode untilan interrupt or RESET occurs, whereupon the Pro-gram
Chttp://www.wendangwang.com/doc/2c8a46421bc4f43b8223483aounter branches to the
starting address ofthe interrupt or Reset service routine.
The MCU will remain in WAIT mode until a Resetor an Interrupt occurs, causing it to
wake up.Refer to Figure 23.
Figure 23. WAIT Mode Flow-chart
OSCILLATOR PERIPHERALSCPUIBIT
ONONOFF0
WFIINSTRUCTION
N
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RESETY
N
INTERRUPTY
OSCILLATOR PERIPHERALSCPUIBIT
ONOFFON0
256 OR 4096CPUCLOCK
CYCLE DELAYOSCILLATOR PERIPHERALSCPUIBIT
ONONONX1)
FETCHRESETVECTORORSERVICEINTERRUPT
Note:
1. Before servicing an interrupt, the CC register ispushed on the stack. The I bit
of the CC register isset during the interrupt routine and cleared whenthe CC register
is popped.
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