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CS 401 Computer Architecture and Assembly Language
Assignment # 05
Deadline
Your assignment must be uploaded / submitted before or on January 07, 2008.
Upload Instructions
Please view the assignment submission process document provided to you by the Virtual
University to upload the assignment.
Rules for Marking
Please note that your assignment will not be graded if:
 It is submitted after due date
 The file you uploaded does not open
 The file you uploaded is copied from some one else
 It dose note contain the com file to run on dos prompt directly.
Objective
The assignment has been designed to enable you:


To know about interrupts handling.
To increase the interrupts knowledge in assembly language by searching the
different short questions.
Q #1. (10 Marks)
Give answers to each.
a. How can we hook an interrupt?
b. How the address of a required interrupt handler is found?
c. What is difference between maskable and non-maskable interrupts?
d. Briefly explain the context switching with example.
e. When an IRET instruction is executed, what action takes place?
Solution:
a. To hook an interrupt we change the vector corresponding to that interrupt.
As soon as the interrupt vector changes, that interrupt will be routed to the
new handler. So introducing a new entry in the mapping table is called
hooking an interrupt.
b. The correlation process from the interrupt number to the interrupt handler
uses a table called interrupt vector table. Its location is fixed to physical
memory address zero. Each entry of the table is four bytes long containing
the segment and offset of the interrupt routine for the corresponding
interrupt number. The first two bytes in the entry contain the offset and the
next two bytes contain the segment. Mathematically offset of the interrupt n
will be at nx4 while the segment will be at nx4+2. One entry in this table is
called a vector.
c. The processor can inhibit certain types of interrupts by use of a special
interrupt mask bit. This mask bit is part of the condition code register, or a
special interrupt register. If this bit is set, and an interrupt request occurs on
the interrupt request input, it is ignored. There are some interrupts which
cannot be masked out or ignored by the processor. These are associated
with high priority tasks which cannot be ignored (like memory parity or bus
faults). In general, most processors support the Non-Maskable Interrupt
(NMI). This interrupt has absolute priority, and when it occurs, the
processor will finish the current memory cycle, and then branch to a special
routine written to handle the interrupt request.
d. A context switching involves storing the old state and retrieving the new
state. When the interrupt instruction is called, the values of CS, IP and Flags
are stored on the stack and these values are restored at the end of servicing
the current interrupt.
e. The values of CS, IP and Flags are popped from stack.