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Effects of Parasitic Components in High-Frequency Resonant Drivers for Synchronous Rectification MOSFETs Speaker: Giorgio Spiazzi Department of Information Engineering – DEI University of Padova, ITALY 1 Outline • Review of voltage source driver topology • Analysis of resonant voltage source driver topologies – Unclamped turn-on and clamped turn-off – Clamped turn-on and clamped turn-off – Unclamped turn-on and unclamped turn-off • Analysis of parasitic component effects 2 Voltage Source Topology Dissipative driver +Vdd Ron i(t) S1 Rch + M Vgon vC(t) + C S2 Ron = RDSon(S1)+Rch+Rg v C t VCoff t R C Vgon VCoff 1 e on 3 Resonant Driver DR1 Unclamped turn-on and clamped turn-off S1 Db1 Lext + Vdd M Db2 S2 Vo Dc1 + Possible energy recovery to output in VRM applications 4 Resonant Driver DR1 Unclamped turn-on and clamped turn-off S1 Db1 + Vdd Lext Db2 i(t) Dc1 S 2 Vo VCon Ipk_p vC(t) i(t) M Toff + VCoff Ton vC + tfu tri t ig(t) I1 - Ipk_n 5 Resonant Driver DR1 Turn-on phase RDSon Lint +VDb RLp Lext Rg + Vdd S1 M Db1 VCon Ipk_p vC(t) i(t) C Toff VCoff Ton Ron + Vgon tri t ig(t) L i(t) + vC(t) tfu I1 Ipk_n C Resonant circuit parameters Qon Z o R on L Zo C R on o 2L 2Qon o 1 1 2 4Q on 6 Resonant Driver DR1 Inductor current and capacitor voltage Vg VCo it Zo 1 1 2 4Q on e t sin t v C t Vg If Qon>>1: i t Vg VCo Zo e o t 2 Qon Vg VCo 2Q on 1 1 2 4Q on t 1 e sin t 2Q on 1 2 cost 4Q on sin o t v C t Vg Vg VCo e Final capacitor voltage vC Ton VCon Vgon Vgon VCoff e o t 2 Qon 1 sin o t coso t 2Q on 2 Qon 7 Unclamped Resonance Normalized capacitor voltage and inductor current as a function of ot for different Q values (vC(0) = 0, VN = Vgon, IN = Vgon/Zo) Ton 1 Q = 1000 2 Q = 10 [IN] Q=5 0.8 Q=2 Q=1 0.6 [VN] 1.6 1.2 Q = 0.5 0.4 Ton 0.2 0 0 3 2 3 0.8 o 4 3 0.4 5 3 0 2 8 Unclamped Resonance Ideal performance comparison between a voltage source and an unclamped resonant drivers 2 1 [h] 0.8 [VN] Pres 1.8 PNONres 0.6 Normalized final 1.6 capacitor voltage 0.4 1.4 0.2 1.2 0 0.1 0.5 1 Q 10 1 100 9 Unclamped Resonance • High Q means high L, that means lower resonant frequency, i.e. higher turn on interval • Minimum loss resistance is the SR gate internal resistance Rg Ton LC Tsw o Q on L Tsw 2 L Tsw Zo C C 2C Zo Qd R on For a voltage source topology: R on R on Tsw Qd C Tsw 1 C ln 1 k VCon k Vgon 10 Maximum Ron = 0.05, k = 0.8, Ron_min = 1W, C = 10nF 100 100 100 Ron [W] 10 10 Voltage source topology R v( f ) R r( f 4) Q = 0.5 Ron_min 11 R r( f 2) Q=1 R r( f 1) Q=4 0.1 0.1 0.01 0.08 0.01 Unclamped resonance topology Q=2 00 0.01 0.5 0.5 11 1.5 1.5 22 2.5 2.5 f 33 3.5 3.5 44 4.5 4.5 55 5 fsw [MHz] 11 Resonant Driver DR1 Turn-off phase Roff + L i(t) Vgoff + vC(t) C VCon Ipk_p vC(t) i(t) Toff VCoff Ton Roff-Rg + L Vgoff VDc + tri t ig(t) Rg I1 ig(t) i(t) tfu + C vC(t) Ipk_n 12 DR1 Characteristics • both switches S1 and S2 turn on and off at zero current; • the control signals of S1 and S2 have no critical timing, the only requirement being to avoid any cross conduction; • the switching times of S1 and S2 have no influence in the circuit behavior; • S1 and S2 body diodes are not used (they have high voltage drop and bad reverse recovery behavior); • switch lead inductances as well as any parasitic inductance due to traces and layout simply add to the external inductance (they are actually exploited by the circuit); • different Ton and Toff times can be easily achieved; • Toff interval duration as well as the amount of recovered energy depends on Vo value (disadvantage); • S2 command signal must be suitably higher than Vo to completely turn it on (disadvantage). • No low impedance paths during on and off intervals 13 Resonant Driver DR2 Clamped turn-on and clamped turn-off Ipk_p +Vdd VCon I2 I3 i(t) Dc2 S1 vC(t) ig(t) Lext M S2 Toff VCoff tru Dc1 tfw tfi tfu tfw t tri Ton Ipk_n Dc1 and Dc2 can be substituted by MOSFETs, thus ensuring a low impedance path to Vdd an to ground during on-time and off-time 14 Resonant Driver DR2 Ron L + i(t) + vC(t) Vgon + Ron-Rg Vdd VDc L+ Turn-on phase C Ipk_p VCon Rg I2 I3 i(t) ig(t) ig(t) i(t) + C vC(t) vC(t) Toff VCoff tru tfw tfi tfu tfw tri t Ton + RLp Vdd VD2 i(t) + VDc L+ Ipk_n Rg ig(t) + C vC(t) 15 DR2 Characteristics • both S1 and S2 switches turn on at zero current, but they turn off almost at the inductor peak current; • the control signals of S1 and S2 have critical timing, having to minimize the freewheeling intervals tfw, in order not to adversely affect the overall efficiency; • the switching times of S1 and S2 have a great influence on the circuit behavior, causing a significant power loss at turn off (see point 1) as well as increase of Ton and Toff intervals; • S1 and S2 body diodes are involved during the recovery of the inductor energy; • switch lead inductances as well as any parasitic inductance due to traces and layout have a great impact on the circuit behavior, since they cause high frequency parasitic oscillations at turn off and delay S1 and S2 turn off times; • VCon value is easily controlled by the supply voltage Vdd (advantage) 16 Resonant Driver DR3 +Vdd Unclamped turn-on and unclamped turn-off VCon Ipk_p S1 Db1 Lext vC(t) i(t) M Toff Db2 t Ton S2 VCoff Ipk_n VCon Vgon 1 e 2Qon V e 2Qon 1 e 2Qoff goff 1 e 1 1 2 Qon Qoff VCoff Vgoff 1 e 2Qoff V e 2Qoff 1 e 2Qon gon 1 e 1 1 2 Qon Qoff 17 DR3 Characteristics Same considerations as DR1. Moreover: • high VCon values can be achieved with very low supply voltage Vdd; • Vdd value must be higher than the threshold voltage of S1 (p-channel MOSFET) in order to fully turn it on; • the driver needs some oscillating cycles in order to achieve a steady state operation 18 Losses Comparison Driver parameters: • • • • • • • • • • S1,2 = IRF7319 Db1,2, Dcl, and Dc1,2 = STPS1L40U Switching frequency: fsw = 1.8MHz Maximum diode voltage drop: VDc = VDb = 0.63V External inductance parasitic resistance: RLp = 200mW External inductance: Lext = 30nH (DR1), Lext = 35nH (DR2), Lext = 30nH (DR3) Internal gate resistance: Rg = 0.25W Equivalent gate capacitance: C = 10nF Supply voltage: Vdd = 5V (DR1), Vdd = 6.8V (DR2), Vdd = 3.85V (DR3) VRM output voltage for DR1: Vo = 1.3V 19 Losses Comparison: calculations MOSFET S1 and S2 parameters RDS(on) [W] IRF 7319 VD [V] LSint LDint [nH] [nH] Tsw_off [ns] Qg@ VGS=5V Qg@ VGS=7V [nC] [nC] 17 p-MOS 0.098 1 4 6 32 13 n-MOS 0.046 1 4 6 17 12.5 16.5 Details of Losses Calculation for DR1 (VCon = 7.41V, Lext = 30nH, Vdd = 5V, Vo = 1.3V) Turn on Pdd [mW] PDb1,2 [mW] 724 91 PDcl [mW] PR [mW] Po [mW] 142 PLoss [mW] Ton, Toff [ns] Ipk [A] 233 55 2.28 PTot_loss [mW] 502 Turn off 103 13 153 212 269 58.3 -2.55 20 Losses Comparison Details of Losses Calculation for DR2 (VCon = 7.43V, Lext = 35nH, Vdd = 6.8V) Turn on Turn off Pdd [mW] Pdd_recovered [mW] PD1,2 [mW] PDcl ,2 [mW] PR [mW] PLoss [mW] Ton, Toff [ns] Ipk [A] 967 179 22 51 241 295 56.1 3.2 199 29 36 215 280 50.5 -3.25 PTot_loss [mW] 574 Details of Losses Calculation for DR3 (VCon = 7.44V, VCoff = -3.71V, Lext = 30nH, Vdd = 3.85V) Turn on Turn off Pdd [mW] PDb1,2 [mW] PR [mW] PLoss [mW] Ton, Toff [ns] Ipk [A] 772 126 272 399 54.4 3.16 126 242 374 54.4 -3.17 PTot_loss [mW] 773 21 Losses Comparison Driver DR2 losses do not include S1 and S2 switching losses: at turn-on: Psw_on = 220mW at turn-off: Psw_off = 135mW Total DR1 losses: Ptot_loss = 502mW Total DR2 losses: Ptot_loss = 574+355 = 929mW Total DR3 losses: Ptot_loss = 773mW 22 Experimental Waveforms: DR1 With Lext Dcl1 Rs + C VC VRs + CLoad = 10nF (smd), Rs = 0.1W, Ualim = 5V, fsw = 1.8MHz vC [2V/div] vRs [100mV/div] vG_p-MOS [1V/div] VGS_n-MOS [1V/div] vDS_n-MOS [2V/div] 23 Experimental Waveforms: DR1 Without Lext Dcl1 Rs + C VC VRs + CLoad = 10nF (smd), Rs = 0.1W, Ualim = 5V, fsw = 1.8MHz vC [2V/div] vRs [200mV/div] vG_p-MOS [1V/div] VGS_n-MOS [1V/div] vDS_n-MOS [2V/div] 24 Experimental Waveforms: DR2 With Lext CLoad = 10nF (smd), Rs = 0.1W, Ualim = 7.5V, fsw = 1.8MHz TpNMOS = 58.4ns, TpPMOS = 58.4ns (misurati a 1V) vC [2V/div] vRs [100mV/div] vG_p-MOS [2V/div] VGS_n-MOS [2V/div] vDS_n-MOS [2V/div] 25 Experimental Waveforms: DR2 Without Lext CLoad = 10nF (smd), Rs = 0.1W, Ualim = 7.5V, fsw = 1.8MHz TpNMOS = 58.4ns, TpPMOS = 58.4ns (misurati a 1V) vC [2V/div] vRs [200mV/div] vG_p-MOS [2V/div] VGS_n-MOS [2V/div] vDS_n-MOS [2V/div] 26 Experimental Waveforms: DR3 With Lext CLoad = 10nF (smd), Rs = 0.1W, Ualim = 4V, fsw = 1.8MHz vC [2V/div] vRs [100mV/div] vG_p-MOS [1V/div] VGS_n-MOS [1V/div] vDS_n-MOS [2V/div] 27 Experimental Waveforms: DR3 Without Lext CLoad = 10nF (smd), Rs = 0.1W, Ualim = 4V, fsw = 1.8MHz vC [2V/div] vRs [200mV/div] vG_p-MOS [1V/div] VGS_n-MOS [1V/div] vDS_n-MOS [2V/div] 28 Effect of Device Parasitic Capacitances The final capacitor voltage during turn on is lower than expected, especially for driver DR2. Why? + Effect of device’s output capacitances [V,A] + vCp VCon 6 4 vC 4 2 VCoff 0 0 -2 -2 -4 Ton_sw = 90ns Time -4 + vC i(t) C vDS_n-MOS 8 VCon_nominal iL Cp [V,A] 6 2 Lext Vdd vDS_n-MOS 8 RLp VCon vC iL VCoff Ton_sw = 150ns X axis scale = 50ns/div Time 29 Effect of Device Parasitic Capacitances DR2 Measurements: Vdd = 7V, fsw = 1.8MHz, Lext = 0 vc(t) [2V/div] Tsw-cond = 90ns Tsw-cond = 60ns Time [100ns/div] 30 Effect of Device Parasitic Capacitances DR2: Effect of Switch Conduction Time on VCon and VCoff (Vdd = 7V, Rs = 0) VCon VCoff Tsw_cond [V] [V] [ns] 0.5901 5.93 1.5 64 0.63 0.068 With 0.6482 5.86 1.28 90 0.62 -0.049 Lext 0.7049 6.14 1.23 99 0.68 -0.039 0.7791 6.42 1.17 140 0.74 -0.050 1.0878 6.94 -0.22 140 0.878 -0.255 1.0689 6.8 -0.22 120 0.83 -0.284 1.0437 6.94 0.14 107 0.87 -0.204 0.9408 6.6 0.22 90 0.78 -0.2 0.6965 5.86 1 60 0.62 -0.127 Pdd [mW] Without Lext Pnom [W] 2 Pnom CVCon f sw Pnom Pdd Pnom 31 DR1 Power Losses at Different Vdd (Rs = 0, Vo = 0) With Lext Without Lext Vdd VCpeak VCon Pdd Pnom [V] [V] [V] [mW] [W] 3 4.19 3.95 0.264 0.281 0.061 3.5 5.23 4.9 0.375 0.432 0.133 4 6.1 5.72 0.496 0.589 0.158 4.5 6.95 6.5 0.635 0.761 0.166 5 7.8 7.34 0.792 0.970 0.184 3 3 2.9 0.197 0.151 -0.298 3.5 4 3.84 0.285 0.265 -0.075 4 4.93 4.72 0.404 0.401 -0.006 4.5 5.88 5.58 0.545 0.560 0.027 5 6.68 6.42 0.698 0.742 0.059 32 DR2 Power Losses at Different Vdd (Rs = 0, Tsw-cond = 58.4ns) Vdd VCpeak VCon Pdd Pnom [V] [V] [V] [mW] [W] 5 5.62 4.09 0.310 0.301 -0.030 5.5 6.5 4.71 0.384 0.399 0.037 6 7.24 5.22 0.449 0.490 0.084 6.5 7.8 5.54 0.519 0.552 0.060 7 8.34 6 0.594 0.648 0.084 7.5 9.02 6.38 0.683 0.733 0.068 5 6.78 4.4 0.372 0.348 -0.067 5.5 7.56 4.66 0.433 0.391 -0.109 Without 6 8.28 5.04 0.505 0.457 -0.104 Lext 6.5 9 5.4 0.588 0.525 -0.121 7 9.58 5.78 0.683 0.601 -0.136 7.5 10.22 6.16 0.779 0.683 -0.141 With Lext 33 DR3 Power Losses at Different Vdd (Rs = 0) With Lext Without Lext Vdd VCon VCoff Pdd Pnom [V] [V] [V] [mW] [W] 3 3.99 -1.9 0.363 0.287 -0.268 3.5 5.78 -2.88 0.609 0.601 -0.013 3.75 6.5 -3.32 0.744 0.761 0.021 4 7.1 -3.74 0.880 0.907 0.030 4.25 7.8 -4.11 1.037 1.095 0.053 4.5 8.42 -4.54 1.197 1.276 0.062 5 9.63 -5.16 1.589 1.669 0.048 3 2.91 -1.02 0.255 0.152 -0.675 3.5 3.74 -1.31 0.373 0.252 -0.480 4 4.71 -1.78 0.542 0.399 -0.356 4.5 5.9 -2.26 0.752 0.627 -0.201 5 6.94 1.011 0.867 -0.166 -2.7 34 Internal MOSFET Inductance • For the same Vdd value, the final VCon voltage without the external inductor Lext in DR1 and DR3 (and, to a less extent, also in DR2) is much lower than the corresponding value with Lext, and this phenomenon is more pronounced at lower Vdd values • This result can be explained only by a lower Qon factor of the circuit without Lext, i.e. a higher RDSon of the p-channel MOSFET S1 caused by a reduced gate-to-source voltage due to the voltage drop across the internal source inductance (4nH for the IRF7319) that becomes worse at higher di/dt values, i.e. without Lext. This explains why the observed phenomenon is more pronounced at lower Vdd values, and justify why DR1, that requires a higher Vdd than DR3 to achieve the same VCon value, has lower overall losses than DR3 even without energy recovery. 35 Resonant VRM VGS_Q1 Q1 C1 CA HB1 LR LF1 TR iF1 + VIN CB VC1 + CF VO iR HB2 + N:1 LF2 iF2 RL + VC2 C2 Q2 VGS_Q2 • Square-wave operation of the primary half-bridge • Zero-voltage and zero-current commutations of SR MOSFETs Q1 and Q2 • Operation at fs = 1.8MHz, VIN = 48V, Vo = 1.3V, Io = 50A • Resonant drivers for SRs 36 VRM Prototype 4 IRF7836 SR MOSFETs (Qg = 18-27nC @VGS = 4.5V, Rg = 1W) 37 Experimental Waveforms: DR1 DR1 measured waveforms driving 4 IRF7836 SR MOSFETs (no energy recovery) Ploss = 1W each HB1 HB2 VGS1 [2V/div] VGS2 [2V/div] 38 References 1. D. Maksimovic, “A MOS gate drive with resonant transitions,” in Proc. Power Electron. Spec. Conf., 1991, pp. 527–532. 2. Y. Ren, M. Xu, Y. Meng, F. C. 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