Download top plate. It is not - SMDP-VLSI

BASIC BLOCKS :
PASSIVE COMPONENTS
1
PASSIVE COMPONENTS:
• Capacitors
 Junction Capacitors
 Inversion Capacitors
 Parallel Plate Capacitors
•
Resistors
 Poly Resistors
 Diffused Resistors
 Switched capacitors as resistors
 Active Load
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CAPACITORS
The desired characteristics for capacitors
used are given below:
· Good matching accuracy
· Low voltage-coefficient
· High ratio of desired capacitance to
Parasitic capacitance
· High capacitance per unit area
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Poly- SiO2 – Channel Capacitance
This structure uses the Gate to Source and gate to
Drain Capacitances to realise the required
Capacitances. This capacitance achieves a large
capacitance per unit area and good matching but
suffers from high voltage dependent parasitic
capacitance to ground.
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Poly – SiO2 – Poly Capacitor
This is one of the best configurations for
high performance capacitors.
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MOS Accumulation Capacitor
This has a high capacitance per unit area
and used where grounded capacitors re
required.
6
Capacitors realized using various inter connect layers
This gives the method to obtain capacitors by
appropriate choice of plates and connection between
various metal and Poly Si layers available. It should
be mentioned that each interconnect layer is
insulated from the others by a SiO2 layer. Of the
various structure shown, the four layer structure
has the least parasitic capacitance.
7
As processes migrate toward finer line widths and higher
speed performance, the oxide between metals increases while
the allowed space between metals decreases. For such
processes, samelayer, horizontal, capacitors can be more
efficient than different-layer vertical capacitors. This is due
to the fact that the allowed space between two M1 lines, for
example, is less than the vertical space between M1 and M2.
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The capacitor plate with the smallest parasitic
associated with it is referred to as the top plate.
It is not necessarily physically the top plate
although quite often it is. In contrast, the bottom
plate is that plate having the larger parasitic
capacitance associated with it. Schematically, the
top plate is represented by the flat plate in the
capacitor symbol while the curved plate
represents the bottom plate.
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10
While designing for matched capcitors or ratioed
capacitors, a technique of common centroid lay out is
used. The concept is best illustrated with an example.
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VICINITY EFFECTS
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RESISTORS
The diffused resistor is normally formed with
source/drain diffusion. The sheet resistance of such
resistors are normally in the range of 50 to 100/
for non salicide process and about 5-15/ for
sallicide processes. These resistance have a voltage
dependence in the range of 100-500 ppm/V range and
also a high parasitic capacitance to ground.
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The poly Si resistor has a sheet resistance in the
range of 30-200 / depending on the doping of
the poly Si layer. For a polysilicide process the
resistance is about 10/.
15
The n-well resistance has a resistance of 1-10K/
along with a high voltage sensitivity. In cases where
accuracy is of no concern this structure is very
useful.
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ACTIVE (ac) RESISTORS
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19
SWITCHED CAPACITOR RESISTOR
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AMPLIFIERS
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SMALL SIGNAL PARAMETERS
IDS 
k W
VGS  VTH 2 1  n VDS 
2 L
ids  gm vgs  gds vds  gmb vsb where gm 
gm 
IDS
VGS
and gds 
 k'
IDS
VGS
, gds 
IDS
VDS
, and gmb 
IDS
VBS
W
VGS  VTH  2k' W IDS
L
L
IDS
VDS

k' W
VGS  VTH 2 n  n IDS  1
2 L
rds
gmbs 
gm 
2 2 F  VBS
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COMMON SOURCE AMPLIFIERS
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25
gm = gm1 and RL = R ||l rds1 for Resistance load
amplifier
gm = gm1 and RL = rds1 ||l rds2 ||l 1/gm2 for Active load
amplifier
gm = gm1 and RL = rds1 ||l rds2 for Current source load
amplifier and
gm = gm1 + gm2 and RL = rds1 ||l rds2 for Push Pull
Amplifier.
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Ain = gm1 (R ||l rds1) for Resistance load amplifier
Ain = gm1 (rds1 ||l rds2 ||l 1/gm2) = for Active load
amplifier.
Ain = gm1 (rds1 ||l rds2) = for Current source load
amplifier
Ain = (gm1 + gm2) (rds1 ||l rds2) = for Push Pull amplifier.
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The capacitor at the input CIN = CGS1 for Active Load
and Current Source Load Amplifier and CIN = CGS1 +
CGS2 for the Push Pull amplifier. The bridging capacitor
C = CGD1 for Active Load and Current Source Load
Amplifier and C = CGD1 + CGD2 for the Push Pull
amplifier. The capacitor at the output CL = CLoad + CGS2
+ CBD1 + CBD2 for the Active Load amplifier and is CL =
CLoad + CBD1 + CBD2 for the Current Source Load and
Push Pull Amplifiers.
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vout  gm RL 1 1  s / z 
Ain 

s  1 
vin
A
g
vout  gm RL 1 2 1  s / z 
1
1

where 1 
z  m and 2 
s  1 s  2 
RS CM 
vs
RL CL
C
CM is the Miller Capacitance seen at the input.
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COMMON DRAIN AMPLIFIER
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31
rout 


A
1
for current source load
gm1  gmbs1  gds1  gds2 
1
for active load
gm1  gmbs1  gds1  gm2  gds2 
1
for push pull configurat ion
gm1  gmbs1  gds1  gm2  gmbs2  gds2 
gm1
vout

for current source load
vin gm1  gmbs1  gds1  gds2 


gm1
for active load
gm1  gmbs1  gds1  gm2  gds2 
gm1
for push pull configurat ion
gm1  gmbs1  gds1  gm2  gmbs2  gds2 
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COMMON GATE AMPLIFIER
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vout 1  gm1  gmb1 rds1 RL gm1 rds1 RL
Ain 


for gm1  gmb & gm1 rds1  1
rds1  RL 
rds1  RL 
vin
A
gm1  gmb1 rds1  1RL 
vout

vs rds1  gm1  gmb1 rds1 RS  RS  RL 

RL 
1


rin  RS 
1

gm1  gmbs1   rds1 
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CASCODE AMPLIFIER
C1 = Cgd1, C2 = Cdb1 + Csb2 + Cgs1, C3 = Cgd2
+ Cdb3 + Cdb2 + Cgd3 and 2 = gmbs2/gm2.
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


v 
1

CM  Cgd1  1  1   Cgd1 1  gm1 rin2   Cgd1  1  gm1
1  RL2 gds 2 

vin 
gm2




gds 2  
1 


   3 Cgd1
 Cgd1 1  gm1
1


gm2  gds 3  

Since in the presence of a signal source with a source
impedance RS, the pole contributed by the Miller
Capacitance seen by the Cascode amplifier will be
farther than the Common Source Amplifier with nearly
the same gain and input and output impedances.
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In cascode amplifier we have used a simple current
source load. However, to obtain a larger gain we can
use a cascade of current mirror load. It should be
mentioned here that a single current source is
represented as a single transistor with a bias while
we have represented a cascade current source with
two transistors in series with appropriate gate bias.
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TELESCOPIC CASCODE AMPLIFIER
2
1  gm3 rds 3 
1 

rin2 

gm2  
rds 2 
v1
A1   gm1
vin
1
 1

gm1


 r  gds1   2 g
 in2

ds
gm2 ≈ gm3, gds2 = gds3 = gds1 = gds5
GL 
gds 3 gds 4 gds 2 gds1

gm3
gm2
A2 
g
vout
1 1

 ds
v1 rin' 2 GL
GL
gm1 1
vout v1 vout
A

 A1 A2 
vin vin v1
2 GL
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FOLDED CASCODE AMPLIFIER
2
1  gm3 rds 3 
1 

rin2 

gm2  
rds 2 
v1
A1   gm1
vin
||l 1/gds5
1
 1

gm1


 r  gds1   2 g
 in2

ds
gds 3 gds 4 gds 2 gds1  gds 5 
GL 

gm3
gm2
A2 
A
vout 1 1
g
 '
 ds
v1 rin2 GL GL
g
vout v1 vout
1

 A1 A2  m1
vin vin v1
2 GL
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