Download Lect wk 8-10 Latches FF State Machines

EE2004 Digital Electronics
Dr Gwee Bah Hwee
Associate Professor
School of Electrical and Electronic Engineering
Office: S1-B1b-42
Phone: 6790-6861
Email: [email protected]
1
EE4305 Digital Design with VHDL,
by Dr. Yu Yajun
Topics



Latches & flip-flops
Synchronous state machine analysis
Synchronous state machine design
2
Combinational and sequential circuits
Two types of Digital Circuits:
Combinational Circuits: output(s) depend only on
present value of inputs and not on past values. Therefore,
output is strictly a function of the inputs.
Examples - Random Logic and Array Logic. Circuits
formed by SOP or POS are Random Logic. The PLD
devices, PLAs and PALs, are Array Logic. Adders are
another example of combinational circuits.
3
Sequential Circuits
Outputs depend on both present and past input values.
Past input values determine present state of circuit.
To remember the present state, the sequential circuit must
have some form of ‘memory’.
Output
Input
Combinational
Logic
Memory
Element
Block Diagram of Sequential Circuits
4
Storage Elements
A storage element can maintain a binary state
indefinitely (as long as power is delivered to the circuit),
until it is directed by an input signal to switch states.
• Latch: a memory element whose excitation input signals
control the state of the device. The state of the device
can be read at the output of the element. Any change to
output can only be initiated by the input.
• Flip-flop: differs from a latch in that it has a control
signal called a clock. The clock controls the state of the
device. Any change to output can only be initiated by
the clock.
5
What is a clock signal?
 Specifications: period (tper), frequency (1/tper), duty
cycle (tH/tper)
6
Simple Latches (1)
No input
Output
♥ Output depends on feedback voltage only
♥ When feedback applies onto the input of inverter, after a
short time (propagation delay), it appears inverted on the
output
♥ The new state of voltage which feeds back to the input
causes a similar inversion
♥ The output voltage oscillates
7
Simple Latches (2): Bi-stable Elements
No input
Output
♥ When powered on, outputs of each inverter will go
through a period of instability
♥ One output settle to a high level & the other to a low
level
♥ No way to predict the output status
♥ Circuit exhibits a primitive form of “memory”, it
remembers the resolution of the initial voltage applied on
the inputs of the inverters
8
Compare with
9
Simple Latches (3):
Feedback Circuits with External Inputs
Feedback circuits with external inputs allow
designer to control the value stored in the
memory.
External
inputs
Y
Feedback path
10
Basic Binary Cell
Binary cell is the basic building block of memory, it
is used to store a single bit of information.
SET condition
stores a ‘1’
RESET condition
stores a ‘0’
REST condition
unchanged
information
Two types of basic binary cells:
• Cross-coupled NOR gate cell
• Cross-coupled NAND gate cell
11
Cross-Coupled NOR Gate Cell
S (set)
R (reset)
Q’
Q
12
States of the cross-coupled NOR gate
a. Set state (set condition)
When “S input” asserted (1) and “R input” not asserted
(0), then Q output is asserted = 1 and Q’ = 0
∴ binary cell is loaded with a binary bit “1” (i.e., SET).
If the “S input” is de-asserted thereafter, the cell
condition does not changed.
b. Reset state (reset condition)
When “S input” is not asserted (0), and “R input”
asserted (1), then Q output is not asserted = 0 and Q’ =
1.
∴ binary cell is loaded with a binary bit “0” (i.e., RESET)
If the “R input” is de-asserted thereafter, the cell
condition does not changed.
13
c. Resting state (resting condition)
When both “S and R inputs” are not asserted (0,
0), then Q and Q’ are unchanged
d. State which is not allowed
When both “S and R inputs” are asserted
simultaneously (1, 1), then both Q and Q’ are
changed from high to low voltage. This is
contrary in logic, as Q and Q’ are complementary
outputs
When both inputs are released simultaneously,
the cell will go to an indeterminate state due to
the race between Q and Q’.
14
Symbol and truth table of Cross-Coupled NOR Gate
S
Q
Q’
R
S (set)
R (reset)
1
0
1
0
Set state
0
0
1
0
Rest
0
1
0
1
Reset state
0
0
0
1
Rest
1
1
0
0
Not allowed
Q Q’
15
Cross-Coupled NAND Gate Cell
S (set)
Q
R (reset)
Q’
16
States of the cross-coupled NAND gate
a. Set state (set condition)
When “S input” asserted (0) and “R input” not asserted
(1), then Q output is asserted = 1 and Q’ = 0
∴ binary cell is loaded with a binary bit “1” (i.e., SET).
If the “S input” is de-asserted thereafter, the cell
condition does not changed.
b. Reset state (reset condition)
When “S input” is not asserted (1), and “R input”
asserted (0), then Q output is not asserted = 0 and Q’ =
1.
∴ binary cell is loaded with a binary bit “0” (i.e., RESET)
If the “R input” is de-asserted thereafter, the cell
condition does not changed.
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c. Resting state (resting condition)
When both “S and R inputs” are not asserted (1,
1), then Q and Q’ are unchanged
d. State which is not allowed
When both “S and R inputs” are asserted
simultaneously (0, 0), then both Q and Q’ are
changed from low to high voltage. This is
contrary in logic, as Q and Q’ are complementary
outputs
When both inputs are released simultaneously,
the cell will go to an indeterminate state due to
the race between Q and Q’.
18
Symbol and truth table of Cross-Coupled NAND Gate
S
Q
Q’
R
S (set)
R (reset)
Q
Q’
0
1
1
0
Set state
1
1
1
0
Rest
1
0
0
1
Reset state
1
1
0
1
Rest
0
0
1
1
Not allowed
19
Timing Representation of SR Latch
Ideal (zero-gate-delay) Set-Reset latch timing diagram
20
Timing Representation of SR Latch
Actual timing with non-zero gate delays.
In reality, every circuit output requires a nonzero
amount of time to respond to changes on its inputs.
21
Delay Parameters
tPLH - delay time between an input change and a
corresponding low-to-high output transition.
tPHL - delay time between an input change and a
corresponding high-to-low output transition
tPLH and tPHL represent the sum of the propagation delays
through the gates between a given latch input and output,
with separate delay parameters usually specified for each
input/output pair.
22
Propagation Delays of SR Latch
S
N1
Q’
Q’
N1
N2
S
N2
Q
R
S
Q
R
tPLH
(S to Q)
tPHL (R to Q)
R
tPLH
(N2)
Q
tPHL
(N2)
Q’
tPHL
(N1)
tPLH
(N1)
23
Timing Behavior of SR Latch
When S changes from 0→1, Q’ changes from 1→0 after the
propagation delay tPHL through NOR gate N1.
Then, the feedback signal causes Q to change from 0→1 after
tPLH through gate N2.
Thus, Q’ always changes before Q when setting a SR latch built
from cross-coupled NOR gates.
∴ tPHL from input S to output Q’ of the latch involves a single
gate delay, whereas tPLH from input S to output Q includes two
gate delays.
A similar behavior exists between input R and the two outputs.
When resetting, reset pulse on the input R, output Q changes
before output Q’.
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Summary of Basic Latch
The memory element in the sequential circuit model can be
realized by special hardware that includes a binary cell
(basic latch) to store the Preset State of the circuit.
Basically, a latch is a memory device that can assume one
of two stable output states, has a pair of complementary
outputs, and has one or more inputs that can cause the
output state to change.
The basic latch as it stands is an asynchronous sequential
circuit.
25
Clocked Latch or Flip-Flop
It is a common practice to synchronize the operation of
all latches by a common clock or pulse generator in
synchronous sequential circuit.
By adding some combinational circuits to the inputs of
the basic latch, the latch can be made to respond to
input levels during the occurrence of a clock pulse.
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Clocked Set/Reset (SR Flip-Flop)
Set
1
0
Reset
Cross
coupled
NAND gate
cell
Clk
S
R
Next state of Q
0
X
X
No change
1
0
0
No change
1
0
1
Q=0, reset state
1
1
0
Q=1, set state
1
1
1
In-determined
27
Characteristic Table
• A Truth-Table for specifying the operational
characteristic of the clocked flip-flop.
S
0
0
0
0
1
1
1
1
R
0
0
1
1
0
0
1
1
Qt
0
1
0
1
0
1
0
1
Qt+1
Rest
Mode
Reset
Mode
Set
Mode
Not
Allowed
28
Characteristic Equation
The characteristic equation of the flip-flop specifies
the value of the next state as a function of the
present state and the inputs.
S
R
Qt
Qt+1
0
0
0
0
0
0
1
1
0
1
0
0
0
1
1
0
1
0
0
1
1
0
1
1
1
1
0
X
1
1
1
X
Qt\ S R 00
0
0
1
1
01
11
10
0
0
X
X
1
1
Qt+1= R’Qt + S
29
Excitation Table
The excitation table is an important design aid
derived from the characteristic table. It provides the
desired inputs to produce a specific output
transition.
Qt
→ Qt+1
0
→ 0
0
1
→ 1
→ 0
1
→ 1
S
R
30
Typical operation of an
SR Flip-Flop
31
Delay-latch (or D Flip-Flop)
Set
Cross
coupled
NAND gate
cell
1
0
Reset
When clock pulse reaches high, Q output follows D input.
The circuit is similar to SR flip-flop, but an additional
inverter is used. There is only one input besides the clock.
32
Characteristic Table
D
0
0
1
1
Qt
0
1
0
1
Characteristic Equation
Qt+1
0
Reset
condition
0
1
Set
Condition
1
Qt+1 = D
Excitation Table
Qt → Qt+1
0→0
0 →1
1 →0
1 →1
D
0
1
0
1
Output follows input so long
as Clk is asserted.
When not asserted output is
latched
33
Timing representation
34
Types of Flip-Flop
 Clocked SET/RESET Latch (SR Flip-Flop)
 Delay-Latch or D-Latch (D Flip-Flop)
 Toggle Flip-Flop (T Flip-Flop)
 JK Flip-Flop
35
General Model of Flip-Flop
Input informing circuit
Set
Flip-Flop Input
Clk
Basic Cell
Q
Set/Reset
Decoder
Reset
Q
36
Input Forming Logic (IFL)
The Input Forming Logic (IFL) is a combinational logic block.
Its functions are:
 Decodes the flip-flop inputs, including the clock
pulse and the present state of the basic cell.
 Produces the required asserting output signals, SET or
RESET, in synchrony with the clock, while not asserting
SET and RESET at the same time.
37
The JK flip-flop
Functionally identical to SR flip-flop (J ≡ SET, K ≡ RESET)
except that J and K inputs are permitted to be asserted
together.
Modified from SR flip-flop by direct feedback from output to
the SET/RESET decoder.
1
0
38
Characteristic & Excitation Tables of JK Flip-Flop
J K Qt Qt+1
0
0
0
0
Rest
0
0
1
1
Rest
0
1
0
0
Reset
0
1
1
0
Reset
1
0
0
1
Set
1
0
1
1
Set
1
1
0
1
Toggle
1
1
1
0
Toggle
Qt → Qt+1
0 →0
0 →1
1 →0
1 →1
J
K
39
TOGGLE or T Flip-Flop
Toggle
Change of output state when the T input is asserted.
The general T flip-flop circuit is a multiple-feedback system,
which the outputs are fed back into the SET/RESET decoder.
40
Exercise
• Derive the characteristic table.
• Derive the excitation table.
• Derive the characteristic equation.
41
Asynchronous Preset and Clear
These asynchronous inputs are standard for most
integrated circuit flip-flops and are normally added in
order to make the device more flexible.
Completely overrides J and K inputs.
These inputs are NOT synchronized by the clock signal.
When asserted, they affect the output immediately.
42
JK Flip-Flop with Asynchronous Inputs
preset
clear
43
Triggering Schemes of Flip-Flops
There are 3 basic ways in which flips-flops can be
triggered or clocked.
1. Level Triggering. This is normally implemented with the
use of a simple gating scheme to gate the clock.
However, this scheme can cause the flip-flop to be
unstable under certain input conditions. The output of the
flip-flop also does not necessarily change in synchrony
with a clock edge.
44
2. Pulse Triggering. This is normally implemented with the
use of the master-slave system.
Under normal
circumstances, this system does cause the output to
change with a clock edge. However, this scheme can
give rise to problems known as “ones catching” and
“zeros catching”.
3. Edge-Triggering. This is normally implemented with the
use of the pulse transition detector. This system ensures
that the output of the flip-flop changes only with a clock
edge. This is now the predominant mode of triggering
used in synchronous sequential systems.
45
Symbols for Flip-Flop with different Triggering
Schemes
S
Q
CLK
R
Q’
Rising edge triggered
R
Q’
Low level triggered
Q
CLK
R
Q
CLK
High level triggered
S
S
S
Q
CLK
Q’
R
Q’
Falling edge triggered
46
Level Triggered vs Edge Triggered
Clk
J
K
Q (level
triggered)
Q (rising edge
triggered)
Q (falling
edge
triggered)
47
Master/Slave JK Flip-Flop
J
CLK
Q
Slave
Basic
Cell
Master
Basic
Cell
K
Q
CLK
Master input
gating
Slave input
gating
48
Master/Slave JK Flip-Flop
The master/slave JK flip-flop is a pulse-triggered device.
It guarantees stability against oscillatory state changes due to
multiple operations during asserted clock pulse (Race Problem).
On the rising-edge of the clock pulse:
1. Master basic cell is loaded in accordance to the input
condition of the 1st SET/RESET decoder (J, K, Q, Q).
2. Slave basic cell is inhibited due to the inversion clock pulse is
applied onto the inputs of the 2nd SET/RESET decoder.
3. The new state (new data) is blocked by the intermediate
NAND gates.
49
Master/Slave JK Flip-Flop
On the falling-edge of the clock pulse:
1. Master cell is inhibited.
2. Slave cell is enabled, data stored in the Master cell is
passed through the Slave cell and the outputs Q and Q are
updated.
3. The new state is fed back to the input of the 1st
SET/RESET decoder.
For the circuit configuration shown earlier, the MASTER/SLAVE
changes state on the Falling-Edge of the clock.
50
An Edge Triggering Circuit
Edge Triggering is achieved by the Pulse Transition Detector
(PTD). The PTD merely converts the CLK’s rising edge to a very
narrow pulse.
51
Summary: Next State Tables of Flip-Flops
D Flip-Flop
Action
Next State
0
Reset
1
Set
T Flip-Flop
T Actioin
Next State
0 Do nothing Unchanged
Change state
1
Toggle
(0→1, 1→0)
SR Flip-Flop
Inputs Action Next State
S R
0 0
Do
Unchanged
nothing
0 1 Reset
0
1 0
Set
1
1 1 Avoided
?
JK Flip-Flop
Inputs Action Next State
J K
0 0
Do
Unchanged
nothing
0 1
Reset
0
1 0
Set
1
1 1 Toggle Change state
(0→1, 1→0)52
D
0
1
TTL MEMORY ELEMENTS
Device
No. of
Elements
74LS73A
2
7474
2
74LS75
4
7476
2
74111
2
74116
2
74175
4
74273
8
74276
4
74279
4
Element Description
Negative–edge triggered JK flip-flop with clear
Positive–edge triggered D flip-flop with preset & clear
D latch with enable
Pulse-triggered JK flip-flop with preset & clear
Master-slave JK flip-flop with preset, clear & data lockout
4-Bit hazard-free D latch with clear and dual enable
Positive-edge triggered D flip-flop with clear
Positive-edge triggered D flip-flop with clear
Negative-edge triggered JK flip-flop with preset & clear
SR latch with active-low inputs
53
Topic 4: Clocked Sync. State-Machine Analysis
You will learn:
– State-Machine Structure
– State-Machine Output Logic
– Characteristic Equations
– State Machine Analysis
54
Synchronous Sequential Logic Circuits (I)
In digital system, one important application is control, where
digital signals are received and interpreted to generate
control outputs according to the sequence in which the
input signals are received.
Combinational logic cannot satisfy this condition, therefore
a sequential logic system is used to provide a feedback
path from the output back to the input.
Sequential Logic System, also called Sequential Circuit,
Sequential Machine, or State Machine.
55
Synchronous Sequential Logic Circuits (II)
Sequential logic system must have memory capability with at
least one feedback path from memory element to the system
inputs.
Two types of sequential circuits:
 Synchronous sequential circuits – All the states of the
circuit change at the simultaneous moments. They use flipflops for memory and cycled by a special single
synchronizing input waveform called the system clock.
 Asynchronous sequential circuits – The states of the
circuit can change any time along with the change of input
signals. They use unclocked flip-flops or time-delayed
device for memory. An asynchronous sequential circuit quiet
often resembles a combinational circuit with feedback.
56
Model of Sequential Circuits
x1
Fundamental concepts :
 Input (x1, x2,…, xn)
xn
 Output (z1, z2,…, zm)
 Present state (y1, …, yr)
y1
 Next state
 State transition
 Excitations to the Next
state (Y1,Y2,…, Yr)
•
•
•
•••
Combinational
logic
yr
•
•
•
z1
zm
Y1 • • • Yr
Memory
zi = gi (x1, x2, …, xn, y1, y2, …, yr), i = 1, 2, …, m
Yi = hi (x1, x2, …, xn, y1, y2, …, yr), i = 1, 2, …, r
Note: zi, xi, yi, and Yi are all binary variables (logic 0 or 1).
57
General Model for Mealy Network
Mealy model – Outputs depend on both external inputs and
present state.
Z1
X1
X2
Xm
Z2
Combinational
Subnetwork
Zn
D1
D
Q1
CLK
Q1
D2
Q2
D
Q2
CLK
Qk
Dk
Clock
D
Qk
CLK
58
General Model for Moore Network
Xm
Q1
…
Q2
Qk
D1
D
Q1
CLK
D2
D
Q2
CLK
Dk
D
Qk
CLK
Combinational
Subnetwork
(Output logic: for Outputs)
X1
X2
Combinational Subnetwork
(Next state logic
for Flip-Flop Inputs)
Moore model – Outputs depend ONLY on present state
Z1
Z2
Zn
Clock
59
Mealy Model State Diagram
The operation of a sequential machine can be conveniently
described by a State Diagram, which graphically defines the
State-to-State transition of a sequential machine.
60
Mealy Model State Table
Input variables are listed across the top
State identifiers are listed down the left
side
Table entries are the next state identifier
and outputs
Input (X)
S
0
1
A
B, 1
C, 0
B
B, 0
A, 1
C
A, 0
C, 0
S*, Z
S*
or
Output (Z)
S
X=0
X=1
X=0
X=1
A
B
C
1
0
B
B
A
0
1
C
A
C
0
0
How to read ?
For an input X = 0 with the sequential circuit in state A, the circuit will
proceed to the next stage B with an output Z = 1
61
Output Response of the Mealy State Machine
Determine the output response of the sequential circuit to the input
sequence X = 0110 1011 00 assuming initial state is A.
Clock Pulse: 0
Present state: A
Input x:
0
Next state:
B
Output z:
1
1
B
1
A
1
2
A
1
C
0
3
C
0
A
0
4
A
1
C
0
5
C
0
A
0
6
A
1
C
0
7
C
1
C
0
8
C
0
A
0
9
A
0
B
1
10
B
Hence, the resulting output sequence is
Y = 1100 0000 01 and the final state of
the circuit is B
What if the initial state is B or C ?
62
62
Mealy Model Timing Diagram (I)
T0
T1
T3
T2
T5
T4
Clock
State
A
B
A
C
A
C
Input X
0
1
1
0
1
0
Output Z
1
1
0
0
0
A
0
63
63
Mealy Model Timing Diagram (II)
T0
T1
T5
T4
T3
T2
Clock
State
A
B
A
C
A
C
Input x
0
1
1
0
1
0
Output z 1
1
0
0
0
0
“False” 0 Output
A
“False” 1 Output
The “false” value arises because the network
has assumed a new state but the old input
associated with the previous state is still
present.
64
64
Mealy Model Timing Diagram
 Assumption: state changes on high-to-low transition of the
clock.
 Output z can change any time either due to input or state
changes, since z is a function of both.
 Two unexpected output changes are observed:
 At T0, z drops to 0 when the state changes to B, and
goes back to 1 when input x changes to 1.
 A similar event occurs at time T3.
 The output of a Mealy model circuit should be sampled
only when the circuit has stabilized after an input change.
65
Moore Model State Diagram and State Table
Input (X)
S
0
1
Output
(Z)
S0
S1
S2
S3
S*
66
Moore Machine’s Timing Diagram
 Assume initial state is A and the input sequence X = 10101.
The timing chart for the Moore sequential network:
Clock
X
0
1
State
S0
Output
0
S2
1
1
S2
1
1
0
S3
S3
S1
0
0
1
Output Changes only when FFs change
state. Output change resulting from input
change does not appear until the
triggering edge of the clock; therefore, the
output is displaced in time with respect to
the input sequence.
67
67
Analysis of Synchronous Sequential Circuits
1. Identify functional blocks of system
2. Write Boolean expression for each of the outputs of NEXTSTATE DECODER (inputs of flip-flops), and output of the
circuit.
3. Plot K-maps (state map) from Boolean expressions.
4. Construct PRESENT & NEXT STATE TABLE using K-maps
(state map) and Characteristic Table of Flip-Flops
5. Use present state, input, output, and next state to develop a
State Diagram.
6. Describe behaviour based on state diagram.
68
Example 1
Analyze the following sequential circuit
CLK
X
Flip-Flop B
SB
A
X
Q
B
C
RB
B
Q
A
Y
SA
B
C
RA
B
Q
Q
Flip-Flop A
A
A
69
Next State Maps
Plot K-maps from logic expressions, use input X, and present state
variables A and B as input variables of K-maps.
AB
X
00 01 11 10
AB
X
0
0
1
1
RA = X B
SA = X B
AB
X
00 01 11 10
AB
X
0
0
1
1
SB = X A
00 01 11 10
00 01 11 10
RB = X A
70
Output Map
AB
X
00 01 11 10
0
1
Y = (XAB)
71
Present and Next State Table
State 0
State 1
State 2
State 3
AB
Present Input Next State Output True Next State
Sate
A B X SA RA SB RB
Y
At+1
Bt+1
0 0
0
0 0
1
0 1
0
0 1
1
1 0
0
1 0
1
1 1
0
1 1
1
00
01
11
10
0
0
1
1
0
1
0
0
0
0
X
Characteristic Table
SA = X B
72
State Diagram
•
Obtain At+1 (and Bt+1) from SR next state table by comparing the A,
SA and RA, etc.
•
Draw state diagram for the circuit to be analyzed:
0/0
1/0
1/0
A B
0 0
Format: X/Y
1/1
0/0
A B
0 1
A B
1 0
0/0
0/0
1/0
A B
1 1
73
Analysis
Diagram shows the machine generates a proper
sequence from state 00 to 01, 11, 10 and goes
back to 00. The only time to generate an output
Y is in state 10 to 00 when input X is asserted
high. Two flip-flops produce 4 useful states.
74
Example 2
Analyze the following sequential circuit
X
B
C
C
XABC
A
B
B X A X
+5V
B
CLR
K
J
PRE
B
CLR
K
+5V
+5V
J
PRE
LOAD
CLK
RESET
CLR
K
J
PRE
Q
Q
Q
Q
Q
Q
A
A
B
B
C
C
75
Next State and Output Equations
Derive the logic expressions for outputs of the NEXT STATE
decoder and outputs of the sequential circuit
JA = BC + BX,
KA = B
JB = AB + BC
KB = B
JC = AX
KC = B + X
LOAD = ABCX
76
Nex t State M aps
AB
CX
00
01
11
10
AB
CX
00
01
11
10
00
00
0
1
1
0
01
01
0
1
1
0
11
11
0
1
1
0
10
10
0
1
1
0
JA = BC + BX
AB
CX
KA = B
00
01
11
10
00
0
0
0
1
01
0
0
0
11
1
0
10
1
0
AB
CX
00
01
11
10
00
0
1
1
0
1
01
0
1
1
0
0
1
11
0
1
1
0
0
1
10
0
1
1
0
JB = AB + BC
KB = B
77
Next State Maps
AB
CX
AB
CX
00
01
11
10
00
1
1
1
1
0
01
0
1
1
0
0
0
11
0
1
1
0
0
0
10
1
1
1
1
00
01
11
10
00
0
0
0
0
01
1
1
0
11
1
1
10
0
0
JC = AX
KC = B + X
AB
CX
00
01
11
10
00
0
0
0
0
01
0
0
0
0
11
0
0
1
0
10
0
0
0
0
LOAD = ABCX
78
Remaining steps
•Set up present and next state table
•Draw state diagram
•Analyze function
79
State
0
State
1
State
2
State
3
State
4
State
5
State
6
State
7
A
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
B
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
C
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Load A* B* C*
0
1 0 0
0
0 0 1
0
1 1 0
0
1 1 1
0
0 0 0
0
0 0 1
0
0 0 0
0
0 0 0
0
1 1 0
0
1 1 0
0
1 1 0
0
1 1 1
0
0 0 0
0
0 0 0
0
0 0 0
1
0 0 0
80
State Diagram
• States 000, 001, 100,
110
and
111
are
sequential states.
• States 010, 011 and
101 are never reached
unless NOISE or a
POWER
ON
CONDITION forces the
circuit
into
these
states.
They
are
unused states.
• Unwanted states that
hold the machine must
be avoided. They are
HOLD states (unused).
• Above 3 states are not
HOLD states - will not
stay for more than one
clock cycle.
Format: X/LOAD
ANY
STATE
011
SYSTEM RESET
0/0
010
1/0
1/0, 0/0
000
1/0
0/0
State changes on
falling-edge of clock
100
1/0, 0/0
1/0, 0/0
001
1/0
0/0
111
110
1/0
0/0
101
0/0,
1/1
81
Programmable Hold States
Programmable Hold States are states which a circuit
can be placed with a specific input condition, the
system will hold and no input condition except for a
special reserved input will release or reset the system.
This temporary holding operation can be a useful
debugging tool and is done by a pulse feature built
into a software or computer program.
82
Example 3
Analyze the following sequential circuit
CLK
+5V
+5V
+5V
RESET
CLR
Q
A
D
PRE
CLR
D
PRE
CLR
D
PRE
Q
Q
Q
Q
Q
A
B
B
C
C
83
Flip Flop equations (input of flip-flops)
D A = C, D B = A, D C = B
AB
C
0
1
AB
00
1
0
01
1
0
DA
11
1
0
10
1
0
C
0
1
0
1
01
0
0
11
1
1
10
1
1
DB
AB
C
00
0
0
AB
00
0
0
01
1
1
Dc
11
1
1
10
0
0
C
0
1
00 01 11 10
100 101 111 110
000 001 011 010
PRESENT and NEXT STATE map
84
PRESENT and NEXT STATE Tabulation
Present
State
A B C
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Inputs
-
Next State
Code
DA DB DC
1
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
Outputs
-
True Next
State
A B C
1 0 0
0 0 0
1 0 1
0 0 1
1 1 0
0 1 0
1 1 1
0 1 1
85
Draw State Diagram
A
B
C
A*
B*
C*
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
1
0
1
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
0
1
1
1
1
1
1
0
1
1
86
Draw State Digram – Systematic way
A
B
C
A*
B*
C*
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
1
0
1
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
0
1
1
1
1
1
1
0
1
1
87
State Diagram
Two Hold states (010 and 101) are isolated from the main
sequence states. This is typical of a "twisted-ring counter" circuit.
RESET
ANY
STATE
000
001
011
010
100
State changes take
place on the
rising-edge of
clock
101
110
111
88
Example 4
Analyze the twisted-type ring counter circuit
C
RESET
C +5V
A
A
B
+5V
B+5V
CLK
CLR
K
J
PRE
CLR
K
J
PRE
CLR
K
J
PRE
Q
Q
Q
Q
Q
Q
A
A
B
B
C
C
Flip-Flop equations:
J A = C, J B = A, J C = B
K A = C, K B = A, K C = B
89
NEX T STATE M AP S
AB
C
0
1
00
1
0
JA
01 11
1
1
0
0
0
1
00
1
1
01
1
1
0
1
C
00
0
0
01
1
1
00
0
1
0
1
KA
01 11
0
0
1
1
11
0
0
10
0
0
C
00
0
0
0
1
AB
11
1
1
10
0
0
C
0
1
10
0
1
KB
AB
JC
AB
C
10
1
0
JB
AB
C
AB
00
1
1
01
0
0
11
1
1
KC
01 11
0
0
0
0
10
1
1
10
1
1
Flip-Flop equations:
J A = C, J B = A, J C = B
K A = C, K B = A, K C = B
90
PRESENT and NEXT STATE Tabulation
AB
00
C
01
11
10
0
1
PRESENT
STATE
A
B
C
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
NEXT STATE CODE
INPUT
-
OUTPUT
JA
1
0
1
0
1
0
1
0
KA
0
1
0
1
0
1
0
1
JB
1
1
1
1
0
0
0
0
KB
0
0
0
0
1
1
1
1
JC
0
0
1
1
0
0
1
1
KC
1
1
0
0
1
1
0
0
TRUE NEXT
STATE
A
B
C
91
State Diagram of the Circuit
000
110
101
001
011
010
111
100
92
Design of Synchronous Sequential Circuits
1. Study circuit specifications.
2. Draw a block diagram, and/or timing diagram, and/or flow chart,
and identify the inputs and outputs.
3. Draw State Diagram.
4. Develop Present State/Next State Table
5. Determine number of flip-flops. Number of flip-flops dictate the
number of state variables.
6. Assign binary values to each state. Binary values are called state
assignment codes.
7. Decide on flip-flop type to construct characteristic truth-table.
8. Use K-maps to derived logic equations for Next State Decoder and
Output Decoder.
9. Draw sequential circuit based on the logic equations.
93
Guidelines for Construction of State Diagram
1. Understand the problem statement by constructing sample
input and output sequences.
2. Determine the reset conditions.
3. If only a few sequences lead to a nonzero output, it is good
to start constructing partial state diagram with those
sequences. Another way is to set up states for sequences or
groups of sequences that must be “remembered” by the
network.
4. When adding arrow, determine if it can go to one of the
previously defined states before creating a new state.
5. Verify that for each combination of values of the input
variables, there is one and only one path leaving each state.
6. Test if the correct output sequences can be obtained from
your diagram with the input sequences in part 1.
94
Design a Sequence Recognizer
Design a circuit with one input X and one output Z that
recognizes the input sequence 101. The circuit is also
required to recognize the overlapping sequences.
For example:
X=
Z=
0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 0
0 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0
95
101 Sequence Recognizer - State Diagram
If a 1 is received, go to new state S1 to “remember” that the first input in
the desired sequence has been received
Start with reset state
0/0
S0
0/0
S0
1/0
S2 created to “remember” that
the first two inputs in the desired
sequence (10) have been received
S1
0/0
0/0
S0
S2
1/0
1/0
S1
0/0
S0
0/0
S2
1/1
1/0
1/0
S1
0/0
96
101 Sequence Recognizer
- build up State/Output Table
0/0
S0
0/0
S2
1/1
0/0
1/0
S1
x
1/0
S
0
1
S0
S0, 0
S1, 0
S1
S2, 0
S1, 0
S2
S0, 0
S1, 1
S*, z
State/Output Table
97
101 Sequence Recognizer - set state variables
Let Ns be the number of states and NF the number of flipflops (state variables), then
2
N F −1
< NS ≤ 2
NF
Since Ns = 3, the number of state variables NF = 2
Let the state variables be Q1 and Q0.
State assignment:
S0: Q1Q0 = 00
S1: Q1Q0 = 01
S2: Q1Q0 = 10
98
Construct Present and Next State Table
0/0
00
0/0
1/0
1/0
1/1
01
10
0/0
Present
state
I/P
Next state
O/P
Next state
decoder
A
B
X
At+1
Bt+1
Z
DA
DB
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
1
0
1
0
1
0
0
1
0
0
1
1
0
1
0
0
1
1
0
0
0
0
0
0
0
1
0
1
0
1
1
0
1
1
1
0
X
X
X
X
X
1
1
1
X
X
X
X
X
99
Derive State Maps and Output Maps
X
AB
0
1
00 01 11 10
0
0
1
0
d
d
0
0
X
I/P
A
0
0
0
0
1
1
1
1
X
0
1
0
1
0
1
0
1
B
0
0
1
1
0
0
1
1
Next state
At+1
0
0
1
0
0
0
X
X
Bt+1
0
1
0
1
0
1
X
X
O/P
Z
0
0
0
0
0
1
X
X
00 01 11 10
0
1
0
1
DA = X’B
Present
state
AB
0
1
0
1
d
d
DB = X
Next state
decoder
DA
0
0
1
0
0
0
X
X
DB
0
1
0
1
0
1
X
X
X
AB 00
0 0
1 0
01 11 10
0
0
0/0
d
d
Z = XA
00
0/0
0
1
1/0
1/0
1/1
01
10
0/0
100
Draw Logic Circuit
D
A
A
Flip-Flop A
Z
X
D
B
B
CLK
Flip-Flop B
101
Robot and Maze Finite-state Controller - Specs
Design a finite-state controller to maneuver the robot in the
maze.
X = 1 sees obstacle
X = 0 otherwise
Sensor
(X)
wheels
Bottom view of robot
Robot has two control lines; Z1 =1 turns the robot to the left and Z2 = 1
turns the robot to the right. When it encounters an obstacle, the robot
should turn right until no obstacle is detected. The next time an
obstacle is detected, the robot should turn left until the obstacle is
102
cleared, an so on.
Robot and Maze Finite-state Controller
Design a finite-state controller to maneuver the robot in the maze.
X = 1 when in contact with obstacle
X = 0 otherwise
Sensor
(X)
w heels
Bottom view of robot
Robot has two control lines; Z1 =1 turns the robot to the left and Z2 = 1 turns
the robot to the right. When it encounters an obstacle, the robot should turn
right until no obstacle is detected. The next time an obstacle is detected, the
robot should turn left until the obstacle is cleared, an so on.
103
Robot and Maze Finite-state Controller
– State Diagram / Table
State NL (y1y0 = 00) = no obstacle detected, last turn was left
State OR (y1y0 = 01) = obstacle detected, turning right
State NR (y1y0 = 11) = no obstacle detected, last turn was right
State OL (y1y0 = 10) = obstacle detected, turning left
1/01
0/00
1/01
OR
NL
OL
X
0/00
X/Z1Z0
0/00
State Table
NR
1/10
1/10
0/00
S
0
1
NL
NL, 00
OR, 01
OR
NR, 00
OR, 01
NR
NR, 00
OL, 10
OL
NL, 00
OL, 10
S*, Z1Z0
104
Next State Decoder
Use JK Excitation Table, derive the Next State Code
Present state
0/00
0/00
1/10
Input
True next state
Output
Next State Code
y
1
y
2
X
y
1
y
2
Z Z
1 2
J
1
K
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
1
0
0
1
1
1
0
1
1
1
0
0
1
0
0
1
0
1
X
X
X
X
1
0
0
0
NL
OL
1/01
X/ Z 1 Z 2
1/10
OR
NR
0
0
0
0
1
J
2
K
0
0
X
X
X
X
0
1
2
1/01
0/00
0/00
105
Next State Maps
From the state table, draw K-maps for J1, K1, J2, K2, Z1 and Z2
y1y2
y1y2
X
0
1
00
0
0
01
1
0
11 10
X X
X X
X
0
1
00
X
X
y1y2
y 1y 2
0
1
11 10
0 1
0 0
K1 = y2 X
J1 = y2 X
X
01
X
X
00
0
1
01
X
X
11 10
X 0
X 0
J2 = y1 X
X
0
1
00
X
X
01
0
0
11 10
0 X
1 X
K2 = y1 X
106
Output Map
y 1y 2
X
00
0
0
0
1
01
0
0
11 10
0 0
1 1
Z1 = y1 X
y1y2
X
0
1
00
0
1
01
0
1
11 10
0 0
0 0
Z2 = y1 X
107
Draw logic circuit diagram
J1
K1
y1
y1
Z1
X
J2
y2
Z2
K2
CLK
y2
108
Simple Vending Machine Controller - Specs
 Design a controller for a simple coin-operated candy
machine.
 A candy cost 40⊄, and the machine could only accept
10⊄ and 20⊄ coins. Change should be returned if more
than 40⊄ is deposited. No more than 50⊄ can be
deposited on a single purchase; therefore, the maximum
change is 10⊄.
 Assume that it is physically impossible to insert two
coins at the same time. Also assume the coin detector
automatically reset its outputs to 0 in the next clock
pulse.
Release
R
candy
N
Coin
Controller
detector
C
Release
Y
change
109
Simple Vending Machine Controller
- Construct State Diagram
N = 1 if a 10⊄ coin is deposited, Y = 1 if a 20⊄ coin is deposited
R = 1 releases the candy, C = 1 releases the change
Note: N = Y = 1 in the same clock cycle is impossible.
00/00
Format NY/RC
10/00
00/00
S0 01/00
S1
01/00
10/00
10/10
01/11
S3
00/00
State assignment:
S0 : Q1Q0 = 00 ( 0⊄ deposited)
S1 : Q1Q0 = 01 (10⊄ deposited)
S2 : Q1Q0 = 10 (20⊄ deposited)
S3 : Q1Q0 = 11 (30⊄ deposited)
01/10 S
2
10/00
00/00
110
Next State Decoder
Present
State
Inputs
Next State
Output
A
B
N
Y
A*
B*
R
C
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
0
0
1
0
0
0
0
1
1
X
X
X
X
0
1
0
0
0
1
0
0
0
1
0
1
1
1
0
0
0
1
1
0
1
0
0
0
0
1
1
1
X
X
X
X
1
0
0
0
1
0
0
0
1
0
0
1
0
0
1
0
1
0
1
0
1
1
0
0
1
0
1
1
X
X
X
X
1
1
0
0
1
1
0
0
1
1
0
1
0
0
1
1
1
1
1
0
0
0
1
0
1
1
1
1
X
X
X
X
F/F inputs
TA
TB
111
Next State and Output Maps
AB
NY
00
01
11
10
00 01 11 10
0
1
X
0
0
1
X
1
0
1
X
1
0
1
X
0
AB
NY
00
01
11
10
TA= Y + BN
AB
NY
00
01
11
10
0
0
X
0
0
1
X
1
R = AY + ABN
0
0
X
1
0
0
X
1
0
1
X
1
0
0
X
1
TB= N + ABY
00 01 11 10
0
0
X
0
00 01 11 10
0
1
X
0
AB
NY
00
01
11
10
00 01 11 10
0
0
X
0
0
0
X
0
0
1
X
0
C = ABY
0
0
X
0
112
Draw logic circuit diagram
Y
B
N
TA
A
TB
B
BN
ABY
A
AY
CLK
C
R
ABN
113