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Transcript
Lecture 04: MOS Transistor The MOS Transistor Polysilicon Aluminum The NMOS Transistor Cross Section n areas have been doped with donor ions (arsenic) of concentration ND - electrons are the majority carriers Polysilicon W Gate Source n+ L p substrate Gate oxide Drain n+ Field-Oxide (SiO2) p+ stopper Bulk (Body) p areas have been doped with acceptor ions (boron) of concentration NA - holes are the majority carriers Switch Model of NMOS Transistor | VGS | Source (of carriers) Open (off) (Gate = ‘0’) Gate Drain (of carriers) Closed (on) (Gate = ‘1’) Ron | VGS | < | VT | | VGS | > | VT | Switch Model of PMOS Transistor | VGS | Source (of carriers) Open (off) (Gate = ‘1’) Gate Drain (of carriers) Closed (on) (Gate = ‘0’) Ron | VGS | > | VDD – | VT | | | VGS | < | VDD – |VT| | Threshold Voltage Concept VGS G + D S - n+ n channel n+ p substrate depletion region B The value of VGS where strong inversion occurs is called the threshold voltage, VT The Threshold Voltage where VT = VT0 + (|-2F + VSB| - |-2F|) VT0 is the threshold voltage at VSB = 0 and is mostly a function of the manufacturing process Difference in work-function between gate and substrate material, oxide thickness, Fermi voltage, charge of impurities trapped at the surface, dosage of implanted ions, etc. VSB is the source-bulk voltage F = -Tln(NA/ni) is the Fermi potential (T = kT/q = 26mV at 300K is the thermal voltage; NA is the acceptor ion concentration; ni 1.5x1010 cm-3 at 300K is the intrinsic carrier concentration in pure silicon) = (2qsiNA)/Cox is the body-effect coefficient (impact of changes in VSB) (si=1.053x10-10F/m is the permittivity of silicon; Cox = ox/tox is the gate oxide capacitance with ox=3.5x10-11F/m) The Body Effect 0.9 0.85 0.8 VSB is the substrate bias voltage (normally positive for n-channel devices with the body tied to ground) 0.75 0.7 0.65 0.6 0.55 A negative bias causes VT to increase from 0.45V to 0.85V 0.5 0.45 0.4 -2.5 -2 -1.5 VBS (V) -1 -0.5 0 Transistor in Linear Mode Assuming VGS > VT VGS VDS G S D n+ ID n+ - V(x) + x B The current is a linear function of both VGS and VDS Voltage-Current Relation: Linear Mode For long-channel devices (L > 0.25 micron) When VDS VGS – VT ID = k’n W/L [(VGS – VT)VDS – VDS2/2] where k’n = nCox = nox/tox = is the process transconductance parameter (n is the carrier mobility (m2/Vsec)) kn = k’n W/L is the gain factor of the device For small VDS, there is a linear dependence between VDS and ID, hence the name resistive or linear region Transistor in Saturation Mode Assuming VGS > VT VGS VDS G S D n+ VDS > VGS - VT ID n+ - V -V + GS T Pinch-off B The current remains constant (saturates). Voltage-Current Relation: Saturation Mode For long channel devices When VDS VGS – VT ID’ = k’n/2 W/L [(VGS – VT) 2] since the voltage difference over the induced channel (from the pinch-off point to the source) remains fixed at VGS – VT However, the effective length of the conductive channel is modulated by the applied VDS, so ID = ID’ (1 + VDS) where is the channel-length modulation (varies with the inverse of the channel length) Current Determinates For of a fixed VDS and VGS (> VT), IDS is a function the distance between the source and drain – L the channel width – W the threshold voltage – VT the thickness of the SiO2 – tox the dielectric of the gate insulator (SiO2) – ox the carrier mobility - for nfets: n = 500 cm2/V-sec - for pfets: p = 180 cm2/V-sec Long Channel I-V Plot (NMOS) 6 X 10-4 VDS = VGS - VT 5 VGS = 2.5V 4 VGS = 2.0V 3 Linear Saturation 2 VGS = 1.5V 1 VGS = 1.0V 0 cut-off 0 0.5 1 1.5 2 2.5 VDS (V) NMOS transistor, 0.25um, Ld = 10um, W/L = 1.5, VDD = 2.5V, VT = 0.4V Short Channel Effects 10 Behavior of short channel device mainly due to 5 Velocity saturation – the velocity of the carriers saturates due to scattering (collisions suffered by the carriers) 0 0 c= 1.5 (V/m) 3 For an NMOS device with L of .25m, only a couple of volts difference between D and S are needed to reach velocity saturation Voltage-Current Relation: Velocity Saturation For short channel devices Linear: When VDS VGS – VT ID = k’n W/L [(VGS – VT)VDS – VDS2/2] Saturation: When VDS = VDSAT ≤ VGS – VT IDSat = k’n W/L [(VGS – VT)VDSAT – VDSAT2/2] Velocity Saturation Effects For short channel devices and large enough VGS – VT 10 VDSAT < VGS – VT so the device enters saturation before VDS reaches VGS – VT and operates more often in saturation 0 IDSAT has a linear dependence wrt VGS so a reduced amount of current is delivered for a given control voltage Short Channel I-V Plot (NMOS) 2.5 X 10-4 Early Velocity Saturation VGS = 2.5V 2 VGS = 2.0V 1.5 Linear 1 Saturation VGS = 1.5V VGS = 1.0V 0.5 0 0 0.5 1 1.5 2 2.5 VDS (V) NMOS transistor, 0.25um, Ld = 0.25um, W/L = 1.5, VDD = 2.5V, VT = 0.4V MOS ID-VGS Characteristics Linear (short-channel) versus quadratic (longchannel) dependence of ID on VGS in saturation X 10-4 6 5 4 3 2 1 0 Velocity-saturation causes the shortchannel device to saturate at substantially smaller values of VDS 2.5 resulting in a substantial drop in current drive 0 0.5 1 1.5 VGS (V) (for VDS = 2.5V, W/L = 1.5) 2 Short Channel I-V Plot (PMOS) All polarities of all voltages and currents are reversed -2 VDS (V) -1 0 0 VGS = -1.0V -0.2 VGS = -1.5V -0.4 -0.6 VGS = -2.0V -0.8 VGS = -2.5V -1 X 10-4 PMOS transistor, 0.25um, Ld = 0.25um, W/L = 1.5, VDD = 2.5V, VT = -0.4V The MOS Current-Source Model ID = 0 for VGS – VT 0 G ID S D ID = k’ W/L [(VGS – VT)Vmin–Vmin2/2](1+VDS) for VGS – VT 0 with Vmin = min(VGS – VT, VDS, VDSAT) and VGT = VGS - VT B VT = VT0 + (|-2F + VSB| - |-2F|) Determined by the voltages at the four terminals and a set of five device parameters NMOS PMOS VT0(V) 0.43 -0.4 (V0.5) 0.4 -0.4 VDSAT(V) 0.63 -1 k’(A/V2) 115 x 10-6 -30 x 10-6 (V-1) 0.06 -0.1 The Transistor Modeled as a Switch 7 x105 6 Modeled as a switch with infinite off resistance and a finite on resistance, Ron VGS VT 5 4 Ron S D 3 2 1 Resistance inversely proportional to W/L (doubling W halves Ron) For VDD>>VT+VDSAT/2, Ron independent of VDD 0 0.5 1 (for VGS = VDD, VDS = VDD VDD/2) VDD(V) NMOS(k) PMOS (k) 1.5 2 VDD (V) 1 35 115 1.5 19 55 2.5 Once VDD approaches VT, Ron increases dramatically 2 15 38 2.5 13 31 Ron (for W/L = 1) For larger devices divide Req by W/L Other (Submicon) MOS Transistor Concerns Velocity saturation Subthreshold conduction Threshold variations Transistor is already partially conducting for voltages below VT In long-channel devices, the threshold is a function of the length (for low VDS) In short-channel devices, there is a drain-induced threshold barrier lowering at the upper end of the VDS range (for low L) Parasitic resistances resistances associated with the source and drain contacts G S D RS Latch-up RD Subthreshold Conductance Transition from ON to OFF is gradual (decays exponentially) Current roll-off (slope factor) is also affected by increase in temperature 10-2 Linear region Quadratic region Subthreshold exponential region S = n (kT/q) ln (10) (typical values 60 to 100 mV/decade) VT 10-12 0 0.5 1 1.5 2 2.5 VGS (V) ID ~ IS e (qVGS/nkT) where n 1 Has repercussions in dynamic circuits and for power consumption Subthreshold ID vs VGS ID = IS e (qVGS/nkT) (1 - e –(qVDS/kT))(1 + VDS) VDS from 0 to 0.5V Subthreshold ID vs VDS ID = IS e (qVGS/nkT) (1 - e –(qVDS/kT))(1 + VDS) VGS from 0 to 0.3V Threshold Variations VT VT Long-channel threshold L Threshold as a function of the length (for low VDS ) Low VDS threshold VDS Drain-induced barrier lowering (for low L)