Download LTC2640 - Single 12-/10-/8-Bit SPI VOUT DACs with 10ppm/°C

LTC2640
Single 12-/10-/8-Bit SPI
VOUT DACs with
10ppm/°C Reference
Description
Features
Integrated Precision Reference
2.5V Full-Scale 10ppm/°C (LTC2640-L)
4.096V Full-Scale 10ppm/°C (LTC2640-H)
n Maximum INL Error: 1LSB (LTC2640A-12)
n Bidirectional Reference: Input or 10ppm/°C Output
n Low Noise (0.7mVpp, 0.1Hz to 200kHz)
n Guaranteed Monotonic Over Temperature
n2.7V to 5.5V Supply Range (LTC2640-L)
n Low Power Operation: 180µA at 3V
n Power Down to 1.8µA Maximum (C and I Grades)
n Asynchronous DAC Clear Pin (LTC2640-Z)
n Power-On Reset to Zero or Mid-Scale options
n Double-Buffered Data Latches
n Guaranteed Operation from –40°C to 125°C (H-Grade)
n8-Lead TSOT-23 (ThinSOT™) Package
n
Applications
The LTC2640 DACs use a SPI/MICROWIRE™ compatible
3-wire serial interface which operates at clock rates up
to 50MHz.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the property
of their respective owners. Protected by U.S. Patents, including 5396245, 5859606, 6891433,
6937178 and 7414561.
(LTC2640-Z)
VCC
REF
INTERNAL
REFERENCE
SDI
Each DAC can also operate in External Reference mode,
in which a voltage supplied to the REF pin sets the fullscale output.
The LTC2640 incorporates a power-on reset circuit. Options are available for Reset to Zero-Scale or Reset to
Mid-Scale after power-up.
Mobile Communications
Process Control and Industrial Automation
Automatic Test Equipment
Portable Equipment
Automotive
Optical Networking
Block Diagram
The LTC2640-L has a full-scale output of 2.5V, and operates
from a single 2.7V to 5.5V supply. The LTC2640-H has a
full-scale output of 4.096V, and operates from a 4.5V to
5.5V supply. A 10ppm/°C reference output is available at
the REF pin.
Integral Nonlinearity (LTC2640A-LZ12)
1.0
SWITCH
VCC = 3V
VFS = 2.5V
0.5
SCK
CONTROL
DECODE LOGIC
24-BIT
SHIFT
REGISTER
RESISTOR
DIVIDER
INL (LSB)
n
n
n
n
n
n
The LTC®2640 is a family of 12-, 10-, and 8-bit voltage‑
output DACs with an integrated, high-accuracy, low-drift
reference in an 8-lead TSOT-23 package. It has a rail-to-rail
output buffer that is guaranteed monotonic.
DACREF
CS/LD
INPUT
REGISTER
DAC
REGISTER
DAC
0
–0.5
VOUT
–1.0
CLR
0
1024
2048
3072
4095
CODE
GND
2640 TA01b
2640 TA01
For more information www.linear.com/LTC2640
2640fc
1
LTC2640
Absolute Maximum Ratings
(Notes 1, 2)
Supply Voltage (VCC).................................... –0.3V to 6V
CLR, CS/LD, REF_SEL, SCK, SDI.................. –0.3V to 6V
VOUT, REF .......................... –0.3V to Min(VCC + 0.3V, 6V)
Operating Temperature Range
LTC2640C................................................. 0°C to 70°C
LTC2640I.............................................. –40°C to 85°C
LTC2640H (Note 3)............................. –40°C to 125°C
Maximum Junction Temperature........................... 150°C
Storage Temperature Range................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................... 300°C
Pin Configuration
LTC2640-Z
LTC2640-M
TOP VIEW
CS/LD 1
SCK 2
SDI 3
GND 4
8 CLR
7 VOUT
6 REF
5 VCC
TOP VIEW
CS/LD 1
SCK 2
SDI 3
GND 4
TS8 PACKAGE
8-LEAD PLASTIC TSOT-23
TJMAX = 150°C (NOTE 6), θJA = 195°C/W
8 REF_SEL
7 VOUT
6 REF
5 VCC
TS8 PACKAGE
8-LEAD PLASTIC TSOT-23
TJMAX = 150°C (NOTE 6), θJA = 195°C/W
2640fc
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For more information www.linear.com/LTC2640
LTC2640
Order Information
LTC2640 A
C
TS8 –L
M
12
#TRM PBF
LEAD FREE DESIGNATOR
TAPE AND REEL
TR = 2,500-Piece Tape and Reel
TRM = 500-Piece Tape and Reel
RESOLUTION
12 = 12-Bit
10 = 10-Bit
8 = 8-Bit
POWER-ON RESET
M = Reset to Mid-Scale
Z = Reset to Zero-Scale
FULL-SCALE VOLTAGE, INTERNAL REFERENCE MODE
L = 2.5V
H = 4.096V
PACKAGE TYPE
TS8 = 8-Lead Plastic TSOT-23
TEMPERATURE GRADE
C = Commercial Temperature Range (0°C to 70°C)
I = Industrial Temperature Range (–40°C to 85°C)
H = Automotive Temperature Range (–40°C to 125°C)
ELECTRICAL GRADE (OPTIONAL)
A = ±1LSB Maximum INL (12-Bit)
PRODUCT PART NUMBER
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
2640fc
For more information www.linear.com/LTC2640
3
LTC2640
Product Selection Guide
PART NUMBER
VFS WITH INTERNAL
PART MARKING* REFERENCE
POWER-ON RESET
TO CODE
PIN 8
RESOLUTION
VCC
MAXIMUM INL
LTC2640A-LM12
LTDHV
2.5V • (4095/4096)
Mid-Scale
REF_SEL
12-Bit
2.7V – 5.5V
±1LSB
LTC2640A-LZ12
LTDHW
2.5V • (4095/4096)
Zero
CLR
12-Bit
2.7V – 5.5V
±1LSB
LTC2640A-HM12 LTDHX
4.096V • (4095/4096)
Mid-Scale
REF_SEL
12-Bit
4.5V – 5.5V
±1LSB
LTC2640A-HZ12
LTDHY
4.096V • (4095/4096)
Zero
CLR
12-Bit
4.5V – 5.5V
±1LSB
LTC2640-LM12
LTDHV
2.5V • (4095/4096)
Mid-Scale
REF_SEL
12-Bit
2.7V – 5.5V
±2.5LSB
LTC2640-LM10
LTDHZ
2.5V • (1023/1024)
Mid-Scale
REF_SEL
10-Bit
2.7V – 5.5V
±1LSB
LTC2640-LM8
LTDJF
2.5V • (255/256)
Mid-Scale
REF_SEL
8-Bit
2.7V – 5.5V
±0.5LSB
LTC2640-LZ12
LTDHW
2.5V • (4095/4096)
Zero
CLR
12-Bit
2.7V – 5.5V
±2.5LSB
LTC2640-LZ10
LTDJB
2.5V • (1023/1024)
Zero
CLR
10-Bit
2.7V – 5.5V
±1LSB
LTC2640-LZ8
LTDJG
2.5V • (255/256)
Zero
CLR
8-Bit
2.7V – 5.5V
±0.5LSB
LTC2640-HM12
LTDHX
4.096V • (4095/4096)
Mid-Scale
REF_SEL
12-Bit
4.5V – 5.5V
±2.5LSB
LTC2640-HM10
LTDJC
4.096V • (1023/1024)
Mid-Scale
REF_SEL
10-Bit
4.5V – 5.5V
±1LSB
LTC2640-HM8
LTDJH
4.096V • (255/256)
Mid-Scale
REF_SEL
8-Bit
4.5V – 5.5V
±0.5LSB
LTC2640-HZ12
LTDHY
4.096V • (4095/4096)
Zero
CLR
12-Bit
4.5V – 5.5V
±2.5LSB
LTC2640-HZ10
LTDJD
4.096V • (1023/1024)
Zero
CLR
10-Bit
4.5V – 5.5V
±1LSB
LTC2640-HZ8
LTDJJ
4.096V • (255/256)
Zero
CLR
8-Bit
4.5V – 5.5V
±0.5LSB
*The temperature grade is identified by a label on the shipping container.
2640fc
4
For more information www.linear.com/LTC2640
LTC2640
Electrical
Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VOUT unloaded unless otherwise specified.
LTC2640-LM12/-LM10/-LM8/-LZ12/-LZ10/-LZ8, LTC2640A-LM12/-LZ12 (VFS = 2.5V)
LTC2640-8
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
LTC2640-10
LTC2640-12
MAX MIN TYP MAX MIN TYP
LTC2640A-12
MAX MIN TYP MAX
UNITS
DC Performance
l
8
10
12
12
Bits
Monotonicity
VCC = 3V, Internal Ref. (Note 4) l
8
10
12
12
Bits
DNL
Differential
Nonlinearity
VCC = 3V, Internal Ref. (Note 4) l
±0.5
INL
Integral
Nonlinearity
VCC = 3V, Internal Ref. (Note 4) l
±0.05 ±0.5
ZSE
Zero-Scale Error
VCC = 3V, Internal Ref.,
Code = 0
l
0.5
VOS
Offset Error
VCC = 3V, Internal Ref. (Note 5) l
±0.5
VOSTC
VOS Temperature VCC = 3V, Internal Ref. (Note 5)
Coefficient
FSE
Full-Scale Error
VFSTC
Full-Scale Voltage VCC = 3V, Internal Ref. (Note 10)
Temperature
C-Grade
Coefficient
I-Grade
H-Grade
Resolution
Load Regulation
ROUT
DC Output
Impedance
VCC = 3V, Internal Ref. (Note 11)
Internal Ref., Mid-Scale,
VCC = 3V ±10%,
–5mA ≤ IOUT ≤ 5mA,
VCC = 5V ±10%,
–10mA ≤ IOUT ≤ 10mA
Internal Ref., Mid-Scale,
VCC = 3V ±10%,
–5mA ≤ IOUT ≤ 5mA,
VCC = 5V ±10%,
–10mA ≤ IOUT ≤ 10mA
±1
±1
LSB
±0.2
±1
±1
±2.5
±0.5
±1
LSB
5
0.5
5
0.5
5
0.5
5
mV
±5
±0.5
±5
±0.5
±5
±0.5
±5
±10
l
±0.5
±0.08 ±0.4
±10
±10
±10
±10
±10
±0.08 ±0.4
±10
±0.08 ±0.4
±10
±10
±10
±0.08 ±0.4
±10
±10
±10
±10
±10
±10
mV
µV/°C
%FSR
ppm/°C
ppm/°C
ppm/°C
l
0.009 0.016
0.035 0.064
0.14 0.256
0.14 0.256 LSB/mA
l
0.009 0.016
0.035 0.064
0.14 0.256
0.14 0.256 LSB/mA
l
0.09 0.156
0.09 0.156
0.09 0.156
0.09 0.156
Ω
l
0.09 0.156
0.09 0.156
0.09 0.156
0.09 0.156
Ω
SYMBOL
PARAMETER
CONDITIONS
MIN
VOUT
DAC Output Span
External Reference
Internal Reference
PSR
Power Supply Rejection
VCC = 3V ±10% or 5V ±10%
ISC
Short-Circuit Output Current (Note 6)
Sinking
Sourcing
VFS = VCC = 5.5V
Zero-Scale; VOUT shorted to VCC
Full-Scale; VOUT shorted to GND
l
l
VCC
Positive Supply Voltage
For Specified Performance
l
ICC
Supply Current (Note 7)
VCC = 3V, VREF = 2.5V, External Reference
VCC = 3V, Internal Reference
VCC = 5V, VREF = 2.5V, External Reference
VCC = 5V, Internal Reference
l
l
l
l
ISD
Supply Current in Power-Down Mode
(Note 7)
VCC = 5V, C-Grade, I-Grade
VCC = 5V, H-Grade
l
l
TYP
MAX
UNITS
0 to VREF
0 to 2.5
V
V
–80
dB
27
–28
48
–48
mA
mA
5.5
V
150
180
160
190
200
240
210
260
µA
µA
µA
µA
0.6
0.6
1.8
4
µA
µA
Power Supply
2.7
2640fc
For more information www.linear.com/LTC2640
5
LTC2640
electrical
characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VOUT unloaded unless otherwise specified.
LTC2640-LM12/-LM10/-LM8/-LZ12/-LZ10/-LZ8, LTC2640A-LM12/-LZ12 (VFS = 2.5V)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VCC
V
220
kΩ
Reference Input
Input Voltage Range
l
0
Resistance
l
160
Capacitance
IREF
190
7.5
Reference Current, Power-Down Mode
DAC Powered Down
l
pF
0.005
0.1
µA
1.250
1.260
V
Reference Output
Output Voltage
l
1.240
Reference Temperature Coefficient
±10
ppm/°C
Output Impedance
0.5
kΩ
Capacitive Load Driving
10
µF
2.5
mA
Short-Circuit Current
VCC = 5.5V; REF Shorted to GND
VIH
Digital Input High Voltage
VCC = 3.6V to 5.5V
VCC = 2.7V to 3.6V
l
l
VIL
Digital Input Low Voltage
VCC = 4.5V to 5.5V
VCC = 2.7V to 4.5V
l
l
0.8
0.6
V
V
ILK
Digital Input Leakage
VIN = GND to VCC
l
±1
µA
CIN
Digital Input Capacitance
(Note 8)
l
2.5
pF
Settling Time
VCC = 3V (Note 9)
±0.39% (±1LSB at 8-Bits)
±0.098% (±1LSB at 10-Bits)
±0.024% (±1LSB at 12-Bits)
Digital I/O
2.4
2
V
V
AC Performance
tS
en
3.2
3.8
4.1
µs
µs
µs
Voltage Output Slew Rate
1
V/µs
Capacitance Load Driving
500
pF
Glitch Impulse
At Mid-Scale Transition
2.1
nV•s
Multiplying Bandwidth
External Reference
300
kHz
Output Voltage Noise Density
At f = 1kHz, External Reference
At f = 10kHz, External Reference
At f = 1kHz, Internal Reference
At f = 10kHz, Internal Reference
140
130
160
150
nV√Hz
nV√Hz
nV√Hz
nV√Hz
Output Voltage Noise
0.1Hz to 10Hz, External Reference
0.1Hz to 10Hz, Internal Reference
0.1Hz to 200kHz, External Reference
0.1Hz to 200kHz, Internal Reference,
CREF = 0.33µF
20
20
650
670
µVP-P
µVP-P
µVP-P
µVP-P
2640fc
6
For more information www.linear.com/LTC2640
LTC2640
Timing
Characteristics
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V. (See Figure 1) (Note 8).
LTC2640-LM12/-LM10/-LM8/-LZ12/-LZ10/-LZ8, LTC2640A-LM12/-LZ12 (VFS = 2.5V)
SYMBOL
PARAMETER
CONDITIONS
t1
SDI Valid to SCK Setup
l
4
ns
t2
SDI Valid to SCK Hold
l
4
ns
t3
SCK High Time
l
9
ns
t4
SCK Low Time
l
9
ns
t5
CS/LD Pulse Width
l
10
ns
t6
LSB SCK High to CS/LD High
l
7
ns
t7
CS/LD Low to SCK High
l
7
ns
t9
CLR Pulse Width
l
20
ns
t10
CS/LD High to SCK Pos. Edge
l
7
SCK Frequency
MIN
50% Duty Cycle
TYP
MAX
UNITS
ns
50
l
MHz
electrical
characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 4.5V to 5.5V, VOUT unloaded unless otherwise specified.
LTC2640-HM12/-HM10/-HM8/-HZ12/-HZ10/-HZ8, LTC2640A-HM12/-HZ12 (VFS = 4.096V)
LTC2640-8
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
LTC2640-10
LTC2640-12
MAX MIN TYP MAX MIN TYP
LTC2640A-12
MAX MIN TYP
MAX
UNITS
DC Performance
Resolution
l
8
8
10
Monotonicity
VCC = 5V, Internal Ref. (Note 4) l
DNL
Differential
Nonlinearity
VCC = 5V, Internal Ref. (Note 4) l
±0.5
INL
Integral
Nonlinearity
VCC = 5V, Internal Ref. (Note 4) l
±0.05 ±0.5
ZSE
Zero-Scale Error
VCC = 5V, Internal Ref.,
Code = 0
l
0.5
VOS
Offset Error
VCC = 5V, Internal Ref. (Note 5) l
±0.5
VOSTC
VOS Temperature VCC = 5V, Internal Ref. (Note 5)
Coefficient
FSE
Full-Scale Error
VFSTC
Full-Scale Voltage VCC = 5V, Internal Ref. (Note 10)
Temperature
C-Grade
Coefficient
I-Grade
H-Grade
ROUT
10
12
12
Bits
12
±0.5
Bits
±1
±1
LSB
±0.2
±1
±1
±2.5
±0.5
±1
LSB
5
0.5
5
0.5
5
0.5
5
mV
±5
±0.5
±5
±0.5
±5
±0.5
±5
mV
±10
VCC = 5V, Internal Ref. (Note 11) l
12
±0.08 ±0.4
±10
±10
±10
±10
±0.08 ±0.4
±10
±10
±10
±10
±10
±0.08 ±0.4
±10
±10
±10
Load Regulation
VCC = 5V ±10%,
Internal Ref. Mid-Scale,
–10mA ≤ IOUT ≤ 10mA
l
0.006 0.01
0.022 0.04
0.09
DC Output
Impedance
VCC = 5V ±10%,
Internal Ref. Mid-Scale,
–10mA ≤ IOUT ≤ 10mA
l
0.09 0.156
0.09 0.156
0.09 0.156
0.16
µV/°C
±0.08 ±0.4
%FSR
±10
±10
±10
ppm/°C
ppm/°C
ppm/°C
0.09
0.16 LSB/mA
0.09 0.156
Ω
2640fc
For more information www.linear.com/LTC2640
7
LTC2640
electrical
characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 4.5V to 5.5V, VOUT unloaded unless otherwise specified.
LTC2640-HM12/-HM10/-HM8/-HZ12/-HZ10/-HZ8, LTC2640A-HM12/-HZ12 (VFS = 4.096V)
SYMBOL
PARAMETER
CONDITIONS
MIN
VOUT
DAC Output Span
External Reference
Internal Reference
PSR
Power Supply Rejection
VCC = 5V ±10%
ISC
Short-Circuit Output Current (Note 6)
Sinking
Sourcing
VFS = VCC = 5.5V
Zero-Scale; VOUT shorted to VCC
Full-Scale; VOUT shorted to GND
l
l
VCC
Positive Supply Voltage
For Specified Performance
l
ICC
Supply Current (Note 7)
VCC = 5V, VREF = 4.096V, External Reference
VCC = 5V, Internal Reference
l
l
ISD
Supply Current in Power-Down Mode
(Note 7)
VCC = 5V, C-Grade, I-Grade
VCC = 5V, H-Grade
l
l
TYP
MAX
UNITS
0 to VREF
0 to 4.096
V
V
–80
dB
27
–28
48
–48
mA
mA
5.5
V
160
200
220
270
µA
µA
0.6
0.6
1.8
4
µA
µA
VCC
V
220
kΩ
Power Supply
4.5
Reference Input
Input Voltage Range
l
0
Resistance
l
160
Capacitance
IREF
190
7.5
Reference Current, Power-Down
Mode
DAC Powered Down
l
pF
0.005
0.1
µA
2.048
2.064
V
Reference Output
Output Voltage
l
2.032
Reference Temperature Coefficient
±10
ppm/°C
Output Impedance
0.5
kΩ
Capacitive Load Driving
Short-Circuit Current
VCC = 5.5V; REF Shorted to GND
10
µF
4.3
mA
Digital I/O
VIH
Digital Input High Voltage
VIL
Digital Input Low Voltage
ILK
Digital Input Leakage
CIN
Digital Input Capacitance
Settling Time
VCC = 5V (Note 9)
±0.39% (±1LSB at 8 Bits)
±0.098% (±1LSB at 10 Bits)
±0.024% (±1LSB at 12 Bits)
l
2.4
V
0.8
V
VIN = GND to VCC
l
±1
µA
(Note 8)
l
2.5
pF
l
AC Performance
tS
3.7
4.2
4.6
µs
µs
µs
Voltage Output Slew Rate
1
V/µs
Capacitance Load Driving
500
pF
Glitch Impulse
At Mid-Scale Transition
3.0
nV•s
Multiplying Bandwidth
External Reference
300
kHz
2640fc
8
For more information www.linear.com/LTC2640
LTC2640
electrical
characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 4.5V to 5.5V, VOUT unloaded unless otherwise specified.
LTC2640-HM12/-HM10/-HM8/-HZ12/-HZ10/-HZ8, LTC2640A-HM12/-HZ12 (VFS = 4.096V)
SYMBOL
PARAMETER
CONDITIONS
en
Output Voltage Noise Density
At f = 1kHz, External Reference
At f = 10kHz, External Reference
At f = 1kHz, Internal Reference
At f = 10kHz, Internal Reference
MIN
TYP
140
130
210
200
MAX
nV√Hz
nV√Hz
nV√Hz
nV√Hz
UNITS
Output Voltage Noise
0.1Hz to 10Hz, External Reference
0.1Hz to 10Hz, Internal Reference
0.1Hz to 200kHz, External Reference
0.1Hz to 200kHz, Internal Reference,
CREF = 0.33µF
20
20
650
670
µVP-P
µVP-P
µVP-P
µVP-P
TIMING
Characteristics
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. VCC = 4.5V to 5.5V. (See Figure 1) (Note 8).
LTC2640-HM12/-HM10/-HM8/-HZ12/-HZ10/-HZ8, LTC2640A-HM12/-HZ12 (VFS = 4.096V)
SYMBOL
PARAMETER
t1
SDI Valid to SCK Setup
CONDITIONS
l
MIN
4
TYP
MAX
UNITS
ns
t2
SDI Valid to SCK Hold
l
4
ns
t3
SCK High Time
l
9
ns
t4
SCK Low Time
l
9
ns
t5
CS/LD Pulse Width
l
10
ns
t6
LSB SCK High to CS/LD High
l
7
ns
t7
CS/LD Low to SCK High
l
7
ns
t9
CLR Pulse Width
l
20
ns
t10
CS/LD High to SCK Pos. Edge
l
7
ns
SCK Frequency
50% Duty Cycle
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltages are with respect to GND.
Note 3: High temperatures degrade operating lifetimes. Operating lifetime
is derated at temperatures greater than 105°C.
Note 4: Linearity and monotonicity are defined from code kL to code
2N – 1, where N is the resolution and kL is given by kL = 0.016 • (2N/ VFS),
rounded to the nearest whole code. For VFS = 2.5V and N = 12, kL = 26
and linearity is defined from code 26 to code 4,095. For VFS = 4.096V
and N = 12, kL = 16 and linearity is defined from code 16 to code 4,095.
Note 5: Inferred from measurement at code 16 (LTC2640-12), code 4
(LTC2640-10) or code 1 (LTC2640-8), and at full-scale.
l
50
MHz
Note 6: This IC includes current limiting that is intended to protect the
device during momentary overload conditions. Junction temperature can
exceed the rated maximum during current limiting. Continuous operation
above the specified maximum operating junction temperature may impair
device reliability.
Note 7: Digital inputs at 0V or VCC.
Note 8: Guaranteed by design and not production tested.
Note 9: Internal Reference mode. DAC is stepped 1/4 scale to 3/4 scale
and 3/4 scale to 1/4 scale. Load is 2k in parallel with 100pF to GND.
Note 10: Temperature coefficient is calculated by dividing the maximum
change in output voltage by the specified temperature range.
Note 11: Full-scale error is determined using the reference voltage
measured at the REF pin.
2640fc
For more information www.linear.com/LTC2640
9
LTC2640
Typical Performance Characteristics
LTC2640-L12 (Internal Reference, VFS = 2.5V)
Integral Nonlinearity (INL)
1.0
1.0
VCC = 3V
0
0
2048
1024
3072
–1.0
4095
0
1024
CODE
2048
1.0
2.52
VCC = 3V
INL (NEG)
–0.5
FS OUTPUT VOLTAGE (V)
DNL (LSB)
0
DNL (POS)
0
DNL (NEG)
–0.5
25 50 75 100 125 150
TEMPERATURE (°C)
25 50 75 100 125 150
TEMPERATURE (°C)
Full-Scale Output Voltage
vs Temperature
0.5
INL (POS)
0
0
2640 G03
DNL vs Temperature
VCC = 3V
–1.0
–50 –25
1.240
–50 –25
4095
2640 G02
INL vs Temperature
0.5
3072
CODE
2640 G01
1.0
1.250
1.245
–0.5
0
VCC = 3V
1.255
VREF (V)
DNL (LSB)
INL (LSB)
1.260
VCC = 3V
0.5
–0.5
INL (LSB)
Reference Output Voltage
vs Temperature
Differential Nonlinearity (DNL)
0.5
–1.0
TA = 25°C, unless otherwise noted.
–1.0
–50 –25
0
2.51
2.50
2.49
2.48
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
2640 G04
VCC = 3V
0
25 50 75 100 125 150
TEMPERATURE (°C)
2640 G05
Settling to ±1LSB
2640 G06
Settling to ±1LSB
CS/LD
2V/DIV
3/4 SCALE TO 1/4 SCALE STEP
VCC = 3V, VFS = 2.5V
RL = 2k, CL = 100pF
AVERAGE OF 256 EVENTS
VOUT
1LSB/DIV
4.1µs
3.6µs
VOUT
1LSB/DIV
1/4 SCALE TO 3/4 SCALE STEP
VCC = 3V, VFS = 2.5V
RL = 2k, CL = 100pF
AVERAGE OF 256 EVENTS
CS/LD
2V/DIV
2µs/DIV
2µs/DIV
2640 G08
2640 G07
2640fc
10
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LTC2640
Typical Performance Characteristics
LTC2640-H12 (Internal Reference, VFS = 4.096V)
Integral Nonlinearity (INL)
1.0
1.0
VCC = 5V
–0.5
0
–0.5
0
2048
1024
3072
–1.0
4095
0
1024
2048
0
1.0
Full-Scale Output Voltage
vs Temperature
4.115
VCC = 5V
DNL (LSB)
INL (NEG)
–0.5
FS OUTPUT VOLTAGE (V)
0.5
INL (POS)
0
DNL (POS)
0
DNL (NEG)
–0.5
25 50 75 100 125 150
TEMPERATURE (°C)
25 50 75 100 125 150
TEMPERATURE (°C)
2640 G11
DNL vs Temperature
VCC = 5V
0
2.028
–50 –25
4095
2640 G10
INL vs Temperature
INL (LSB)
3072
CODE
2640 G09
–1.0
–50 –25
2.048
2.038
CODE
0.5
VCC = 5V
2.058
VREF (V)
DNL (LSB)
INL (LSB)
2.068
VCC = 5V
0.5
0
1.0
Reference Output Voltage
vs Temperature
Differential Nonlinearity (DNL)
0.5
–1.0
TA = 25°C, unless otherwise noted.
–1.0
–50 –25
0
4.105
4.095
4.085
4.075
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
2640 G12
VCC = 5V
0
25 50 75 100 125 150
TEMPERATURE (°C)
2640 G13
Settling to ±1LSB
2640 G14
Settling to ±1LSB
CS/LD
5V/DIV
VOUT
1LSB/DIV
4.6µs
3.9µs
VOUT
1LSB/DIV
1/4 SCALE TO 3/4 SCALE STEP
VCC = 5V, VFS = 4.095V
RL = 2k, CL = 100pF
AVERAGE OF 256 EVENTS
CS/LD
5V/DIV
2µs/DIV
3/4 SCALE TO 1/4 SCALE STEP
VCC = 5V, VFS = 4.095V
RL = 2k, CL = 100pF
AVERAGE OF 256 EVENTS
2µs/DIV
2640 G16
2640 G15
2640fc
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11
LTC2640
Typical Performance Characteristics
TA = 25°C, unless otherwise noted.
LTC2640-10
Integral Nonlinearity (INL)
1.0
Differential Nonlinearity (DNL)
1.0
VCC = 5V
VFS = 4.096V
INTERNAL REF.
0.5
DNL (LSB)
INL (LSB)
0.5
0
–0.5
–1.0
VCC = 5V
VFS = 4.096V
INTERNAL REF.
0
–0.5
0
512
256
768
–1.0
1023
0
512
256
CODE
2640 G17
LTC2640-8
Differential Nonlinearity (DNL)
0.50
VCC = 3V
VFS = 2.5V
INTERNAL REF.
DNL (LSB)
INL (LSB)
VCC = 3V
VFS = 2.5V
INTERNAL REF.
0.25
0.5
0
0
–0.25
–0.5
–1.0
0
128
64
192
–0.50
255
0
128
64
Load Regulation
Current Limiting
0.20
VCC = 5V (LTC2640-H)
VCC = 5V (LTC2640-L)
VCC = 3V (LTC2640-L)
0.15
VCC = 5V (LTC2640-H)
VCC = 5V (LTC2640-L)
VCC = 3V (LTC2640-L)
2
0
–2
OFFSET ERROR (mV)
∆VOUT (V)
ΔVOUT (mV)
4
0.05
0
–0.05
–4
–0.10
–6
–0.15
INTERNAL REF.
CODE = MIDSCALE
–8
–10
–30
Offset Error vs Temperature
3
0.10
2
–20
–10
0
10
IOUT (mA)
20
30
2630 G21
255
2640 G20
2640 G19
LTC2640
6
192
CODE
CODE
8
1023
2640 G18
Integral Nonlinearity (INL)
1.0
10
768
CODE
–0.20
–30
–10
0
10
IOUT (mA)
20
0
–1
–2
INTERNAL REF.
CODE = MIDSCALE
–20
1
30
2630 G22
–3
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
2640 G23
2640fc
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LTC2640
Typical Performance Characteristics
LTC2640
0.4
Gain Error vs VCC
0.2
0.1
0.0
–0.1
–0.2
EXTERNAL REF.
VREF = 2.5V
0.3
0.2
GAIN ERROR (%FSR)
GAIN ERROR (%FSR)
Large-Signal Response
Gain Error vs Temperature
0.4
EXTERNAL REF.
VREF = 2.5V
0.3
TA = 25°C, unless otherwise noted.
0.1
VOUT
0.5V/DIV
0.0
–0.1
–0.2
–0.3
–0.3
–0.4
2.5
3
3.5
4
4.5
5
VFS = VCC = 5V
1/4 SCALE TO 3/4 SCALE
–0.4
–50 –25
5.5
0
VCC (V)
25 50 75 100 125 150
TEMPERATURE (°C)
2640 G24
2µs/DIV
2640 G26
2640 G25
Headroom at Rails
vs Output Current
Power-On Reset Glitch
Mid-Scale-Glitch Impulse
5.0
LTC2640-L
4.0
VCC
2V/DIV
3.5
VOUT (V)
CS/LD
5V/DIV
LTC2640-H12, VCC = 5V:
3.0nV-s TYP
VOUT
5mV/DIV
ZERO-SCALE
LTC2640-L12, VCC = 3V:
2.1nV-s TYP
5V SOURCING
4.5
3V (LTC2640-L) SOURCING
3.0
2.5
2.0
1.5
VOUT
2mV/DIV
5V SINKING
1.0
0.5
0
200µs/DIV
2µs/DIV
2640 G28
2640 G27
3V (LTC2640-L) SINKING
0
1
2
3
4 5 6
IOUT (mA)
7
8
9
10
2640 G29
Supply Current vs Logic Voltage
Exiting Power-Down to Mid-Scale
1.4
SWEEP SCK, SDI, CS/LD
AND CLR BETWEEN
0V AND VCC
1.2
CS/LD
2V/DIV
Hardware CLR
VOUT
1V/DIV
ICC (mA)
1.0
VOUT
0.5V/DIV
0.8
VCC = 5V
0.6
0.4
VCC = 3V
(LTC2640-L)
0.2
LTC2640-H
4µs/DIV
2640 G30
0.0
0
1
3
2
LOGIC VOLTAGE (V)
CLR
5V/DIV
5
4
LTC2640-LZ
1µs/DIV
2640 G32
2640 G31
2640fc
For more information www.linear.com/LTC2640
13
LTC2640
Typical Performance Characteristics
LTC2640
Multiplying Bandwidth
Noise Voltage vs Frequency
0
500
–2
NOISE VOLTAGE (nV/√Hz)
–4
dB
–6
–8
–10
–12
–14 VCC = 5V
VREF(DC) = 2V
–16 VREF(AC) = 0.2VP-P
CODE = FULL SCALE
–18
1k
10k
100k
FREQUENCY (Hz)
TA = 25°C, unless otherwise noted.
1000k
2640 G33
0.1Hz to 10Hz Voltage Noise
INTERNAL REF.
CODE = MIDSCALE
LTC2640-L, VCC = 4V
INTERNAL REF.
CODE = MIDSCALE
400
300
LTC2640-H
(VCC = 5V)
200
LTC2640-L
(VCC = 4V)
100
0
100
10µV/DIV
10k
1k
100k
1M
1s/DIV
2640 G35
FREQUENCY (Hz)
2640 G34
Pin Functions
CS/LD (Pin 1): Serial Interface Chip Select/Load Input.
When CS/LD is low, SCK is enabled for shifting data on
SDI into the register. When CS/LD is taken high, SCK
is disabled and the specified command (see Table 1) is
executed.
SCK (Pin 2): Serial Interface Clock Input. CMOS and TTL
compatible.
SDI (Pin 3): Serial Interface Data Input. Data on SDI
is clocked into the DAC on the rising edge of SCK. The
LTC2640 accepts input word lengths of either 24- or 32-bits.
GND (Pin 4): Ground.
VCC (Pin 5): Supply Voltage Input. 2.7V ≤ VCC ≤ 5.5V
(LTC2640-L) or 4.5V ≤ VCC ≤ 5.5V (LTC2640-H). Bypass
to GND with a 0.1µF capacitor.
REF (Pin 6): Reference Voltage Input or Output. When
External Reference mode is selected, REF is an input
(0V ≤ VREF ≤ VCC) where the voltage supplied sets the
full-scale voltage. When Internal Reference is selected,
the 10ppm/°C 1.25V (LTC2640-L) or 2.048V (LTC2640-H)
internal reference is available at the pin. This output may
be bypassed to GND with up to 10µF (0.33µF is recommended), and must be buffered when driving external DC
load current.
VOUT (Pin 7): DAC Analog Voltage Output.
CLR (Pin 8, LTC2640-Z): Asynchronous Clear Input. A
logic low at this level-triggered input clears all registers
and causes the DAC voltage output to reset to Zero. CMOS
and TTL compatible.
REF_SEL (Pin 8, LTC2640-M): Selects default Reference
at power-up. Tie to VCC to select the Internal Reference,
or GND to select an External Reference. After power-up,
the logic state at this pin is ignored and the reference may
be changed only by software command.
2640fc
14
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LTC2640
Block Diagrams
LTC2640-Z
VCC
REF
INTERNAL
REFERENCE
SWITCH
SDI
SCK
CONTROL
DECODE LOGIC
24-BIT
SHIFT
REGISTER
RESISTOR
DIVIDER
DACREF
CS/LD
INPUT
REGISTER
DAC
REGISTER
CLR
DAC
VOUT
GND
LTC2640-M
VCC
REF
INTERNAL
REFERENCE
SDI
SCK
24-BIT
SHIFT
REGISTER
CONTROL
DECODE LOGIC
REF_SEL
SWITCH
RESISTOR
DIVIDER
DACREF
CS/LD
INPUT
REGISTER
DAC
REGISTER
DAC
VOUT
GND
2640 BD
2640fc
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15
LTC2640
Timing Diagram
t1
t2
SCK
t3
1
2
t6
t4
3
23
24
t10
SDI
t5
t7
CS/LD
2640 F01
Figure 1. Serial Interface Timing
2640fc
16
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LTC2640
Operation
The LTC2640-HM/LTC2640-LM provide an alternative
reset, setting the output to mid-scale when power is first
applied.
The LTC2640 is a family of single voltage-output DACs
in 8-lead ThinSOT packages. Each DAC can operate railto-rail using an external reference, or with its full-scale
voltage set by an integrated reference. 12 combinations of
accuracy (12-, 10-, and 8-bit), power-on reset value (zero
or mid-scale), and full-scale voltage (2.5V or 4.096V) are
available. The LTC2640 is controlled using a 3-wire SPI/
MICROWIRE compatible interface.
Default reference mode selection is described in the Reference Modes section.
Power Supply Sequencing
The voltage at REF (Pin 6) should be kept within the range
–0.3V ≤ VREF ≤ VCC + 0.3V (see Absolute Maximum Ratings). Particular care should be taken to observe these
limits during power supply turn-on and turn-off sequences,
when the voltage at VCC (Pin 5) is in transition.
Power-On Reset
The LTC2640-HZ/LTC2640-LZ clear the output to zeroscale when power is first applied, making system initialization consistent and repeatable.
Transfer Function
For some applications, downstream circuits are active
during DAC power-up, and may be sensitive to nonzero
outputs from the DAC during this time. The LTC2640
contains circuitry to reduce the power-on glitch: the
analog output typically rises less than 5mV above zeroscale during power on if the power supply is ramped
to 5V in 1ms or more. In general, the glitch amplitude
decreases as the power supply ramp time is increased.
See “Power-On Reset Glitch” in the Typical Performance
Characteristics section.
The digital-to-analog transfer function is:
 k 
VOUT(IDEAL) =  N  VREF
2 
where k is the decimal equivalent of the binary DAC input
code, N is the resolution, and VREF is either 2.5V (LTC2640LM/LTC2640-LZ) or 4.096V (LTC2640-HM/LTC2640-HZ)
when in Internal Reference mode, and the voltage at REF
(Pin 6) when in External Reference mode.
INPUT WORD (LTC2640-12)
COMMAND
C3
C2
C1
4 DON'T-CARE BITS
C0
X
X
X
X
DATA (12 BITS + 4 DON'T-CARE BITS)
D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
MSB
D0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
LSB
INPUT WORD (LTC2640-10)
COMMAND
C3
C2
C1
4 DON'T-CARE BITS
C0
X
X
X
X
DATA (10 BITS + 6 DON'T-CARE BITS)
D9
D8
D7
D6
D5
D4
D3
D2
D1
MSB
D0
X
LSB
INPUT WORD (LTC2640-8)
4 DON'T-CARE BITS
COMMAND
C3
C2
C1
C0
X
X
X
X
DATA (8 BITS + 8 DON'T-CARE BITS)
D7
MSB
D6
D5
D4
D3
D2
D1
D0
LSB
X
X
X
2640 F02
Figure 2. Command and Data Input Format
2640fc
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17
LTC2640
operation
Serial Interface
The CS/LD input is level triggered. When this input is
taken low, it acts as a chip-select signal, enabling the
SDI and SCK buffers and the input shift register. Data
(SDI input) is transferred at the next 24 rising SCK edges.
The 4-bit command, C3-C0, is loaded first, followed by
4 don’t-cares bits, and finally the 16-bit data word. The
data word comprises the 12-, 10- or 8-bit input code, ordered MSB-to-LSB, followed by 4, 6 or 8 don’t-cares bits
(LTC2640-12, LTC2640-10 and LTC2640-8 respectively;
see Figure 2). Data can only be transferred to the device
when the CS/LD signal is low, beginning on the first rising
edge of SCK. SCK may be high or low at the falling edge
of CS/LD. The rising edge of CS/LD ends the data transfer
and causes the device to execute the command specified
in the 24-bit input sequence. The complete sequence is
shown in Figure 3a.
The command (C3-C0) assignments are shown in Table 1.
The first three commands in the table consist of write and
update operations. A Write operation loads a 16-bit data
word from the 24-bit shift register into the input register.
In an Update operation, the input register is copied to the
DAC register and converted to an analog voltage at the
DAC output. Write to and Update combines the first two
commands. The Update operation also powers up the
DAC if it had been in power-down mode. The data path
and registers are shown in the Block Diagram.
Table 1. Command Codes
COMMAND*
transferred to the device first, followed by the 24-bit sequence described. Figure 3b shows the 32-bit sequence.
The 16-bit data word is ignored for all commands that do
not include a Write operation.
Reference Modes
For applications where an accurate external reference is not
available, the LTC2640 has a user-selectable, integrated
reference. The LTC2640-LM/LTC2640-LZ provide a fullscale output of 2.5V. The LTC2640-HM/LTC2640-HZ
provide a full-scale output of 4.096V. The internal reference
can be useful in applications where the supply voltage is
poorly regulated. Internal Reference mode can be selected
by using command 0110, and is the power-on default for
LTC2640-HZ/LTC2640-LZ, as well as for LTC2640-HM/
LTC2640-LM when REF_SEL is tied high.
The 10ppm/°C, 1.25V (LTC2640-LM/LTC2640-LZ) or
2.048V (LTC2640-HM/LTC2640-HZ) internal reference
is available at the REF pin. Adding bypass capacitance
to the REF pin will improve noise performance; 0.33µF
is recommended, and up to 10µF can be driven without
oscillation. This output must be buffered when driving an
external DC load current.
Alternatively, the DAC can operate in External Reference
mode using command 0111. In this mode, an input voltage
supplied externally to the REF pin provides the reference
(0V ≤ VREF ≤ VCC) and the supply current is reduced. External
Reference mode is the power-on default for LTC2640-HM/
LTC2640-LM when REF_SEL is tied low.
C3
C2
C1
C0
0
0
0
0
Write to Input Register
0
0
0
1
Update (Power-Up) DAC Register
0
0
1
1
Write to and Update (Power-Up) DAC Register
0
1
0
0
Power Down
0
1
1
0
Select Internal Reference
Power-Down Mode
0
1
1
1
Select External Reference
For power-constrained applications, the LTC2640’s powerdown mode can be used to reduce the supply current
whenever the DAC output is not needed. When in powerdown, the buffer amplifier, bias circuit, and reference
circuit are disabled and draw essentially zero current. The
DAC output is put into a HIGH-impedance state, and the
output pin is passively pulled to ground through a 200k
*Command codes not shown are reserved and should not be used
While the minimum input sequence is 24-bits, it may
optionally be extended to 32-bits to accommodate microprocessors that have a minimum word width of 16-bits
(2-bytes). To use the 32-bit width, 8 don’t-cares bits are
The reference mode of LTC2640-HZ/LTC2640-LZ can be
changed only by software command. The same is true for
LTC2640-HM/LTC2640-LM after power-on, after which
the logic state on REF_SEL is ignored.
2640fc
18
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LTC2640
Operation
resistor. Input and DAC register contents are not disturbed
during power-down.
The DAC can be put into power-down mode by using
command 0100. The supply current is reduced to 1.8µA
maximum (C and I grades) and the REF pin becomes HIGH
impedance (typically > 1GΩ).
Normal operation resumes after executing any command
that includes a DAC update, as shown in Table 1. The DAC
is powered up and its voltage output is updated. Normal
settling is delayed while the bias, reference, and amplifier circuits are re-enabled. When the REF pin output is
bypassed to GND with 1nF or less, the power-up delay
time is 20µs for settling to 12-bits. This delay increases
to 200µs for 0.33µF, and 10ms for 10µF.
Voltage Output
The LTC2640’s integrated rail-to-rail amplifier has guaranteed load regulation when sourcing or sinking up to
10mA at 5V, and 5mA at 3V.
Load regulation is a measure of the amplifier’s ability to
maintain the rated voltage accuracy over a wide range of
load current. The measured change in output voltage per
change in forced load current is expressed in LSB/mA.
DC output impedance is equivalent to load regulation, and
may be derived from it by simply calculating a change in
units from LSB/mA to ohms. The amplifier’s DC output
impedance is 0.1Ω when driving a load well away from
the rails.
When drawing a load current from either rail, the output
voltage headroom with respect to that rail is limited by
the 50Ω typical channel resistance of the output devices
(e.g., when sinking 1mA, the minimum output voltage is
50Ω • 1mA, or 50mV). See the graph “Headroom at Rails
vs. Output Current” in the Typical Performance Characteristics section.
The amplifier is stable driving capacitive loads of up to
500pF.
Rail-to-Rail Output Considerations
In any rail-to-rail voltage output device, the output is limited
to voltages within the supply range.
Since the analog output of the DAC cannot go below ground,
it may limit the lowest codes, as shown in Figure 4b.
Similarly, limiting can occur near full-scale when the REF
pin is tied to VCC. If VREF = VCC and the DAC full-scale error
(FSE) is positive, the output for the highest codes limits
at VCC, as shown in Figure 4c. No full-scale limiting can
occur if VREF is less than VCC – FSE.
Offset and linearity are defined and tested over the region
of the DAC transfer function where no output limiting can
occur.
Board Layout
The PC board should have separate areas for the analog and
digital sections of the circuit. A single, solid ground plane
should be used, with analog and digital signals carefully
routed over separate areas of the plane. This keeps digital
signals away from sensitive analog signals and minimizes
the interaction between digital ground currents and the
analog section of the ground plane. The resistance from
the LTC2640 GND pin to the ground plane should be as
low as possible. Resistance here will add directly to the
effective DC output impedance of the device (typically
0.1Ω). Note that the LTC2640 is no more susceptible to
this effect than any other parts of this type; on the contrary, it allows layout-based performance improvements
to shine rather than limiting attainable performance with
excessive internal resistance.
Another technique for minimizing errors is to use a separate power ground return trace on another board layer.
The trace should run between the point where the power
supply is connected to the board and the DAC ground pin.
Thus the DAC ground pin becomes the common point for
analog ground, digital ground, and power ground. When
the LTC2640 is sinking large currents, this current flows
out the ground pin and directly to the power ground trace
without affecting the analog ground plane voltage.
It is sometimes necessary to interrupt the ground plane
to confine digital ground currents to the digital portion of
the plane. When doing this, make the gap in the plane only
as long as it needs to be to serve its purpose and ensure
that no traces cross over the gap.
2640fc
For more information www.linear.com/LTC2640
19
20
SDI
SCK
CS/LD
X
1
X
2
X
For more information www.linear.com/LTC2640
X
4
X
5
X
8 DON’T-CARE BITS
3
6
C3
SDI
C2
2
C1
3
X
7
X
8
C2
10
C1
11
X
7
X
8
D11
9
D10
10
D9
D8
12
D7
13
D6
14
24-BIT INPUT WORD
11
D5
15
D3
17
DATA WORD
D4
16
D2
18
C0
12
X
14
X
15
X
16
32-BIT INPUT WORD
4 DON’T-CARE BITS
X
13
D11
17
D10
18
D9
19
D8
20
D7
21
D6
22
D5
23
19
D1
24
D3
25
D0
20
DATA WORD
D4
Figure 3b. LTC2640-12 32-Bit Load Sequence
LTC2640-10 SDI Data Word: 10-Bit Input Code + 6 Don’t-Cares Bits;
LTC2640-8 SDI Data Word: 8-Bit Input Code + 8 Don’t-Cares Bits
COMMAND WORD
9
X
6
4 DON’T-CARE BITS
X
5
Figure 3a. LTC2640-12 24-Bit Load Sequence (Minimum Input Word).
LTC2640-10 SDI Data Word: 10-Bit Input Code + 6 Don’t-Cares Bits;
LTC2640-8 SDI Data Word: 8-Bit Input Code + 8 Don’t-Cares Bits
4
C0
C3
COMMAND WORD
1
SCK
CS/LD
D2
26
X
21
D1
27
X
22
D0
28
X
23
X
29
X
24
X
30
31
X
2640 F03a
X
32
2640 F03b
LTC2640
Operation
2640fc
LTC2640
operation
VREF = VCC
POSITIVE
FSE
VREF = VCC
OUTPUT
VOLTAGE
OUTPUT
VOLTAGE
INPUT CODE
(c)
OUTPUT
VOLTAGE
0V
NEGATIVE
OFFSET
0V
0
2,048
INPUT CODE
(a)
2640 F04
4,095
INPUT CODE
(b)
Figure 4. Effects of Rail-to-Rail Operation on a DAC Transfer Curve (Shown for 12-Bits)
(a) Overall Transfer Function
(b) Effect of Negative Offset for Codes Near Zero
(c) Effect of Positive Full-Scale Error for Codes Near Full-Scale
2640fc
For more information www.linear.com/LTC2640
21
LTC2640
Package Description
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
TS8 Package
8-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1637 Rev A)
0.40
MAX
2.90 BSC
(NOTE 4)
0.65
REF
1.22 REF
1.4 MIN
3.85 MAX 2.62 REF
2.80 BSC
1.50 – 1.75
(NOTE 4)
PIN ONE ID
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
0.22 – 0.36
8 PLCS (NOTE 3)
0.65 BSC
0.80 – 0.90
0.20 BSC
0.01 – 0.10
1.00 MAX
DATUM ‘A’
0.30 – 0.50 REF
0.09 – 0.20
(NOTE 3)
1.95 BSC
TS8 TSOT-23 0710 REV A
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. JEDEC PACKAGE REFERENCE IS MO-193
2640fc
22
For more information www.linear.com/LTC2640
LTC2640
Revision History
(Revision history begins at Rev C)
REV
DATE
DESCRIPTION
C
10/13
Updated TS8 package drawing to Rev A.
PAGE NUMBER
22
2640fc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection
of its circuits
as described
herein will not infringe on existing patent rights.
For more
information
www.linear.com/LTC2640
23
LTC2640
Typical Application
Programmable ±5V Output
5V
5V
4
0.1µF
3
SERIAL
BUS
5 6
VCC REF
8
REF_SEL
3 SDI
LTC2640A VOUT 7
2
SCK -LM12
1
–
5
0.1µF
LTC2054
+
1
2
CS/LD GND
4
10V
8
M9
9 M3
10
M1
1
P1
2
P3
3
P9
0.1µF
7
VCC
LT1991
VEE
4
REF
OUT
6
VOUT = ±5V
5
0.1µF
–10V
2640 TA03
Related Parts
PART NUMBER
DESCRIPTION
COMMENTS
LTC1663
Single 10-Bit VOUT DAC in SOT-23
VCC = 2.7V to 5.5V, 60µA, Internal Reference, SMBus Interface
LTC1669
Single 10-Bit VOUT DAC in SOT-23
VCC = 2.7V to 5.5V, 60µA, Internal Reference, I2C Interface
LTC2360/LTC2362/
LTC2365/LTC2366
12-Bit SAR ADCs in TSOT23-6/TSOT23-8 Packages
100ksps/250ksps/500ksps/1Msps/3Msps Output Rates
LTC2450/LTC2452
16-Bit Single-Ended/Differential Delta Sigma ADCs
SPI Interface, Tiny DFN Packages, 60Hz Output Rate
LTC2451/LTC2453
16-Bit Single-Ended/Differential Delta Sigma ADCs
I2C Interface, Tiny DFN and TSOT23-8 Packages, 60Hz Output Rate
LTC2600/LTC2610/LTC2620 Octal 16-/14-/12-Bit VOUT DACs in 16-Lead SSOP
250µA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output,
SPI Serial Interface
LTC2601/LTC2611/LTC2621 Single 16-/14-/12-Bit VOUT DACs in 10-Lead DFN
300µA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output,
SPI Serial Interface
LTC2602/LTC2612/LTC2622 Dual 16-/14-/12-Bit VOUT DACs in 8-Lead MSOP
300µA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output,
SPI Serial Interface
LTC2604/LTC2614/LTC2624 Quad 16-/14-/12-Bit VOUT DACs in 16-Lead SSOP
250µA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output,
SPI Serial Interface
LTC2605/LTC2615/LTC2625 Octal 16-/14-/12-Bit VOUT DACs with I2C Interface
250µA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output,
I2C Interface
LTC2606/LTC2616/LTC2626 Single 16-/14-/12-Bit VOUT DACs with I2C Interface
270µA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output,
I2C Interface
LTC2609/LTC2619/LTC2629 Quad 16-/14-/12-Bit VOUT DACs with I2C Interface
250µA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output with
Separate VREF Pins for Each DAC
LTC2630
Single 12-/10-/8-Bit VOUT DACs with 10ppm/°C
Reference in SC70
180µA per DAC, 2.7V to 5.5V Supply Range, 10ppm/°C Reference,
Rail-to-Rail Output, SPI Interface
LTC2631
Single 12-/10-/8-Bit I2C VOUT DACs with 10ppm/°C
Reference in ThinSOT
180µA per DAC, 2.7V to 5.5V Supply Range, 10ppm/°C Reference,
Selectable External Ref. Mode, Rail-to-Rail Output, I2C Interface
2640fc
24 Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
For more information www.linear.com/LTC2640
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com/LTC2640
LT 1013 REV C • PRINTED IN USA
 LINEAR TECHNOLOGY CORPORATION 2008