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Supplementary Material
Multiple silicon nanowire complementary tunnel transistors for ultralow-power
flexible logic applications
M. Lee,1 Y. Jeon,1 J.-C. Jung,2 S.-M. Koo,2,a) and S. Kim1,b)
1
Department of Electrical Engineering, Korea University, Anam-dong, Seongbuk-gu, Seoul
136-713, Korea
2
Department of Electronic Materials Engineering, Kwangwoon University, Wolgye-dong,
Nowon-gu, Seoul 139-701, Korea
Electronic mail: a) [email protected], b) [email protected]
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1. Transfer printing and device fabrication
The fabrication of the flexible silicon nanowire (SiNW) tunnel field-effect transistor
(TFET) on a plastic substrate begins with the transfer of the as-fabricated p+-i-n+ SiNWs from
a donor Si chip to a receiver plastic substrate (see Figs. S1 and S2). A 50-nm-thick ultraviolet
(UV)-curable resin (Q-sys, NIR Q1) with a low viscosity of 6.5 cps at 25˚C, which is a liquid
photopolymer that cures when exposed to UV light, was laminated on the plastic by a spincoating process (Fig. S1(a)). Then, the receiver plastic coated with the UV-curable resin was
brought into conformal contact with a donor Si chip containing the SiNWs under controlled
temperature and contact pressure (Fig S1(b)). Since the viscosity of the resin used for the
transfer of the SiNWs is low, the SiNWs are anchored on the surface of the plastic, not on the
surface of the resin. Subsequently, after the resin layer was cured by exposing it to UV light
(Fig. S1(b)), the receiver plastic was peeled off from the donor Si chip, bringing the SiNWs
with the plastic, as the crystalline connections to the supporting post at the ends of the SiNWs
was broken (Figs. S1(c) and S2(b)). Finally, the resin layer was completely removed by
oxygen plasma etching and/or ethanol solution, leaving the SiNWs on the plastic in organized
arrays by the van der Waals interactions with the surface of the plastic (Figs. S1(d) and S2(c)).
To make the representative p+-i-n+ SiNW on the plastic into contact with the metal source
and drain electrodes, the patterned source and drain regions of the p+-i-n+ SiNW were
deposited by thermal evaporation using aluminum (Al)/gold (Au) (80/20 nm) metals after
buffered hydrogen fluoride (BHF) treatment and subsequent rinsing in deionized (DI) water
in order to remove native oxides and promote the formation of ohmic contacts. After the liftoff process, a 10-nm-thick Al2O3 gate dielectric layer was deposited by an atomic layer
deposition (ALD) technique using trimethylaluminium (TMA) and H2O at 150˚C. In the final
step, the top-gate electrode (Al: 150 nm) was formed by photolithography, thermal
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evaporation and lift-off processes, to complete the fabrication of the p+-i-n+ SiNW TFET on
the plastic substrate.
Figure S1. Method of transferring as-fabricated SiNWs from donor Si chip to plastic substrates. (a) Laminating
an UV-curable resin on the plastic by a spin-coating process. (b) Contacting the receiver plastic coated with the
resin with the donor Si chip containing the SiNWs under controlled temperature and contact pressure, and
solidifying the resin layer by UV light exposure. (c) Peeling the receiver plastic from the donor Si chip, bringing
SiNWs with the plastic, as the crystalline connections to the supporting post at the ends of the SiNWs was
broken. (d) Removing the resin layer by oxygen plasma etching and/or ethanol solution, leaving the SiNWs on
the plastic in organized arrays by the van der Waals interactions with the surface of the plastic.
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Figure S2. (a) Photographs illustrating direct transfer method. Entire array of the SiNWs is successfully
transferred from a donor Si chip to a plastic substrate, with a few broken SiNWs arising from mechanical forces
during the transfer process. (b-c) Optical images illustrating as-transferred SiNWs on the plastic substrate. The
comparision between the images taken (b) before and (c) after the removal of the resin shows that the SiNWs
are efficiently transferred onto the plastic and anchored on it by surface adhesion.
2. Device simulation
The simulation was performed for a two-dimensional (2-D) device structure, which had
been cut horizontally along the channel transport direction of the SiNW TFETs, using
Silvaco Atlas, version 5.14.0.R, which uses a non-local Hurkx band-to-band tunneling
(BTBT) model.S1 The non-local BTBT model has a more physical basis compared with local
BTBT model and does not depend on the electrical field local to each mesh point and
calculates tunneling-induced generation-recombination rate more accurately, taking into
account the spatial variation of the energy bands.S2 Fermi-Dirac statistics were assumed and
Shockley-Read-Hall (SRH) recombination and drift-diffusion models were used to model
carrier transport. Bandgap narrowing was applied, while gate leakage was ignored. Only the
n-type devices were studied: therefore, we refer to the p+-doped region as the source and the
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n- and/or n+-doped region as the drain. Three different device structures were considered. The
first (Reference Device) uses a symmetric source-drain doping: 1×1020 cm-3 p-type for the
source, and the same but n-type for the drain. The second (Device A) employs an asymmetric
source-drain doping: 1×1020 cm-3 p-type for the source, and 1×1017 ~ 1×1020 cm-3 n-type for
the drain. The third (Device B) incorporates a gate-to-drain underlap: gate underlap length
from 0 to 2 μm. In all simulations, the channel (2 μm in length) was p-type doped with a
uniform doping concentration of 1×1015 cm-3 and a graded junction profiles were used for the
source and drain, where the doping concentration is reduced from the source and drain
regions to the channel region by 2 nm/dec. A high-κ gate dielectric Al2O3 (10 nm in thickness)
with dielectric constant of 8.4 and Al metal gate with a work function of 4.28 eV were used.
To better understand the effect of the drain doping concentration (from 1×1017 to 1×1020
cm-3 for Device A) and gate underlap length (from 0 to 2 µm for Device B) on the ambipolar
conduction, we have performed further experimental characterization and numerical
simulations. In addition, in order to study the mechanical properties of the devices, we have
also performed systematic tests by bending the flexible plastic substrate mechanically along
the channel transport direction to achieve convex (or tensile) and concave (or compressive)
surface strain values of 0.67%. The applied strain value was estimated by using the radius of
bending curvature and the thickness of the plastic substrate. Fig. S3(a) shows the normalized
drain current (log(Ids/Vgs2)) as a function of the inverse gate voltage (Vgs-1) obtained from the
experimental data for the different devices in the flat and strained states. In this figure,
regions I and II are the regimes where the experimental results follow Kane’s model with
ambipolar- and on-state BTBT behavior, respectively,S3 whereas region III represents offstate leakage of the devices. In region II, the slopes of the dotted lines for the devices in the
flat and strained states are almost identical, indicating that there is no significant change in
the on-state BTBT generation rate after the application of surface strains (up to 0.67%) on the
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plastic substrate. Note that the slope of the straight line is related to the tunneling reduced
effective mass and the bandgap of the material, such that an increase in the slope implies a
decrease in the BTBT generation rate. In region III, it can also be seen that the off-state
leakage of the devices is not significantly affected by applied strains of up to 0.67% as well.
In region I, the Reference device clearly follows Kane’s model with ambipolar BTBT
behavior. The slope of the dotted line decreases with increasing drain voltage because it
moves the turn-on point of the ambipolar tunneling current toward a more positive value in
gate voltage, due to the influence of the drain potential on the ambipolar tunnel junction. In
contrast, both Device A and B show the clear suppression of ambipolar conduction,
independent of the applied drain voltage. The numerical simulation results are shown in Fig.
S3(b) for the corresponding structures of the Reference device, Device A, and Device B. It
shows qualitatively the same tendency as the experimental data, but it allows to examine the
effect of drain doping concentration and gate underlap dimension on the ambipolar I-V
characteristics in further detail. For Device A, the ambipolar conduction can be suppressed
for drain doping concentration of less than 1×1018 cm-3. In the case of Device B, a rather
small gate underlap of ~20 nm results in the complete suppression of ambipolar conduction
which, in turn, requires the sacrifice of the off-state leakage.
Fig. S4 shows the 2-D electron current density distribution profiles across the channel in
the ambipolar state (Vgs=-3 V and Vds=1 V) for Device A with various drain doping
concentrations from 1×1017 to 1×1020 cm-3, and for Device B with various gate underlap
lengths from 0 to 2 µm, respectively. In the case of Device A, as the drain doping
concentration decreases from 1×1020 to 1×1017 cm-3, the electron current density in the n+
drain of the channel surface gradually decreases from ~0.1 A/cm2 down to ~0.03 A/cm2, as
shown in Fig. S4(a). For drain doping levels below 1×1018 cm-3, the BTBT electrons from the
channel to the drain region are effectively blocked and, consequently, the ambipolar
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conduction is completely turned off at a drain doping level of 1×1017 cm-3. On the other hand,
as clearly shown in Fig. S4(b), Device B also exhibits a drastic decrease in the electron
current density from ~0.1 A/cm2 down to ~0.01 A/cm2 as the gate underlap length increases
from 0 to 2 µm, which implies that the ambipolar tunneling can be effectively controlled by
making a slight change in the gate underlap dimension. Note that as long as a small gate
underlap length of ~20 nm is present, hardly the electrons tunnel from the channel to the
drain region, thereby suppressing the ambipolar conduction of the device.
Figure S3. Experimental measurement and simulation results for different SiNW TFETs in flat and strained
states. a) Normalized drain current (log(Ids/Vgs2)) as a function of the inverse gate voltage (Vgs-1) obtained from
the experimental data for the different devices in the flat and strained states. Regions I and II are the regimes
where the experimental results follow Kane’s model with ambipolar- and on-state BTBT behavior, respectively,
whereas region III represents off-state leakage of the devices. b) Corresponding simulation results showing the
effect of the drain doping concentrations and gate underlap dimensions on the ambipolar conduction.
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Figure S4. 2-D electron current density JTUN distribution profiles across the channel (Vgs=-3 V and Vds=1 V). (a)
Device A with various drain doping concentrations from 1×1017 to 1×1020 cm-3. (b) Device B with various gate
underlap lengths from 0 to 2 µm.
3. Multiple SiNW fabrication
Fig. S5 schematically summarizes the key process steps to generate the multiple SiNWs
(p+-n0-n--n+ SiNWs for n-TFET and n+-p0-p--p+ SiNWs for p-TFET) from bulk Si wafers by
using a fully CMOS-compatible top-down route. Note that the crystalline connections to the
supporting posts at the end of the SiNWs are not shown to provide clarity. With an
oxide/nitride stack defining the 400-nm-wide active Si lines (Fig. S5(a)), the Si substrate was
etched anisotropically until the desired trench depth was reached (Fig. S5(b)). Subsequently,
the wafer was dipped in tetramethylammonium hydroxide (TMAH, (CH3)4NOH; 25% diluted
in water) solution to generate the triangular Si wires (Fig. S5(c)). Thermal oxidation of the Si
wires was subsequently carried out in a wet ambient to reduce the size of the SiNWs down to
sub-100 nm (Fig. S5(d)). After the nitride film was completely stripped in hot phosphoric
acid, n- and p-wells on the SiNWs (for n- and p-TFET, respectively) were separately formed
by a conventional twin-well process, where masked P+ and B+ ion implantations were
performed with a dose of 1×1012 cm-2 at ion energies of 40 and 15 keV, respectively (Fig.
S5(e)), and then Si wafer was annealed at 1100˚C for 90 min in a nitrogen ambient. In order
to form the lightly doped drain (LDD) extension regions (n- drain for n-TFET and p- drain for
p-TFET), each of the n- and p- drain extension regions was formed separately by masked ion
implantations (As+ 1×1013 cm-2 at 80 keV and BF2+ 1×1013 cm-2 at 50 keV, respectively), in
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an attempt to suppress the ambipolar conduction (Fig. S5(f)). Additionally, in order to make
source tunnel junction and drain contact regions of the SiNWs doped heavily (p+ source/n+
drain for n-TFET and n+ source/p+ drain for p-TFET), As+ and BF2+ ions with a dose of
5×1015 cm-2 were implanted as n- and p-type dopants at ion energies of 80 and 50 keV,
respectively, after the source and drain contact regions in the SiNWs were defined in turn
with separate photomasks (Fig. S5(g)). Next, the wafer was firstly annealed at 900˚C for 60
min in nitrogen ambient, followed by rapid thermal annealing (RTA) at 1000˚C for 10 s in
order to activate the implanted dopants with uniform diffusion and eliminate defects. By
removing the surrounding oxide using buffered oxide etchant (BOE) solution, the SiNWs
were released from the Si substrate and, thus, the freestanding multiple p+-n0-n--n+ SiNWs
and n+-p0-p--p+ SiNWs for n- and p-TFET were formed (Fig. S5(h)).
Shown in Fig. S6 is the SEM image of the multiple SiNWs taken after size reduction
oxidation of the Si wires and the subsequent nitride strip. Note that, in order to distinguish the
clear SiNWs from the surrounding oxide layer, chemical staining in BOE solution was
performed after deposition of 150-nm-thick polycrystalline silicon. Clearly, the multiple
SiNWs have dimensions of approximately 100 nm and are completely surrounded by the
oxide layer. Notably, the multiple SiNWs are electrically isolated from the Si substrate and
can be easily transferred onto flexible plastic substrates. Fig. S7 shows the secondary ion mas
spectroscopy (SIMS) analysis for the arsenic and boron profiles in SiNWs after the thermal
steps. It is confirmed that the boron and arsenic concentrations in the p+ source, n- drain
extension and n+ drain contact regions of the SiNW n-TFET are approximately at the
1020~1021, 1017~1018 and 1020~1021 cm-3 levels, respectively (Fig. S7(a)). In the case of the
SiNW p-TFET, the arsenic and boron concentrations in the n+ source, p- drain extension and
p+ drain contact regions are also approximately at the 1020~1021, 1017~1018 and 1020~1021 cm3
levels, respectively (Fig. S7(b)).
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Figure S5. Key process steps to generate the multiple SiNWs from bulk p-type (100) Si wafers. (a) Definition of
400-nm-wide Si active lines on a oxide/nitride stack (10/150 nm). (b) Si trench etching using the nitride film as
a hard mask. (c) Crystallographic wet-chemical etching in 25 wt.% TMAH solution to generate the triangular Si
wires. (d) Thermal oxidation of the Si wires to reduce the dimension of the SiNWs down to sub-100 nm. (e)
Masked n- and p-well implantation doping in the SiNWs (P+ 1×1012 cm-2 at 40 keV and B+ 1×1012 cm-2 at 15
keV, respectively), followed by annealing at 1100˚C for 90 min in a nitrogen ambient. (f) Masked n- and pimplantation doping of the SiNWs (As+ 1×1013 cm-2 at 80 keV and BF2+ 1×1013 cm-2 at 50 keV, respectively) to
form the LDD regions in the SiNWs, in an attempt to suppress the ambipolar conduction in TFETs. (g) Masked
n+ and p+ implantation doping of the SiNWs (As+ 5×1015 cm-2 at 80 keV and BF2+ 5×1015 cm-2 at 50 keV,
respectively) to form the heavily doped source and drain contact regions in the SiNWs, followed by annealing at
900˚C for 60 min and RTA 1000˚C for 10 s in a nitrogen ambient to activate the implanted dopants with
uniform diffusion and eliminate defects. (h) Release of the SiNWs via wet-chemical etching in BOE solution to
form the freestanding multiple p+-n0-n--n+ SiNWs and n+-p0-p--p+ SiNWs for n- and p-TFET, respectively.
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Figure S6. SEM images of the multiple SiNWs taken after size reduction oxidation of the Si wires and the
subsequent nitride strip. Note that, in order to distinguish the clear SiNWs from the surrounding oxide layer,
chemical staining in BOE solution was performed after polysilicon deposition.
Figure S7. SIMS analysis. (a) Boron (BF2+ 5×1015 cm-2 at 50 keV) and arsenic (As+ 1×1013/5×1015 cm-2 at 80
keV) profiles for p+ source and n-/n+ drain extension/contact regions in the SiNW n-TFET, respectively. (b)
Arsenic (As+ 5×1015 cm-2 at 80 keV) and boron (BF2+ 1×1013/5×1015 cm-2 at 50 keV) profiles for n+ source and
p-/p+ drain extension/contact regions in the SiNW p-TFET, respectively. The profiles were analyzed after
activation annealing at 900˚C for 60 min and RTA at 1000˚C for 10 s. The analysis was performed with a
double-focusing magnetic sector mass spectrometer (CAMECA IMS-7f) using a 10 kV Cs+ primary beam for
arsenic and a 10 kV O2+ primary beam for boron.
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References
S1
G. A. M. Hurkx, D. B. M. Klaassen, and M. P. G. Knuvers, IEEE Trans. Electron Devices
39, 331 (1992).
S2
Atlas User’s Manual, Silvaco Int., Santa Clara, CA, May 26, (2006).
S3
The BTBT generation rate GBTBT, known as Kane’s model, is given as:
Gbtbt  Akane E
2
1 / 2
g
 Bkane E g3 / 2 

exp  





(S1a)
q 2 m01/ 2
 m01/ 2
Akane 
, Bkane 
18  2
2q
(S1b)
where m0 is the tunneling reduced effective mass, Eg is the bandgap of the material, and the
constant q and ħ are the electron charge and the reduced Planck’s constant, respectively.
Rewriting equation (S1) in terms of Vgs, for Ids ∞ Gbtbt, we get
 B E 3/ 2 
I ds  Akane D 2 E g1/ 2Vgs2 exp   kane g 

DV gs 

(S2)
where the constant D obviously parameterizes the influence of the gate capacitance and other
effects relating to the gate control of the maximum electric field across the tunneling
junction, yielding ξ=DVgs.
Taking the natural log of the normalized drain current (Ids /Vgs2), we get
 I 
B' '
log  ds2   log( A' ' ) 
V 
Vgs
 gs 
A' ' 
B E
Akane  D 2
, B' '  kane g
1/ 2
D
Eg
(S3a)
3/ 2
(S3b)
Thus, plotting log(Ids /Vgs2) as a function of Vgs-1, one would expect a straight line with a slope
determined by the value of B”, while the intercept giving A” value.
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