Download P10345 – Automated TFT Noise Characterization Platform Kendell

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P10345 – Automated TFT Noise
Characterization Platform
Kendell Clark1, Stephen Marshall1, Carmen Parisi1, James Spoth2, Ryan Vaughn3
Faculty Advisor: Dr. Robert Bowman1
1)Department of Electrical Engineering, Rochester Institute of Technology 2)Department of Computer Engineering,
Rochester Institute of Technology 3)Department of Mechanical Engineering, Rochester Institute of Technology
Abstract—A low noise, automated measurement environment
is constructed for the purpose of characterizing on wafer devices.
Novel analog circuitry provides both the low noise bias
capabilities needed for device characterization as well as the low
noise amplification of low level signals. Custom digital hardware
and LabVIEW software are used to control the analog circuitry
and measurement automation. The entire project is encased in a
RF/EMI shielded container to reduce the effect of external noise
coupling into the sensitive signal path and is designed to fit over
an existed wafer probe station.
Index Terms— Noise Measurement, RF/EMI Shielding, Low
Noise Amplification, Low Noise Biasing, 1/f Noise, Current
Source
I. INTRODUCTION
The purpose of the Automated TFT Noise Characterization
Platform is to provide researchers a fast and easy way of
characterizing the noise in on-wafer devices by providing an
electrically quiet environment and automation of connection
switching, instrument control, and data acquisition.
Major competing products retail for over one million dollars
and are marketed to large corporations with an interest in
characterizing thousands of devices of widely varying types
for use in R&D or production testing. Small research budgets
do not allow for purchase of these expensive systems, nor do
they require the extensive functionality provided. The
Characterization Platform aims to address the needs of small
research groups on a low budget, interested in retrofitting an
existing, low-cost wafer probe station with a low-noise
measurement environment.
There are many key features and design components of the
project. One of these is a shielded container which reduces the
influence of environmental RF and EMI noise on the measure.
Another component is a low noise amplifier designed to
provide gain to very low level measurement signals inside the
shielded environment. Low noise current and voltage sources
to bias the device under test without contributing additional
noise are also incorporated into the platform. The bias
circuitry and device measurement process is user controlled
through a LabVIEW interface and includes a high resolution
mode for the current sources.
II. SYSTEM OVERVIEW
The system was designed with several considerations. First,
it is difficult to manually measure a statistically significant
sample of devices in an efficient manner. Each measurement
requires the user to make connections between different pieces
of lab equipment to first measure the device’s I-V
characteristics, and then to set up the low noise measurement
system, bias the device carefully, and record data. By
automating IV curve measurement and providing an easily
adjustable and programmable bias source, measurement time
is reduced.
By providing an electrically shielded container, any noise
sources in the surrounding environment are prevented from
contaminating the measured signal. Custom circuit and PCB
design also help to reduce the amount of noise contributed by
the measurement system.
Previous 1/f noise measurement systems typically use a
voltage source and a resistor to provide current bias to the
device. This circuit topology has a noise floor fundamentally
limited by the thermal noise of the resistor. The bias current
circuit developed in this project is able to source comparable
amounts of current while significantly reducing the noise floor
from that of a resistor.
The system was designed to have a PC LabVIEW based
user interface. The measurement board communicates with
this software using an NI USB development board and
onboard logic. The onboard logic is used to control bias
circuitry, amplifier gain, and connection switching. The PC
software coordinates IV measurements, bias generation,
settling times, and data acquisition. A system block diagram is
shown below.
PC
NI USB
Development
Board
Digital Control
Circuit
Biasing Circuit
DUT
Signal
Conditioning
(Amplification)
Measurement
(DSA, B1500)
Figure 1 – Overall system block diagram.
III. ELECTRICAL THEORY OF OPERATION
A. Digital Circuitry
The digital hardware component is a Xilinx CoolRunner II
XC2C64A CPLD. This part was chosen because it was
available in a VQ44 package, which minimizes board space
without the complexity of a BGA device, while providing a
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sufficient 33 I/O pins. Ignoring BGA devices, competing
products from are only available in 100 pin or greater TQFP
packages.
To isolate the ground used by the controller PC, inputs to
the CPLD are isolated using Fairchild Semiconductor
FOD8001-ND opto-couplers. These devices accept a digital
input and produce an isolated digital output. Since the NI USB
6501 uses a 5V VCC and the CPLD requires a 3.3V VCCIO,
these devices also perform the necessary level shifting.
The CPLD’s digital outputs are connected to the attached
peripherals (relay drivers and D/A Converter) using its general
purpose I/Os at 3.3V LVCMOS levels.
In addition to the 3.3V VCCIO supply, the CPLD requires a
1.8V supply for its logic core. (VCC) To provide these rails,
Linear Technology regulators (specifically, LT1761 for the
1.8V and LT1965 for the 3.3V) were chosen. These regulators
were desirable because they would accept the +18V supply
provided by the batteries. Fixed output devices were chosen to
simplify circuit design.
The final element required to utilize the CPLD in a real
system is a JTAG test/programming interface. To facilitate
easy programming using a Xilinx Parallel Cable IV or Xilinx
USB Platform Cable II (The most common programming
devices supplied by Xilinx), a 14 pin Molex 87833-1420
connector is used, so the 14 pin ribbon cable included with
those two programming cables can be used without
modification.
B. Computer Interface
The controller PC running the LabVIEW software will
connect to the board using an NI USB 6501 device. This
device provides 24 digital I/O lines at 5V TTL logic levels.
While only 5 I/Os are necessary for the current design, this is
the least expensive USB interface provided by National
Instruments. This device is easily controlled with the
LabVIEW software.
C. CPLD Design
The CPLD was designed to use a four wire full-duplex SPI
interface to send and receive configuration information from
the PC. To allow for easy control, the data input is broken into
an instruction (4 bits) and data. The CPLD design allows for
variable bit length transmission, allowing flexibility in
connected components and internal registers. Figure XX show
the operation of a 20 bit write over the bus. The CPLD
provides a DOUT signal, which is only used to test
communication with the board. While not in use, the clock,
data, and strobe bits are held at VCC.
Figure 2 – SPI communication timing diagram
The instruction input is processed by a state machine, which
then enables the appropriate register or state machine inside
the CPLD to process the data. The internal structure of the
CPLD is shown in Figure 3
Figure 3 – CPLD logic architecture
D. Control Software
To control the measurement circuitry and test equipment a
LabVIEW-based control application was developed. The
software controls an HP3562A dynamic signal analyzer
(DSA) and the USB 6051 board used to communicate with the
board. Drivers for DSA control needed to be written using the
LabVIEW instrument I/O assistant, while a publicly available
driver was used to obtain measurements from the DSA.
Control of the USB-6501 was achieved using the DAQ
Assistant. To enable easy modification of the measurement
flow and easy expansion for added tests or measurement
equipment, a number of sub VIs (Virtual Instruments) were
written to make the top level VI easy to understand and
modify. Individual VIs were created to control each peripheral
connected to the CPLD and the CPLD interface itself. The
data bits produced by each sub VI were abstracted to integer,
string, or Boolean parameters that are passed to the VI during
execution.
The top level control software implements the algorithm
shown in Figure 4 to take a noise measurement:
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before being applied to its respective node. To establish a
drain current for the DUT the control voltage is converted into
a precision low noise current using an active low noise current
source.
Once the DUT is biased correctly and the
measurement process begins low level noise signals are passed
through amplification stages up to levels that can be measured
by the lab’s dynamic signal analyzer.
F. Voltage Bias Circuit
The circuit shown below in Figure 5 is used twice in the
project to bias both the gate of the device under test as well as
the negative terminal of the low noise amplifier. The gate bias
voltage is needed to set the DUT into the correct region of
operation for measurement while the LNA voltage is used to
cancel out DC offset at its output in order to correctly interface
with the measurement equipment.
RCharge
Control
Voltage
Figure 4 – Measurement software flow
E. Analog Measurement and Bias Circuitry
To test the 1/f noise of a transistor (henceforth referred to as
a device under test, or DUT), it must be biased in the desired
operating region. 1/f noise may be measured in any of the
states of operation. The 1/f noise contributed by a device may
also differ depending on the state of operation it is in. It is
desirable for the characterization platform to be able to bias a
DUT in all regions of operation: cutoff, triode, and saturation.
To bias a device, a known current must be passed through
the drain. Controlling this current can change the operating
region, assuming a fixed voltage bias on the gate. This gate
voltage can also be varied, to produce a wide range of bias
points for the DUT. Thus, a voltage biasing circuit and a
current biasing circuit were developed.
VDD
DAC
V_cntrl1
I_DUT
LPF
I_noise
I_noise
V_noise
12b Din
I_Bias
LPF
DAC
V_cntrl2
Low Noise
Bias Current
Generator
12b Din
DAC
V_cntrl3
12b Din
-VSS
Figure 5 – Analog block diagram
Figure 5 depicts a block diagram of the analog bias and
measurement circuitry. Three control voltages are established
via commands from the digital circuitry and LabVIEW
software through the three DACs in order to correctly bias the
DUT. At the DUT gate and low noise amplifier nodes, the
control voltage is first filtered to ensure correct noise levels
RFilter
Charging
Relay
C
DUT
Gate or
LNA (-)
Terminal
LPF
Figure 6 – Low Noise Voltage Bias Circuit
Using the custom LabVIEW software the user selects a
desired bias voltage for the device under test between ±10V.
Their choice is then sent from the computer to the digital
circuitry located in the shielded container where it is outputted
from a D/A converter’s output as the control voltage to the
bias circuit. This control voltage is then filtered by the lowpass RC filter to bring its noise level to within specification
before being output by the bias network to the correct node
elsewhere in the circuit. Throughout the entire measurement
process the control voltage is held at the user defined level.
In order to filter the control voltage noise to acceptable
levels RFilter and C need to have a cutoff frequency of 1mHz or
lower. For this project RFilter = 1MΩ and C = 1mF creating a
cutoff frequency of 159µHz. Because the bias networks RC
time constant is relatively large (~6000s) it requires a large
amount of time in order to charge to the correct voltage
needed at the output. To speed up the circuit’s settling time the
charging relay is flipped by a signal from the CPLD before the
control voltage is outputted from the D/A converter. Flipping
the relay connects RCharge (10Ω) in parallel with RFilter. Since
RCharge is very small compared to RFilter the bias circuit’s time
constant is greatly reduced (< 0.1s) and the circuit can charge
to the required output bias voltage in much less time than it
would normally be capable of. Once the output voltage has
settled, a second signal from the CPLD flips the switching
relay back to no connection and the control voltage is then
filtered and the output held at a constant value.
G. Low Noise Current Source
Since the 1/f noise characteristic of a device is measured at
its drain (or collector, in the case of a BJT), it is imperative
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that any measurement apparatus that connects to this node
must not contribute a significant amount of current noise. A
bias current source must connect to this node, so this current
source must be low noise. Furthermore, it must be capable of
providing extremely low currents (single nano-amp levels) for
biasing the DUT in cutoff. For this reason, it must have very
high output impedance.
The circuit block must also have a digitally programmable
output current. A 12-bit D/A converter was selected to provide
programmable voltage biases for other parts of the circuit.
This D/A converter was also chosen to be used to program the
bias current, and as such is a multiple output D/A. The current
source circuit topology was developed to provide extremely
high output impedance, low noise, a maximum output of
100µA, and a 100dB dynamic range, resulting in a minimum
output current of 1nA.
A dynamic range of 100dB equates to approximately 17 bits
of resolution. 17-bit D/A converters are difficult to find,
expensive, and often will often sacrifice performance
characteristics such as INL (integral nonlinearity) and DNL
(differential nonlinearity) to achieve such a high resolution.
While linearity is not crucial to the operation of the current
source, a cheaper solution was found this still allowed
preservation of linearity. The current source was designed
with two operation modes, one for high current and one for
low current. The low current mode allowed a minimum output
of 1nA with 1nA resolution, and the high current mode
allowed 100µA maximum output current with 24nA
resolution.
This
is
summarized
in
Table
1.
The circuit uses a control voltage and an operational
amplifier to establish a fixed bias across a resistor, Rs. The
control voltage comes from the D/A converter, which allows
the output current to be set digitally. This control voltage is
referenced to be a maximum of 1V from ground. The two
output modes (high current and low current) are achieved by
changing Rs. The simplified schematic of Figure 6 does not
show the switching scheme.
Since Rs is known, and the maximum control voltage is 1V,
then the maximum current through Rs can be determined. The
control voltage has 12-bit resolution, and hence the current
through Rs will also have this resolution. Current in Rs is also
the output current. The JFET serves as an active output device,
enhancing output impedance and providing isolation of the
output node from the input. This isolation is key to the low
output noise of the circuit.
The circuit is only designed to provide a DC output current,
so low pass filters are used on the gate and the drain to reduce
the amount of noise injected at those nodes. The noise signals
present at the output of the circuit will the sum of the channel
noise, any noise sources injecting into the channel node, and
any noise injected into the gate times the transconductance of
the JFET.
𝑖𝑛𝑜 = 𝑔𝑚 𝑣𝑛,𝑔 + 𝑣𝑐ℎ
The noise in the channel, vch, is the sum of the op-amp input
noise voltage, the noise voltage from Rs, and the channel noise
intrinsic to the JFET, which is a combination of 1/f noise and
white noise. JFETs are naturally low noise devices. The design
uses a JFET with intrinsic noise lower than the desired output
noise level. It can be assumed that noise created by the resistor
Rs or the op-amp will be far greater. Equation 2 provides a
simplified model of the current noise present in an MOS
device:
2
𝐾𝑔𝑚
3
𝑊𝐿𝐶𝑜𝑥 𝑓
2
𝑖𝑐ℎ
= 4𝑘𝑇 𝑔𝑚 +
VDD
Sensitive
Measurement
DUT
Node
Control
Voltage
LPF
Iout
C
LPF
Noise
Injection
C
Rs
FIGURE 7 – Low-noise current source shown with sensitive measurement node
and points where noise is injected.
(1)
(2)
The current noise in the channel has two terms; the first
describes channel thermal noise, and the second describes
channel 1/f noise.
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the circuit, RS can be 10kΩ or 243kΩ). For this reason, C is
chosen to be large so that most of the noise current is shunted
to ground through that low impedance branch, rather than
flowing through the JFET channel and adding noise.
Noise voltage source Vn2 is not filtered. It is a voltage
source that sees the parallel combination of R S, 1/sC, and 1/gm
to ground. The amount of current Vn2 sources through 1/gm is
equal to gmVn2. It is presumed that, since Vn2 of the amplifier is
8nV/sqrt(Hz) and gm is on the order of mΩ-1, the contributed
noise current will be small enough. If operational testing
proves it is too much, the contributed noise can be attenuated
by inserting a large resistor in the feedback loop to create a
voltage divider.
VDD
DUT
Iout
Vn1
LPF
Vg
Rf
Vn2
In1
In,ch
Cf
LPF C
Rs
Inr
Figure 8 – Current source circuit with equivalent noise sources inserted. Inr is
the equivalent thermal noise current of Rs, In1 and Vn2 are the equivalent input
noise sources of the op-amp for the positive terminal. Vn1 is the output noise
of the amplifier and any additional sources of noise present at the inverting
terminal (D/A converter output noise, for example).
The circuit here is shown with equivalent noise sources.
These sources are undesirable, and analysis of the circuit
shows that they are negligible at the output. Each source can
be treated independently by zeroing out the other sources. The
objective of this analysis is to determine the contribution of
each noise source to the current noise at the channel. Results
of the analysis show that all sources add negligible noise
compared to the intrinsic JFET channel noise, In,ch.
Since 1/f noise is typically a very low frequency
phenomenon, the noise contributed at low frequencies will be
considered. We define a minimum bandwidth for the system
of 0.1Hz. The circuit topology heavily relies on using
capacitors to attenuate the noise, even at low frequencies.
Thus, attenuations for LPF blocks can be evaluated at 0.1Hz.
This will provide a worst-case estimate of the total noise
injected into the channel node. The amplifier used in the
design, an ADA4004, has input noise sources of 8 nV/sqrt(Hz)
at 0.1 Hz and 30 pA/sqrt(Hz) at 0.1 Hz. These values are
extrapolated from noise spectral density plots on the datasheet.
Noise voltage source Vn1 is the first source to consider. It
is passed through the LPF consisting of Rf and Cf. The
resulting signal, Vg, is then amplified by the transfer function
of the JFET. The output noise current is thus gmVg. Typical
transconductances for a JFET in the active region are 1 to 3
mΩ-1. For the low frequencies considered here, Vn1 is any
noise on the inverting terminal multiplied by the DC openloop gain of the amplifier. By choosing Rf and Cf large, Vn1
can be attenuated enough so that the contributed noise at the
channel is small.
Noise current sources Inr and In1 can be combined into
one noise current source. These currents will see the parallel
combination of impedances present at the JFET source node.
These impedances are RS, 1/sC, and the impedance looking
into the source of the JFET, 1/gm. This creates a current
divider. 1/gm can be a small value compared to the large RS (in
H. Low Noise Amplifier
A low noise transconductance amplifier is used to amplify
the noise current signal at the drain of the DUT. A simplified
diagram of the analog measurement circuit is shown below.
Two amplification stages are used to achieve the desired
maximum system gain of 160dB. This gain is adjustable in
increments of 20dB by switching feedback resistors in and
out. Ri is a small value of 100Ω and does not affect the
operation of the amplifier as a transconductor.
Current Bias
Circuit
Rf1
Rf2
Ri
Ri
DUT
Vout
Vbias
Circuit
Figure 9 – The LNA circuit attached to the DUT drain node.
I. PCB Layout
The main concern during PCB layout is noise. Signals
coming from the wafer must be protected up until they enter
the first low-noise amplifier, at which point the thermal noise
of the surrounding circuitry has no significant effect on the
signal of interest. The signal from the wafer attach to the PCB
board using SMA connectors. The traces are then coaxed
(three traces being ground-signal-ground) to the relays and
then fed from the relays into the low noise amplifier. The goal
during layout was to minimize the distance from the SMA
connectors to the low-noise amplifier. The figure below
shows the complete PCB layout. Green is the bottom copper
layer, Red is the top copper layer, and yellow is the silkscreen
layer. The left side of the board is comprised of analog
circuitry, while the right side of the board contains the digital
circuitry that controls the relays and interfaces with the outside
world.
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Figure 12: Sensitive signal path. Blue dots highlight the path from the relays
to the low-noise amplifier (R15).
Figure 10: Complete board layout with bottom metal layer (green), top metal
layer (red), and silkscreen (yellow) shown.
The next figure shows a close up view of the sensitive signal
path. The SMA connectors can be seen on the left side of the
board with their respective labels for Drain, Source, and Gate
of the DUT. The groupings of three traces are the co-axed
traces that touch relay nodes of SW8 and SW9.
Figure 13: Bottom copper layer view only. Bottom layer acts as ground plane
for all circuitry, with all grounds tied together at a single point.
Figure 11: Sensitive signal path. DUT S, G, and D are SMA connectors
connected to the DUT nodes.
The next figure shows the signal path from the relays to the
low noise amplifier. The path is very short to minimize the
risk of contamination and the trace width is wide to minimize
the resistance seen by the incoming sensitive signal.
The figure above shows the bottom copper layer of the
PCB, which is electrically the ground plane. One important
tactic employed to reduce noise in the circuit is to tie all of the
grounds together in one place. The left side of the board is the
ground for all analog circuitry and the right side of the board
is the ground for all digital circuitry. The two are connected in
one place, as seen above. The external batteries also have
their grounds tied to the same spot. All free space on the
bottom of the board is filled with metal to provide, as much as
possible, and uninterrupted and solid ground plane. All pins
that require grounding are immediately tied to ground through
a via. By reducing ground loops, the potential for noise
contamination in the circuit can be reduced.
IV. MECHANICAL THEORY OF OPERATION
A. Mechanical Design Process
The main goal of the mechanical components of the noise
characterization system is to provide continuous physical RFI
and EMI protection for the measurement apparatus while the
M150 was in use. It was also specified that the protective
barrier must fit on, and not interfere with the operation of, the
M150 during operation, as well as contain the electronic
components of the system and provide a window through
which the positioning microscope of the M150 could see.
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B. Material Selection
The critical first step in creating the shielded container was
to select the appropriate materials to construct the apparatus
out of. The shielded enclosure had to be constructed out of a
rigid material that could be affixed to the M150 easily that was
light enough so as not to break the M150. This material also
had to shield the container from EMI and RFI, as well as be
non-ferrous so the container did not introduce any noise of its
own. The selected material, rolled Aluminum, met all of these
criteria.
To include a viewport for the M150’s microscope a
substance that was transparent and conductive was required.
The chosen material was ClearShield™ plastic film because
the material allows 80% visible light transmission, over 80db
of attenuation below 100kHz, and is conductive.
C. Three Dimensional CAD Design
The design of the shielded enclosure was created using
Pro/ENGINEER® (Parametric Technology Corporation) CAD
software to define the shapes and physical part geometries. By
using the CAD software, it was possible to create multiple
designs for each part and asses the positive and negative
attributes of differing geometries. This greatly reduced the
time needed to redesign the assembly when space or design
requirements changed.
The actual geometries created in Pro/ENGINEER were
constrained two main specifications: the need to fit on the
M150 without damaging it, the need to allow the M150 its full
range of motion, and the need to house all of the electronic
components used in measurement. The first specification
required the creation of detailed dimensional references for all
of the components on the M150 and recording the movements
that the M150 might have to make for the measurement of a
150mm wafer. After these measurements and movements
were taken, the parts required for the electronic system
components were measured to determine the volume required
inside the shielded area. All of this information was then
combined to create a three dimensional system model for
shielded container. The model creation was made significantly
easier through Pro/ENGINEER’s ability to combine multiple
part files to be into one assembly drawing, allowing the
designer to quickly determine if the parts that have been
combined will fit.
D. Manufacture
The metallic structures of the shielded enclosure were
created from plate aluminum using a combination of
machining, hand working, and the use of epoxy resin. The
manual machining was done in the RIT machine shop using a
three axis milling machine, a band saw, and a belt sander. The
band saw was used to create rough cuts, while the milling
machine was used for finer work to create straight lines, 90°
angles, and any holes needed in the design. The belt sander
was used to clean any excess material from the cut sections.
Hand working was used in the final stages of manufacture, just
before the application of the metallic epoxy, to insure that the
surfaces fitted together correctly. The epoxy was used to bond
the plates together and to ensure a continuous conductive
surface between pieces.
V. FUTURE WORK AND IMPROVEMENTS
One piece of future work on the Noise Characterization
Platform would be to correct a problem with the low noise
amplifier. Currently, using the circuit described in Section H
causes the DC offset of the second stage to be larger than the
rails of the operational amplifier for certain Vbias voltages.
The applied Vbias appears on the output of the first amplifier
because it is being used as a transimpedance amplifier and the
noise current which is gained up and converted to a voltage
rides on top of this DC offset. Since the second stage of
amplification is a voltage amplifier both the noise signal and
Vbias offset are amplified by the circuit. Amplifying Vbias
(which can be between ±10V) causes the output of the circuit
to hit the upper or lower rail.
This railing of the second op-amp affects the quality of the
measurement and makes interfacing with the dynamic signal
analyzer more difficult. A simple fix to the issue is shown
below in Figure 14.
Current Bias
Circuit
Rf1
Rf2
Ri
Ri
-
DUT
+
+
Ri
Vout
Rf2
Vbias
Circuit
Figure 14 – Low noise amplifier offset correction
The circuit in Figure 14 is identical to the one in Figure 9
with the addition of two more resistors. These resistors are the
same values as the two feedback resistors on the negative
terminal of the second amplifier and form a voltage divider
using the applied Vbias voltage and ground. The voltage
between the two resistors is connected to the second stage
positive terminal. Since the two new resistors are the same
value as the feedback resistors and Vbias is applied to both RI
resistors identical voltage dividers are formed with the same
potential seen at the both input terminals of the second stage.
This forces Vout to be 0V with only the measured signal being
transmitted to the dynamic signal analyzer.
A second piece of work that must be accomplished in order
to make the project fully functional is to modify the low noise
current sources so they can fully provide the range of needed
bias currents. Presently, the output swing of the current
amplifier being used is not close enough to either supply to
allow for the full range of needed bias currents. An amplifier
with rail-to-rail output swing is required to fully implement
the needed features in the circuit. Also a JFET with a smaller
pinch off voltage range should be used for the active device in
the current source. The JFET being used now has a pinch off
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voltage between 0.5V and 3V which depending on what its
exact value is can affect how the overall circuit performs and
how well the operational amplifier can set the desired bias
current.
A potential improvement to the overall system would be to
streamline the layout of the PCB. Currently component
density is quite high due to the presence of large capacitors,
power resistors, relays, etc. and steps could be taken to reduce
the amount of layout space required and component density.
If a suitable dual package low noise amplifier be found the
low noise amplifier circuitry could be condensed. This would
also benefit the noise performance of the system as having
both low noise amplifiers in one package reduces the
probability of noise coupling into the signal as the amps are
located as close together as they could possibly be.
Removing some of the relays in the circuit would also serve
to reduce layout area and complexity. While the relays are
required in the signal path for physical isolation from
unneeded circuitry to keep noise performance at acceptable
levels not all of the switches need to be relays. In these cases
MOSFET switches should be able to be implemented without
any loss of performance though testing and/or simulations
should be done to confirm this assumption. One such example
of where MOSFET switches could be used would be in the
DUT gate and low noise amplifier bias circuitry. The relays in
place now are not in the signal path and most likely can be
replaced smaller MOSFET switches.
If the MOSFET
switches can be driven by 3.3V then they can be toggled
directly from the CPLD which may mean fewer relay drivers
are needed potentially getting rid of more components from
the board.
VI. REFERENCES
[1] Johns, David A. and Ken Martin. Analog Integrated
Circuit Design. John Wiley and Sons. 1997.
[2] Stanford Research Systems. Model SR570 – Low Noise
Current Preamplifer. SRS, Inc. 1997.
[3] Xilinx Inc. A Quick JTAG ISP Checklist. App Note
XAPP104. 2005.
[4] Xilinx Inc. Bulletproof CPLD Design Practices. App
Note XAPP784. 2005.