Download hot wire CVD TFTs with high deposition rate silicon nitride

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Solid-State Electronics 52 (2008) 427–431
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All hot wire CVD TFTs with high deposition
rate silicon nitride (3 nm/s)
R.E.I. Schropp a,*, S. Nishizaki b, Z.S. Houweling a, V. Verlaan a,
C.H.M. van der Werf a, H. Matsumura b
a
Utrecht University, Faculty of Science, SID – Physics of Devices, P.O. Box 80000, 3508 TA Utrecht, The Netherlands
b
Japan Advanced Institute of Science and Technology (JAIST), 1-1 Asahidai, Nomi, Ishikawa 923-1292, Japan
The review of this paper was arranged by Guglielmo Fortunato
Abstract
Using the hot wire (HW) chemical vapor deposition (CVD) method for the deposition of silicon nitride (SiNx) and amorphous silicon
(a-Si:H) thin films we have achieved high deposition rates for device quality materials up to 7.3 nm/s and 3.5 nm/s, respectively. For thin
films of SiN1.3, deposited at 3 nm/s, the mass-density of the material reached a very high value of 3.0 g/cm3. The silane utilization rate for
this fast process is 77%. The high mass-density was consistent with the low 16BHF etch rate of 7 nm/min. We tested this SiN1.3 in ‘‘all hot
wire” thin film transistors (TFTs), along with a-Si:H material in the protocrystalline regime at 1 nm/s. Analysis shows that these ‘‘all hot
wire” TFTs have a Vth = 1.7–2.4 V, an on/off ratio of 106, and a mobility of 0.4 cm2/V s after a forming gas anneal. We therefore conclude that the HWCVD provides SiNx materials with dielectric properties at least as good as PECVD does, though at a much higher
deposition rate and better gas utilization rates.
Ó 2007 Elsevier Ltd. All rights reserved.
Keywords: Thin film transistors; Silicon nitride; High deposition rate; Hot wire chemical vapor deposition
1. Introduction
For economic production of thin film transistors (TFTs)
for active matrix applications, it is desirable to have high
deposition rate and good gas utilization. Although plasma
enhanced chemical vapor deposition (PECVD) is presently
still the workhorse of the semiconductor industry, it has a
number of limitations, which are all linked to the use of
plasma [1]. For instance the formation of dust, caused by
the positive potential in the bulk of the plasma, which traps
negatively charged particles, is a serious issue. To avoid
formation of dust due to charged particles in PECVD,
depletion of silane has to be avoided. This lowers the gas
utilization, which is defined as the percentage of gas that
is actually deposited within the reactor, to values as low
*
Corresponding author. Tel.: +31 30 2533170; fax: +31 30 2543165.
E-mail address: [email protected] (R.E.I. Schropp).
0038-1101/$ - see front matter Ó 2007 Elsevier Ltd. All rights reserved.
doi:10.1016/j.sse.2007.10.034
as 1%. Other drawbacks of PECVD depositions are the
damage that may be caused by ion bombardment (especially in direct PECVD reactors [2]) and the fact that the
substrate is a part of the deposition setup itself. The latter
drawback is especially important when using a wider selection of substrate types (insulating as well as conducting) or
when a full inline production line is aimed for.
Lately, we have focused on ultra fast deposition (>7 nm/s)
of dense amorphous hydrogenated silicon nitride (SiNx)
using the hot wire chemical vapor deposition (HWCVD)
method [3]. In HWCVD, the source gasses are catalytically
decomposed at heated metal filaments and the method thus
is totally plasma free. Due to the efficient catalytic decomposition of feedstock gases at the heated metal filaments,
good gas utilization (>75%) [4–6], and thus high deposition
rates [3,7,8] are achieved using HWCVD. Because the
potential of HWCVD would be much larger if both channel material and gate dielectric are deposited with the same
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R.E.I. Schropp et al. / Solid-State Electronics 52 (2008) 427–431
technique, ‘‘all hot wire” TFTs have been investigated in
the past [9,10] and showed good performance and stability
[11,12].
At Utrecht University, the thin film SiNx deposited at
3 nm/s, reached a very high density of 3.0 g/cm3. This high
density has thus far never been reached for PECVD SiNx
[13]. Since it is expected that these very compact SiNx layers have good dielectric properties we tested this SiN1.2 in
‘all HW’ thin film transistors (TFTs) along with a-Si:H
material in the protocrystalline regime at 1 nm/s.
The purpose of this paper is to show that this fast deposited, high density SiNx is suitable for use in bottom gate
staggered TFTs, as commonly used in active matrices.
100% at process pressures between 1 Pa and 100 Pa. For
SiNx depositions, ammonia is added as a source gas to
the silane. Using this mixture, the decomposition efficiencies at the wire change considerably. Especially the ammonia decomposition efficiency is reduced significantly by
adding SiH4 to an originally pure NH3 ambient [16]. Still,
very good decomposition efficiencies are reported in a
SiH4/NH3 mixture at relatively low total flow rate, namely
98% and 52% for SiH4 and NH3, respectively [5]. In the
present work, we maintained a high SiH4 utilization efficiency of 77%, despite the much higher flow rates that
are necessary to obtain the high SiNx deposition rate [3].
The utilization efficiency for the less expensive ammonia
is under these conditions 7%.
2. Hot wire chemical vapor deposition
3. Characterization of HWCVD SiNx
The depositions described in this paper were performed
in a hot wire reactor that is part of an ultra high vacuum
multi-chamber system (PASTA) [14]. A schematic drawing
of the reactor is shown in Fig. 1. As source gasses for SiNx
pure silane (SiH4) and ammonia (NH3) were used. For aSi:H only pure SiH4 is used. Thus, for both types of materials no hydrogen dilution was used. The source gasses are
catalytically decomposed at tantalum filaments held at
2100 °C (SiNx) or 1850oC (a-Si:H). The substrate was
heated by radiation from the filaments only and reached
a temperature of about 450 °C (SiNx) or 250 oC (a-Si:H).
No additional heating was applied. In this laboratory system, a shutter is situated between the sample and the wires
to control the duration of the deposition.
For HWCVD, in order to decompose the source gasses
it is necessary for the molecules to collide with the heated
wires. The decomposition probability of a single SiH4 molecule by one collision with the catalyzer is roughly 40%
[4,15]. Because multiple collisions take place, the effective
probability of molecule-surface collision approaches
Fig. 1. Schematic drawing of the experimental HWCVD reactor.
At Utrecht University, thin films of SiNx deposited at
3 nm/s are investigated. Fig. 2 shows the mass density
and atomic H content as a function of the N/Si ratio in
the films, for samples made under many different gas flow
ratio and pressure conditions. The absolute H, N and Si
contents are determined by elastic recoil detection (ERD)
[17] from which the total mass density can be calculated.
It appeared that the samples with an atomic N/Si ratio
(also x in SiNx) around 1.3 have a maximum in mass density (3.0 g/cm3). These high densities have thus far never
been reached for PECVD SiNx, even when applied at substrate temperatures higher than 500 oC [13,18]. This is the
case because PECVD leads to materials that are too porous
and too H-rich at high N concentration [19]. In the hot
wire CVD process the substrate temperature was limited
to 450 oC. The hydrogen concentration in the films shows
an inverse trend, showing the smallest H concentration
(9 at.%) for films with the highest density. In a previous
publication [20] we have shown that this hydrogen is
mainly bonded to nitrogen atoms and only a small amount
is present in the Si–H configuration. This low amount of
Fig. 2. Structural properties of HWCVD SiNx films. The mass density
reaches a maximum of 3.08 g/cm3 at x = 1.3. Also at this composition the
H content is minimal (9 at.%).
R.E.I. Schropp et al. / Solid-State Electronics 52 (2008) 427–431
Si–H bonds is an advantage for the use as sidewall and
liner material in ULSI p-MOS transistors. This is the case
because H, coming from the SiNx at the sidewalls, can create defects at the gate/gate insulator interface [21].
Etch rate experiments in a 16BHF solution (5 parts 40%
NH4F with 1 part 50% HF) confirmed the high mass density. Fig. 3 shows the etch rates for various films with different N/Si ratios. The best etch rate observed was 7 nm/
min, which was again achieved at an N/Si ratio of 1.20.
This etch rate is much lower than that obtained for
PECVD layers, even though the latter layers are made at
a much lower deposition rate [22–25].
In Fig. 4, the results of stress measurements on the films
are shown. Stress measurements were performed using a
Schott glass substrate and a DEKTAK step profiler. The
stack curves due to stress in the film-substrate stack. From
the curvature the total mechanical stress can be obtained
[26]. The most N-rich samples have the highest amount
of tensile stress while for more Si-rich films the total stress
decreases. For layers with N/Si = 1.20 the tensile stress
becomes as low as 16 MPa. This low stress will be helpful
429
in for instance, plastic electronics, when TFTs are deposited on thin polymer foil. This stress is much lower than
reported for single-layer near-stoichiometric PECVD SiNx
coatings [22,27,28].
SiNx films with various x values in the range 1.0 <
x < 1.5 have been incorporated in metal–insulator–semiconductor structures with n-type c-Si h1 0 0i wafers to
determine their electrical properties from C–V to I–V measurements. Aluminum (Al) is evaporated on the backside
of the c-Si wafer as Ohmic contact and Al dots
(0.16 cm2), were evaporated as front contact. Capacitance–voltage (C–V) measurements were performed in the
dark and at room temperature at a high signal frequency
of 1 MHz. We analyzed the behavior of the static dielectric
constant, fixed nitride charges, and trapped interface
charges as a function of N/Si ratio. We make no distinction
between fixed and mobile nitride charge and surface state
charge and simply monitor the collective fixed nitride
charge. Furthermore we assume, for the sake of simplicity,
that all charge resides in the bulk. I–V measurements show
that the HW SiNx films with N/Si P1.45 have high dielectric breakdown fields that exceed 5.9 MV/cm. For these
films we deduce a low positive fixed nitride charge density
of 6.2–7.8 1016 cm3 from the flat band voltage and from
the small hysteresis in the backward sweep we deduce a low
fast trapped interface charge density of 1.3–1.7 1010 cm2. The dielectric constant e for different compositions is seen not to change appreciably over the whole
range and amounts to 6.3.
The root-mean-square (rms) roughness measured on
300 nm thick SiN1.3 layers is only about 1 nm. Such low
values are necessary to attain high field-effect mobility in
TFTs. For more Si-rich layers the roughness increases
and for more N-rich layers (with an N/Si ratio of 1.55) even
rms values of 0.5 nm are reached.
4. TFTs with HWCVD SiNx and HWCVD a-Si:H
Fig. 3. The high mass density of the films is consistent with the low etch
rate of 7 nm/min in a 16 BHF etch solution.
Fig. 4. The total mechanical stress (tensile) as a function of atomic N/Si
ratio. For N/Si = 1.2 the stress becomes as low as 16 MPa.
To test these HW deposited films for application in a
field effect transistor (FET), trilayer structures, consisting
of HWCVD SiNx (made at 3 nm/s), HWCVD a-Si:H
(made at 1 nm/s) [29] and lc-Si:H highly doped n-layers,
were deposited at Utrecht University on Corning 1737
glass with pre-patterned Cr gates as provided by Japan
Advanced Institute of Science and Technology (JAIST).
Fig. 5a shows a schematic cross section of the tri-layer
structure and Fig. 5b shows a diagram of the final TFT
structure.
It was necessary to introduce an air break between the
SiNx deposition and the a-Si:H deposition, which most
likely puts an upper limit on the achievable mobility. Nevertheless, these TFTs are still suitable for their purpose,
namely to determine whether the 3 nm/s SiNx is suitable
for TFTs. After deposition of the HW films, the photolithographic structuring was performed at JAIST. For the
determination of the required back etch time for definition
of the channel region between the top source and drain
430
R.E.I. Schropp et al. / Solid-State Electronics 52 (2008) 427–431
n+ uc-Si:H 27 nm
a-Si:H 200 nm
V d=8 V W/L=2
10 -5
SiNx:H 400 nm
First
-6
10
100 nm Cr
Second
Corning 1737 0.7 mm
Third
-7
Drain current (A)
10
-8
10
-9
10
-10
10
-11
10
-12
10
-13
10
Fig. 5. (a) Cross section of the tri-layer TFT structure on Cr pre-patterned
gates and (b) completed TFT structure.
-5
0
5
10
15
Gate voltage (V)
b
-7
[×10 ]
contacts, the etch rate of the HWCVD a-Si:H was checked.
It appeared that the HWCVD a-Si:H (made under protocrystalline conditions [29]) had an etch rate in diluted
HF/HNO3 that is 50% slower than conventional a-Si:H.
Vg: 0-10V (1 Vstep)
2
W/L=2
Drain current (A)
V g=10 V
5. Characterization of the HWCVD TFTs
9V
1
8 V
7V
6V
5V
0
0
2
4
6
8
10
Drain voltage (V)
c
[×10-3 ] 1.0
V d =8 V W/L=2
First
Second
0.8
Square root of Id
No pinholes have been found within the matrix made
(86 TFTs) and the transfer and output characteristics are
shown in Fig. 6a and b. The square root of the drain current as a function of gate voltage is shown in Fig. 6c. The
transfer characteristics were measured three times. The
subsequent curves correspond to the first, second, and third
measurement. The threshold voltage is slightly increased in
the direction of more positive gate voltage after each measurement. It is known that the Vth shift caused by charge
trapping is dependent on the composition of the SiNx
dielectric in the case of plasma-deposited films [30] and a
study of the defect density and bond structure specifically
for hot wire deposited SiNx was done at JAIST [31]. It is
shown that Vth shift can be minimized by carefully optimizing the composition of the SiNx. The present TFT data are
consistent with a composition of the SiNx film that is neither too Si rich nor too N rich, since the initial Vth shift
is very small. The S-value is rather large, but this is due
to the large thickness (400 nm) of the SiNx film. In these
first experiments the SiNx gate insulation was deliberately
made thick to avoid electrical breakdown of SiNx. In the
output characteristics it is seen that the series resistance
of the source and drain contacts is very low. The mobility
and Vth are shown in Fig. 5. The mobility is estimated from
the gradient of square root of Id as a function of Vg in the
saturation region (Vd = 8 V).
Although the characteristics of the present TFTs are
already suitable for applications, the mobility is only moderately high. Since the as-deposited mobility was only moderately high, we annealed the TFTs in forming gas (H2/N2)
µ : 0.23cm2/Vs
V th : 1.7V-2.4V
Third
0.6
0.4
0.2
0
-5
0
5
10
15
Gate voltage (V)
Fig. 6. (a) Transfer characteristics, (b) output characteristics, and (c)
square root of the drain current as a function of the gate voltage of the
HWCVD SiNx/a-Si:H TFT, before annealing.
R.E.I. Schropp et al. / Solid-State Electronics 52 (2008) 427–431
Table 1
Mobility determined by three different methods, both before and after
forming gas anneal
Mobility
Method 1
Method 2
Method 3
Anneal
Before
After
Before
After
Before
After
W/L = 2
W/L = 50
0.29
0.17
0.34
0.29
0.32
0.18
0.38
0.32
0.31
0.18
0.34
0.31
at 200 oC for 2 h. This time, the mobility was measured in
three different ways. The first method uses the Id–Vd data
in the linear regime. The equation for the mobility is given
by
ID ¼
W
l C ox ðV g V th ÞV D :
L n
ð1Þ
The second method uses the transconductance gm, at constant Vg,
oI D gm ¼
:
ð2Þ
oV D V G ¼ const
The mobility is then given as
L
1 1
l ¼ gm :
W C ox V d
ð3Þ
The third method is based on the output characteristics
around Vd = 0. Again, in the linear regime (Vd Vg–Vth),
the drain current is proportional to Vd and linearity can be
confirmed if the source-drain resistances are very low. Since
the contacts are very low Ohmic, this method can also be
used.
oI D W
gD ffi ln C ox ðV G V T Þ:
ð4Þ
L
oV D V g ¼const
Table 1 shows the calculated mobilities according to all
three methods, before and after forming gas anneal. All
three methods show consistent results and it is seen that
the highest measured mobility is 0.38 cm2/V s.
6. Conclusions
We have demonstrated that hot wire SiNx layers, deposited at a high rate of 3 nm/s (180 nm/min) can be applied in
TFTs. Combined with hot wire deposited a-Si:H at 1 nm/s,
this should lead to a total deposition time of less than 4 min
for the SiNx/a-Si:H stack. The silane gas utilization is also
of interest, showing a high value of 77%. No pinholes have
been found within the matrix made (86 TFTs). The mobility of these a-Si:H TFTs is 0.4 cm2/V s after a forming gas
anneal. The TFTs have a Vth of 1.7–2.4 V and an on/off
ratio of 106.
431
Acknowledgements
We thank Mr. Yohei Endo for his help with the preparation of the samples. Prof. Ruud Schropp thanks the Japan Advanced Institute of Science and Technology
(JAIST) and Prof. Hideki Matsumura for having had the
opportunity to visit the institute and collaborate on the
TFTs mentioned in this paper.
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