Download Substrate Noise Isolation Characterization in 90 nm CMOS

Substrate Noise Isolation Characterization
in 90 nm CMOS Technology
Sergei Kapora1, Wim Schoenmaker2, Peter Meuris2
1
NXP, Prof. Holstlaan 4, 5656 AA Eindhoven Netherlands,
2
[email protected]
MAGWEL, Martelarenplein 13, B-3000 Leuven Belgium,
[email protected], [email protected]
Presented by Mike Stuber, Magwel
DAC Track 2009
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Substrate Noise Problem
Noise coupling is one of the biggest challenges for deep
submicron SOC mixed-signal designs today:
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Goal / Use Model
3D simulation tool for substrate noise propagation analysis
is introduced
Simulation results are in good agreement with
measurements.
This enables us to
- evaluate different isolation approaches (layout and
process)
- formulate guidelines for substrate noise isolation
- reduce the number of expensive tape-outs of test chips
Resulting in more accurate, quicker chip design
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Problem Complexity
The coupling takes place
1) in the back-end metallization,
2) the front-end substrate
3) in the back-end/front-end connection.
Different mechanisms occur:
- conductive coupling in metal and substrate
- capacitive coupling:
- between the metal lines
- in the substrate (junctions)
- between metal and substrate
- magnetic coupling between intended and unintended loops
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Magwel’s solution:
Unique and patented technology
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Simultaneous 3D simulation of
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back-end (Maxwell)
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front-end (drift-diffusion)
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Frequency domain solver
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Depth-dependent doping concentration
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Gds2 import feature
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Connection of external circuit /
package model
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What Do We Solve ?
- Maxwell's equations everywhere
- Ohm's equation in metal
-Drift-diffusion equations in substrate
-When not needed, magnetic solution can be turned off
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Impact of Coupled Solutions
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Full coupling in the electromagnetic and
semiconductor device equations allows
analysis of parasitic coupling between the
two domains
For example
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DC bias of inductor over high-resistivity
substrate -> inversion layer
(semiconductor effect)
Carrier recombination -> inversion charge
(semiconductor effect)
Inductor RF power -> current in the
inversion layer (coupled EM and
semiconductor)
recombination and surface mobility effects
-> current (semiconductor effects)
Inversion layer current -> additional
magnetic field (EM effect) which feeds
back to the inductor (coupled EM and
semiconductor)
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editEM and solvEM Tools
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Two tools work together
to arrive at the solution
editEM is used to create
the structure and define
the simulation conditions
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Material coefficients
Layer thicknesses
GDSII import and drawing
tools
Doping profiles
solvEM contains the
engine that performs the
numerical solutions
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Test structure (1)
Aggressor
Victim
metal stack
SUB
DNW P+
DNW
SUB
substrate
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Test chip in 90nm CMOS technology
6 different DNW structures (square and
rectangular)
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Reference and de-embedding structures
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Measurements on wafer up to 40 GHz
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Test structure (2)
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Simplifications in gds2 file
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Removing tiles
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Merging small vias together
isolated
PW
DNW
psubstrate
Doping profile of isolated PW with DNW
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Simplified gds2 file merged
with technology file
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Doping profiles
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Metal stack
Full stack, including metal layers
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S-parameters - Measured vs. Modeled
S11 and S21 for DNW structure 20x12 um2
Good agreement between measurements and simulations
Special attention to be paid to mesh and solver settings
Contribution of metal stack coupling is not negligible (see next page)
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Separating Contributions
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Simulation without interconnect isolates substrate
effects from interconnect effects
Different contributions can be separated and
quantified
– Substrate vs.
interconnect
– E-field vs. B-field
– Multiple aggressors
or victims
With and without interconnect
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Results for Varied DNW Size
1
DNW 2
DNW
Varied width
3D model, RC
components only for
explanation of RC
behaviour
Only substrate (no metal
stack) is considered
“Ideal” biasing of DNW
(0Ω connection to 0V)
Noise isolation from substrate (1)
to Pwell tap (2), DNW width varied
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Different Isolation Schemes
Simple structures: Draw layout in editEM, simulate.
No protection
A
V
P+ ring
A
V
Full DNW
A
V
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Additional Insights
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Tool is used for development of noise isolation guidelines
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Effectiveness of different protection structures (guard rings etc.)
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DNW contacting strategy
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Influence of PW-DNW diode biasing impedance on isolation levels
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Includes all coupling paths (conductive, capacitive, inductive)
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Not limited to bulk CMOS processes (SOI, BiCMOS, 3D IC)
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Results can be represented as scalar or vector plots of all solved
parameters (e.g. voltage and current density) that point to process or
layout improvements
Top-down views of
voltage distribution
at silicon surface
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Tool Capabilities
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Complex 3D structures up to hundreds
of thousands of mesh nodes can be
simulated with full EM and device
equation coupling, up to millions of
nodes with reduced interactions
Doping profile import for process
sensitivity studies, process change
studies
GDSII import for efficient measured vs.
modeled comparisons
GDSII import for efficient layout
sensitivity studies
(substrate hidden)
RF Noise injection structure
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Conclusions
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Complex substrate noise problems can be
directly simulated in 3 dimensions, including
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Doping profile import (process change impact)
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GDSII layout import (re-use of existing structures)
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High aspect ratio grids (deep sub-micron structures
separated by hundreds of microns)
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Fully coupled electromagnetic and device
equations (LRC effects)
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Visualization of all solved parameters (potential,
current density, magnetic field) for insight
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