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TCAD Simulation for SOI Pixel Detectors October 31, 2006 Hirokazu Hayashi, Hirotaka Komatsubara (Oki Elec. Ind. Co.), Masashi Hazumi (KEK) for the SOIPIX group SOIPIX collaborators KEK Detector Technology Project : [SOIPIX Group] Y. Arai*, Y. Ikegami, H. Ushiroda, Y. Unno, O. Tajima, T. Tsuboyama, S. Terada, M. Hazumi, H. IkedaA, K. HaraB, H. IshinoC, T. KawasakiD, H. MiyakeE, G. VarnerF, E. MartinF, H. TajimaG, M. OhnoH, K. FukudaH, H. HayashiH, H. KomatsubaraH, J. IdaH KEK、JAXAA, U. TsukubaB, TITC, Niigata U.D, Osaka U.E, U. HawaiiF, SLACG, OKI Elec. Ind. Co.H Financial Support by KEK (*)—contact person 2006/10/31 Detector Technology Project 2 M. Hazumi (KEK) Outline • TCAD Overview • Breakdown voltage • Effect of bias voltage on readout electronics • P-substrate option • Summary 2006/10/31 M. Hazumi (KEK) 3 TCAD Overview 2006/10/31 M. Hazumi (KEK) 4 What’s TCAD ? • TCAD =Technology Computer Aided Design – Process simulation – Device simulation • Finer design rule more complicated processes, longer development time Real Virtual Specifications LSI Manufacturing Function design TCAD Logic design • TCAD can reduce development time drastically and is necessary for semiconductor manufacturing today • Why not for detector R&D ! 2006/10/31 Specifications Circuit design Process data Device data Process simulation Layout design ~3mon. Mask fabrication Device production M. Hazumi (KEK) Characterization Prototyping Device simulation 5 TCAD tools used in this talk • Silvaco TCAD • AHTENA (Process simulation): 2D simulation • ATLAS (Device simulation): 2D or 3D simulation • ENEXSS (Environment for NExt Simulation System) • Developed by Selete (Semiconductor Leading Edge Technologies, http://www.selete.co.jp/) • Full 3D process/device simulation ! ENEXSS example) 3D device simulation for SOI source current SOI NMOS BOX 2006/10/31 particle injection M. Hazumi (KEK) 6 Diode TEG simulation (unit: mm) 2006/10/31 M. Hazumi (KEK) 7 Diode TEG simulation Center (N+) Guard (P+) Bulk (N-) N-substrate P+ > 0 current (unit: mm) baskside fixed at 0V 2006/10/31 M. Hazumi (KEK) 8 Diode TEG simulation Measurements 2006/10/31 M. Hazumi (KEK) 9 TCAD for SOIPIX R&D Useful to obtain field maps device characteristics signals induced by particles • Handle wafer (i.e. sensor) simulation – Pixel and guard ring design optimization • Breakdown voltage • Charge collection – Problem finding/solving before fabrication • Effect of bias voltage on readout electronics – I/O pads – p-stops for P-substrate option 2006/10/31 M. Hazumi (KEK) 10 Breakdown voltage Results of measurements are reported by H. Miyake: Breakdown voltage ~ 100V at bias-ring edges. 2006/10/31 M. Hazumi (KEK) 11 Breakdown voltage simulation simulated depth = 130mm ~-92V ENEXSS 3D process/device simulation 2006/10/31 M. Hazumi (KEK) 12 Electric field simulation at Vbias = -92V 2006/10/31 M. Hazumi (KEK) 13 Breakdown voltage simulation with different configurations ** Simulation with smaller pixels: lower breakdown voltages than the previous case 90 -45V 120 -65V 135 -70V 150 -100V Improvements for the next submission 2006/10/31 M. Hazumi (KEK) 14 Effect of bias voltage on readout electronics 2006/10/31 M. Hazumi (KEK) 15 Back gate effect Threshold variation (measurements) Substrate voltage acts as Back Gate, and changes transistor threshold. ON Back Gate • Backbias should be less than ~8V; otherwise always ON. • Problem specific to Monolithic detectors – readout electronics very close to sensors • Can we reproduce it with TCAD ? 2006/10/31 M. Hazumi (KEK) 16 Problem Finding with Device Simulation 20 -10 0 +10 Backbias (V) VB (V) 16 12 8 4 0 -4 -20 -8 Vts0(V) -12 backbias supplied here ENEXSS TCAD -16 handle wafer 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -20 BOX Threshold voltage (V) NMOS +20 Measurements reproduced With backbias > 8V, NMOS becomes always ON. Substrate voltage under Tr should be kept low. 2006/10/31 M. Hazumi (KEK) 17 P+ implantation to reduce back gate effect Weakest part: I/O buffer 2006/10/31 M. Hazumi (KEK) 18 P+ implantation to reduce back gate effect Additional p+ implantation (with voltage fixed at 0V or with some “anti-bias”) should help reduce the back gate effect. How close should they be to the I/O pads ? 2006/10/31 M. Hazumi (KEK) 19 Simulation setup distance (80, 5, 2mm) NMOS BOX (5 mm wide P+, 1 x 1020 cm-3) Bulk: N- (~700ohm cm, 6 x 1012 cm-3) 350mm Gate threshold voltage at Id= w/L*1e-7 A measured with Vd=1V Backbias (0-20 V) Should we perform 3D simulation ? Comparison made; results don’t show big difference. 2D ~ 10 min., 3D~3days ! choose 2D for this study 2006/10/31 M. Hazumi (KEK) 20 Threshold voltage vs. Bias voltage Large improvement in case of distance = 2mm Vth > 0.25V at VB = 100V ! T hreshold voltage V_B = 0~20 V V th (V ) Threshold voltage 0.4 0.3 0.2 V th (V ) 0.1 0 -0.1 0 10 20 -0.2 -0.3 -0.4 -0.5 -0.6 V_B (V) 0.4 0.35 0.3 0.25 0.2 0.15 0.1 0.05 0 -0.05 0 -0.1 -0.15 distance 80mm 5mm 2mm 50 100 V _B (V ) 2006/10/31 M. Hazumi (KEK) 21 P-substrate option 2006/10/31 M. Hazumi (KEK) 22 n+ guard ring p+ stop n+ pixel p substrate (1.5k ohm) 2006/10/31 M. Hazumi (KEK) 23 Backgate problem on pixel readout electronics Device simulation p-stop voltage 0 SOIPIX readout electronics very close to p-stops may suffer from this “backbias”. p-stops ATHENA/ATLAS TCAD 2006/10/31 M. Hazumi (KEK) 24 Interface charge (qf) n+ pixels qf = 0 V(p-stop) = -45V qf = 3e11/cm2 V(p-stop) = -27.5V qf = 1e13/cm2 V(p-stop) = -23.5V Effect depends on irradiation. 2006/10/31 M. Hazumi (KEK) 25 P-stop optimization (1 small pixel in 1 cell) p-stops 2 2 2 1 4 1 1 2 1 2 (common) V(p-stop) [V] -23.5 -20 -14.5 -11 V(p-p) [V] -22 -18.5 -13 -11 Vbias = -500V for 250mm thick p-bulk Best result smaller |Vbias| sufficient for thinner detector Cf. 1/1/1 must be even better 2006/10/31 Max. Efield (105V/cm) 10 10 5 9 M. Hazumi (KEK) 26 Pixel configuration 1 small pixel in 1 cell 20mm 1 large pixel in 1 cell 4 small pixels in 1 cell (octagon for actual design) Which is better to avoid microdischarge ? Which makes the p-stop potential closer to 0 ? no difference is seen for qf=1e13/cm2 2006/10/31 M. Hazumi (KEK) 27 Choice of pixel design • • • • 2006/10/31 4 n+ octagons in one pixel individual p-stops p-stop as thin as possible (1mm) p-stop distance as close as possible (1-2 mm) M. Hazumi (KEK) 28 Summary • Handle wafer (i.e. sensor) simulation – Pixel and guard ring design optimization • Breakdown voltage well understood and new designs proposed – Problem finding/solving before fabrication • Effect of bias voltage on readout electronics – New P+ bias rings proposed for I/O pads – P-substrate option seems more complicated because of p-stops • TCAD is very useful for SOIPIX R&D ! 2006/10/31 M. Hazumi (KEK) 29 Backup Slides 2006/10/31 M. Hazumi (KEK) 30 TCAD at work for sensor R&D (1) 2006/10/31 M. Hazumi (KEK) 31 TCAD at work for sensor R&D (2) 2006/10/31 M. Hazumi (KEK) 32 Aluminum (0V) 1000nm distance to the 1st metal 2006/10/31 M. Hazumi (KEK) 33 End 2006/10/31 M. Hazumi (KEK) 34