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DISPLAY DEVICE AND METHOD OF DRIVING THE SAME BACKGROUND OF THE INVENTION 1. 5 Field of the Invention The invention relates to a display device and a method of driving the same. In particular, the invention relates to a method of driving a display device that can prevent defects of residual images by discharging residual charges in storage capacitors. 10 2. Description of the Related Art Liquid crystal displays change an electric field at both ends of liquid crystal, control the alignment of the liquid crystal, and adjust transmittance of light passing through the liquid crystal so as to display images. 15 At this time, in order to maintain the electric field at both ends of the liquid crystal, storage capacitors are used. However, in known storage capacitors according to an independent wiring method, since one terminal of each of the storage capacitors is connected to a common voltage, residual charges having been charged in the 20 storage capacitors may not be easily discharged but remain. Therefore, there occurs a problem in which residual images occur due to the residual charges. SUMMARY OF THE INVENTION 25 Accordingly, the invention has been finalized in order to 1 solve the above-described problems, and it is an object of the invention to provide a display device and a method of driving the same that can prevent residual images from occurring due to residual charges by applying a dummy gate signal and a dummy 5 data signal after one frame signal finishes and discharging the residual charges in pixel capacitors. According to an aspect of the invention, a method of driving a display device includes sequentially applying a gate turn-on voltage to a plurality of gate lines during a plurality 10 of image display periods during which unit image frames are displayed, and sequentially applying a plurality of data signals, which correspond to the plurality of gate lines, to a plurality of data lines, and applying the gate turn-on voltage to the plurality of gate lines during vertical blank periods 15 provided between the image display periods, and applying a dummy data signal to the plurality of data lines an apparatus for forming a pattern for a light guiding plate includes Each of the vertical blank periods may be longer than a period during which a gate turn-on voltage is supplied to one 20 gate line, and shorter than the image display period. There may be 24 to 120 image display periods for one second. The plurality of data signals may be driven in an inversion mode. When the number of the plurality of gate lines is an odd number, odd number of gate turn-on voltages and dummy data 25 signals may be applied during each of the vertical blank periods. 2 When the number of the plurality of gate lines is an even number, even number of gate turn-on voltages and dummy data signals may be applied during each of the vertical blank periods. As the dummy data signal, a signal that corresponds to the 5 maximum or minimum pixel gray value may be used. The gate turn-on voltage may be applied to the plurality of gate lines at the same time during each of the vertical blank periods. According to another aspect of the invention, a display 10 device includes a liquid crystal display panel including a plurality of gate lines and a plurality of data lines, a gate driver connected to the plurality of gate lines, sequentially supplying a gate turn-on voltage to the plurality of gate lines or simultaneously supplying the gate turn-on voltage to the 15 plurality of gate lines, and a data driver connected to the plurality of data lines, supplying a plurality of data signals, which correspond to the plurality of gate lines, to the plurality of data lines, or supplying a dummy data signal to the plurality of data lines. 20 The gate driver may include a plurality of stages sequentially supplying the gate turn-on voltage to the plurality of gate lines, and a discharge controller provided between the plurality of stages and the plurality of gate lines and supplying the gate turn-on voltage, which is output by the 25 gate driver, to the plurality of gate lines at the same time 3 according to a control signal that is input from the outside. The discharge controller may include a plurality of OR gates or exclusive OR gates that are connected to the plurality of gate lines, respectively. 5 The liquid crystal display panel may further include a plurality of thin film transistors, pixel capacitors, and storage capacitors that are provided at intersections between the plurality of gate lines and the plurality of data lines, and one electrode terminal of each of the pixel capacitors and 10 the storage capacitors may be connected to each of the thin film transistors, and the other electrode terminal thereof may be connected to a common voltage. BRIEF DESCRIPTION OF THE DRAWINGS 15 FIG. 1 is a block conceptual diagram illustrating a display device according to a first embodiment of the invention; FIG. 2 is a signal waveform diagram illustrating the operation of the display device according to the first embodiment of the invention; 20 FIG. 3 is a signal waveform diagram illustrating the operation of the display device according to the number of gate lines according to the first embodiment of the invention; FIG. 4 is a signal waveform diagram illustrating the operation of the display device according to the number of gate 25 lines according to the first embodiment of the invention; 4 FIG. 5 is a block diagram illustrating a liquid crystal display panel and a gate driver according to a second embodiment of the invention; and FIG. 6 is a waveform diagram illustrating the operation 5 of a liquid crystal display according to the second embodiment of the invention. DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, 10 embodiments of the invention will be described in detail with reference to the accompanying drawings. The invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided such that this disclosure will be thorough and complete and will 15 fully convey the concept of the invention to those skilled in the art. FIG. 1 is a block conceptual diagram of a display device according to a first embodiment of the invention. FIG. 2 is a signal waveform diagram illustrating the operation of a 20 display device according to a first embodiment of the invention. FIGS. 3 and 4 are signal waveform diagrams illustrating the operation of the display device according to the number of gate lines according to the first embodiment of the invention. Referring to FIGS. 1 to 4, a display device according to 25 this embodiment includes a liquid crystal display panel 100, 5 a gate driver 200, a data driver 300, a driving voltage generator 400, and a signal controller 500. The liquid crystal display panel 100 includes a plurality of gate lines G1 to Gn that substantially extend in a column 5 direction and a plurality of data lines D1 to Dm that substantially extend in a row direction and are orthogonal to the plurality of gate lines G1 to Gn, and pixels that are provided at intersections between the gate lines G1 to Gn and the data lines D1 to Dm. 10 Each of the pixels includes a thin film transistor T, a storage capacitor Cst, and a pixel capacitor Clc. The pixels include pixels of red (R), green (G), and blue (B), and natural colors can be displayed by a combination of the pixels red (R), green (G), and blue (B). The liquid crystal display panel 100 includes a thin film transistor substrate (not 15 shown) on which the thin film transistors T, the gate lines G1 to Gn, the data lines D1 to Dm, pixel electrodes, and storage electrodes are formed, a common electrode substrate (not shown) on which a black matrix, color filters, and a common electrode are formed, and liquid crystal (not shown) provided between the 20 thin film transistor substrate and the common electrode substrate. The storage capacitor Cst and the pixel capacitor Clc share the pixel electrode. Here, the thin film transistors T have gate terminals that are connected to the gate lines G1 to Gn, source terminals that 25 are connected to the data lines D1 to Dm, and drain terminals 6 that are connected to the pixel electrodes. In this way, the thin film transistors T operate according to a gate turn-on voltage, which is applied to the gate lines G1 and Gn, and supply data signals (i.e., gray voltages) across the data lines D1 to 5 Dm to the pixel electrodes, each of which is used as one electrode terminal of the pixel capacitor Clc and the storage capacitor Cst, so as to change an electric field at both ends of each of the pixel capacitor Clc. As such, the arrangement of liquid crystal inside the liquid crystal display panel 100 is changed, 10 such that it is possible to adjust the transmittance of light that is supplied from a backlight. A plurality of cutouts and/or a protrusion pattern may be provided on the pixel electrode as a domain controlling unit that controls a direction in which the liquid crystal is aligned, and a protrusion and/or 15 a cutout pattern may be provided on the common electrode. In this embodiment, it is preferable that the liquid crystal be aligned in a vertically aligned mode. A controller that supplies signals for driving the liquid crystal display panel 100 is provided outside the liquid crystal 20 display panel 100. The controller includes a gate driver 200, a data driver 300, a driving voltage generator 400, and a signal controller 500. Here, the gate driver 200 and/or the data driver 300 may be mounted on the thin film transistor substrate of the liquid 25 crystal display panel 100, or may be mounted on a separate 7 printed circuit board (PCB) and then electrically connected to the liquid crystal display panel 100 through a flexible printed circuit board (FPC). In this embodiment, it is preferable that the gate driver 200 and the data driver 300 be manufactured in 5 the form of at least one driving chip and mounted. Further, it is preferable that the driving voltage generator 400 and the signal controller 500 be mounted on the printed circuit board and electrically connected to the liquid crystal display panel 100 through the flexible printed circuit. 10 The signal controller 500 receives an input image signal from an external graphic controller (not shown), that is, an input control signal for controlling pixel data (R, G, and B) and display of the pixel data (R, G, and B), for example, a vertical 15 synchronization signal Vsync, a horizontal synchronization signal Hsync, a main clock CLK, and a data enable signal DE. The signal controller 500 processes the pixel data according to operating conditions of the liquid crystal display panel 100, generates a gate control signal and a data control signal, and transmits the gate control signal to the 20 gate driver 200. Here, the pixel data is rearranged according to the alignment of the pixels of the liquid crystal display panel 100. The gate control signal includes a vertical synchronization start signal that instructs to start outputting the gate turn-on voltage Von, a gate clock signal, output enable 25 signal, and the like. The gate control signal further includes 8 a gate open signal that applies the gate turn-on voltage to all of the gate lines. The data control signal includes a horizontal synchronization start signal that informs the start of transmission of the pixel data, a load signal that instructs 5 to apply a data voltage to a corresponding data line, an inversion signal that inverts a polarity of a gray voltage with respect to the common voltage, a data clock signal, and the like. The data control signal further includes a dummy control signal that outputs a dummy data signal. 10 The driving voltage generator 400 generates various driving voltages that are needed to drive the liquid crystal display by using an external voltage that is input from an external power supply. The driving voltage generator 400 generates a reference voltage GVDD, a gate turn-on voltage Von, 15 a gate turn-off voltage Voff, and a common voltage. The driving voltage generator 400 applies the gate turn-on voltage Von and the gate turn-off voltage Voff to the gate driver 200 according to a control signal from the signal controller 500, and applies the reference voltage GVDD to the data driver 300. 20 Here, the reference voltage GVDD is used as a reference voltage for generating gray voltages that drives the liquid crystal. The gate driver 200 applies the gate turn-on/turn-off voltages Von/Voff of the driving voltage generator 400 to the gate lines G1 to Gn according to the external control signal. 25 In this way, it is possible to control the corresponding thin 9 film transistor T such that a gray voltage to be applied to each of the pixels is applied to the corresponding pixel. At this time, the gate driver 200 sequentially applies the gate turn-on voltage Von to the plurality of gate lines G1 to Gn during one 5 image display period 1P. At least once, the gate driver 200 applies the gate turn-on voltage Von to the plurality of gate lines G1 to Gn at the same time during a vertical blank period 1V. At this time, the vertical blank period 1V refers to a period between a point when 10 one image display period 1P finishes and a point when the next image display period 1P starts. That is, as shown in FIG. 2, the vertical blank period 1V refers to a period after the gate turn-on voltage Von is applied to the final gate line Gn in order to display a predetermined image and before the gate turn-on 15 voltage Von is applied again to the first gate line G1. At this time, the image display period 1P refers to a time region in which one image frame can be displayed. During one image display period 1P, data signals are supplied to all of the pixel capacitors Clc inside the liquid crystal display panel 100. 20 The image display period 1P may change according to the number of gate lines G1 to Gn and time during which the gate turn-on voltage Von is supplied to each of the gate lines G1 to Gn. That is, the time during which the gate turn-on voltage V1 is supplied to each of the gate lines G1 to Gn is 1H, and when there are 25 ānā number of gate lines G1 to Gn, the image display period 1P 10 becomes 1H x n. Further, a plurality of image display periods 1P sequentially display one motion picture. In the liquid crystal display according to this embodiment, it is preferable that there exist 24 to 120 image display periods 1P for one second. 5 Here, one image display period 1P may correspond to one frame frequency 1F or one image display period 1p and one vertical blank period 1v may correspond to one frame frequency 1F. It is preferable that the vertical blank period 1V be longer than the time 1H during which the gate turn-on voltage Von is applied 10 to each of the gate lines G1 to Gn and shorter than the image display period 1P (1H<1V<1P). When the vertical blank period 1V is shorter than the time 1H, it is difficult to supply the gate turn-on voltage Von to all of the gate lines G1 to Gn at the same time. 15 When the vertical blank period 1V is larger than the image display period 1P, it is difficult to smoothly display an image. The data driver 300 generates gray voltages (i.e., data signals) by using a control signal of the signal controller 500 and the reference voltage GVDD of the driving voltage generator 20 400, and applies the generated gray voltages to the data lines D1 to Dm, respectively. That is, the data driver 300 converts the input pixel data of a digital format data into data signals DS1 to DSn of an analog format by using the reference voltage GVDD. Of course, the data driver 300 generates a dummy data 25 signal DS of an analog format according to an external control 11 signal. The data driver 300 generates a plurality of gray voltages by using the reference voltage GVDD. Further, during one image display period 1P, the data driver 300 changes the pixel data 5 of the digital format, which is applied from the signal controller 500, into the data signals DS1 to DSn of the analog format by using the gray voltages, and outputs the data signals DS1 to DSn to the corresponding data lines D1 to Dm, respectively. Accordingly, as shown in FIG. 2, the data signal DS1 is applied 10 to the first gate line G1, the second data signal DS2 is applied to the second gate line G2, the n-1-th data signal DSn-1 is applied to the n-1-th gate line Gn-1, and the n-th data signal DSn is applied to the n-th line Gn. At this time, it is preferable that the data signals DS1 to DSn be supplied while 15 voltages for the data signals have opposite polarities according to the gate lines G1 to Gn adjacent to the data signals DS1 to DSn. That is, preferably, the first data signal DS1 has a positive polarity, the second data signal DS2 has a negative polarity. 20 The data driver 300 generates the dummy data signal DSd at least once during the vertical blank period 1V by using the gray voltages. At this time, the data driver 300 preferably applies the dummy data signal DSd, which is a signal that discharges residual charges of the storage capacitor Cst in the 25 liquid crystal display panel 100 so as to prevent residual 12 images from occurring due to the residual charges. That is, the data driver 300 generates the dummy data signal DSd that eliminates the charging of the storage capacitors Cst and supplies the generated dummy data signal DSd to the plurality 5 of data lines D1 to Dm during the vertical blank period 1V. It is preferable that the dummy data signal DSd should have either the maximum value or the minimum value of a pixel gray voltage, which may change according to a liquid crystal mode in the display panel. 10 That is, when the liquid crystal mode in the liquid crystal display panel 100 is a normally-white mode, the data driver 300 generates a dummy data signal DSd corresponding to normally white and applies the dummy data signal DSd to the plurality of data lines D1 to Dm. When the liquid crystal mode is a normally-black mode, the data driver 300 generates a dummy 15 data signal DSd corresponding to normally black and applies the dummy data signal DSd to the plurality of data lines D1 to Dm. At this time, the liquid crystal display panel 100 displays white or black-based color by the dummy data signal DSd, but the vertical blank period 1V is so short that a user does not 20 recognize the displayed color as a residual image. As such, the dummy data signal DSd is applied such that the charges remaining in the storage capacitor Cst can be forcibly discharged and the residual images can be prevented from occurring. 25 Of course, at this time, it is preferable that one of the data signals DS1 to DSn has opposite signal polarities 13 with respect to the other adjacent data signals DS1 to DSn. Hereinafter, the operation of the display device according to this embodiment will be described with reference to the waveform diagram of FIG. 2. 5 The display device includes a plurality of image display period 1P, and vertical blank periods 1V that are provided between the plurality of image display periods 1P. The display device displays an image through the liquid crystal display panel 100 during the image display period 1P, and during the 10 vertical blank period 1V, the display device synchronizes a plurality of control signals and discharges residual charges of the storage capacitors Cst in the liquid crystal display panel 100. During the image display period 1P, the gate driver 200 15 of the display device sequentially applies a gate turn-on voltage Von to the plurality of gate lines G1 to Gn, and the data driver 300 supplies the plurality of data signals DS1 to DSn to the plurality of data lines D1 to Dm. During the vertical blank period 1V, the gate driver 200 of the display device 20 applies the gate turn-on voltage Von to the plurality of gate lines G1 to Gn at the same time, and the data driver 300 supplies the dummy data signal DSd to the plurality of data lines D1 to Dm. That is, as shown in FIG. 2, during one image display period 25 1P, the gate turn-on voltage Von is sequentially applied to the 14 first to n-th gate lines G1 to Gn, and the plurality of thin film transistors T that are connected to the gate lines G1 to Gn applied with the gate turn-on voltage Von are turned on. Meanwhile, the first to n-th data signals DS1 to DSn are applied 5 to the data lines D1 to Dm and accordingly supplied to the pixel capacitors Clc and the storage capacitors Cst that are connected to the thin film transistors T that are turned on. This will be described in more detail as follows. When the gate turn-on voltage Von is applied to the first gate line 10 G1 and the first data signal DS1 is applied to the plurality of data lines D1 to Dm, the plurality of thin film transistor T that are connected to the first gate line G1 are turned on according to the gate turn-on voltage Von, and by the plurality of thin film transistor that are turned on, the first data signal 15 DS1 is supplied to the plurality of pixel capacitors Clc and the storage capacitors Cst that are connected to the thin film transistors T are turned on. Then, the gate turn-on voltage Von is sequentially applied to second to n-th gate lines G2 to Gn, and accordingly, second to n-th data signals DS2 to DSn are 20 applied to the plurality of data lines D1 to Dm. Therefore, the second to n-th data signals DS2 and DSn are supplied to all of the pixel capacitors Clc and the storage capacitors Cst inside the liquid crystal display panel 100. In this way, the alignment of the liquid crystal in the pixel capacitors Clc is 25 changed according to the data signals DS1 to DSn that are applied 15 to the pixel capacitors Clc, such that the transmittance of light passing through the liquid crystal is controlled and an image is displayed. Here, when the gate turn-on voltage Von is applied to one of the gate lines G1 to Gn, the gate turn-off 5 voltage Voff is applied to the other gate lines G1 to Gn. Further, it is preferable that for the first to n-th data signals DS1 to DSn, voltages for odd data signals and even data signals have opposite polarities. That is, the liquid crystal display panel 100 is driven in a line inversion mode. 10 The gate turn-on voltage Von is preferably supplied to the first to n-th gate lines G1 to Gn according to a gate clock signal (not shown) of the signal controller 500. It is preferable that the gate turn-on voltage Von be supplied during the time 1H. As shown in FIG. 2, the gate turn-on voltage Von is applied 15 to the first to n-th gate lines G1 to Gn at the same time during the vertical blank period 1V, such that all of the thin film transistors T inside the liquid crystal display panel 100 are turned on. At this time, the dummy data signal DSd is applied to the data lines D1 to Dm, and supplied to all of the pixel 20 capacitors Clc and the storage capacitors Cst by the thin film transistors T that are turned on. In this way, the residual charges in the storage capacitors Cst inside the liquid crystal display panel 100 can be completely discharged, and thus residual images can be prevented from occurring due to the 25 residual charges. As the dummy data signal DSd, a signal 16 corresponding to the normally white or a signal corresponding to normally black may be used according to the liquid crystal mode. That is, as the dummy data signal DSd, a signal capable of returning the liquid crystal whose alignment is changed to 5 an initial position is preferably used. The gate turn-on voltage Von and the dummy data signal DSd may be supplied at a time when the vertical blank period 1V starts, or may be supplied during the vertical blank period 1V. Further, a width where the gate turn-on voltage Von is supplied is 10 preferably 1H. Of course, the width may be larger than the 1H in order to sufficiently supply the dummy data signal DSd to the pixel capacitors Clc and the storage capacitors Cst. Here, since the liquid crystal display panel 100 performs the line inversion, the dummy data signal DSd that is supplied 15 during the vertical blank period 1V may change according to the number of gate lines G1 to Gn. That is, as shown in FIG. 3, when there are odd number of gate lines G1 to G2n-1, the gate turn-on voltage Von and the dummy data signal DSd are applied once. 20 Of course, odd number of gate turn-on voltages Von and dummy data signals DSd may be supplied. On the other hand, there are even number of gate lines G1 to G2n, the gate turn-on voltage Von and the dummy data signal DSd are applied twice. Of course, even number of gate turn-on voltages Von and dummy data signals DSd may be supplied. 25 This changes according to the polarity of the data signal 17 DSn that is finally applied during one image display period 1P. That is, as shown in FIG. 3, when there are odd number of gate lines G1 to G2n-1, the final data signal DS2n-1 that is applied through the final gate line G2n-1 has a positive polarity. 5 Therefore, a signal that is finally charged to the storage capacitor Cst also has a positive polarity. In order that the storage capacitor Cst is empty and has a negative polarity, a dummy data signal DSd having a negative polarity is applied once. Meanwhile, as shown in FIG. 4, when there are even number of 10 gate lines G1 to G2n, the final data signal DS2n that is applied through the final gate line G2n has a negative polarity. Therefore, a signal that is finally charged to the storage capacitor Cst also has a negative polarity. In order that the storage capacitor Cst is empty and has a negative polarity, the 15 first dummy data signal DSd-1 having a positive polarity needs to be applied first, and the second dummy data signal DSd-2 having a negative polarity needs to be then applied. As described above, all the charges in the storage capacitors Cst are discharged during the vertical blank period 20 1V to thereby prevent residual images from occurring. Further, as the charges in the storage capacitor Cst are completely discharged, they may not affect the first to n-th data signals DS1 to DSn that are applied during the next image display period 1P. 25 The invention is not limited to the description having been made, and image display periods and vertical blank periods may 18 be different from each other according to gate lines. Of course, the invention is not limited to the description having been made. When plurality of stages are used as the gate driver, logic gates that supply a gate turn-on voltage to all 5 of the gate lines at the same time may be further included. Hereinafter, a liquid crystal display according to a second embodiment of the invention will be described. The description to be made below that overlap the description having been made will be omitted. 10 A technique of the description to be made below may be applied to the above-described first embodiment. FIG. 5 is a block diagram illustrating a liquid crystal display panel and a gate driver according to a second embodiment of the invention. FIG. 6 is a waveform diagram illustrating the operation of the liquid crystal display according to the 15 second embodiment of the invention. Referring to FIGS. 5 and 6, the display device according to this embodiment includes a liquid crystal display panel 100 that has thereon a plurality of gate lines G1 to Gn, a plurality of data lines D1 to Dm, thin film transistors T, pixel capacitors 20 Clc, and storage capacitor Cst, a gate driver 200 that includes a plurality of stages 210-1 to 210-n and a discharge controller 220, which are connected to the plurality of gate lines G1 to Gn, a data driver 300 that is connected to the data lines D1 to Dm, and a signal controller (not shown) that controls these 25 components. 19 The gate driver 200 is formed at the edge of one side of a thin film transistor substrate of the liquid crystal display panel 100. That is, when the thin film transistor substrate of the liquid crystal display panel 100 is manufactured, the 5 gate driver 200 is preferably manufactured together. The gate driver 200 includes the stages 210-1 to 210-n as much as the number of gate lines G1 to Gn, and the discharge controller 220 includes logic gates 220-1 to 220-n as much as the number of the gate lines G1 to Gn. 10 That is, the stages 210-1 to 210-n and the logic gates 220-1 to 220-n are connected to the gate lines G1 to Gn, respectively. At this time, the stages 210-1 to 210-n operate according to a vertical synchronization start signal STV or output of a previous stage, and supply a gate turn-on voltage Von or a gate turn-off voltage Voff to the 15 logic gates 220-1 to 220-n in the discharge controller 220 by using a clock signal CLK or an inverted clock signal CLKB. The logic gates 220-1 to 220-n operate according to an external gate voltage control signal Sag. Further, the logic gates 220-1 to 220-n supply the gate turn-on voltage Von or the gate turn-off 20 voltage Voff, which are applied from the stages 210-1 to 210-n, to the gate lines G1 to Gn, or change a level of the gate turn-off voltage Voff and supply the gate turn-on voltage Von to the gate lines G1 to Gn. To this end, as shown in FIG. 5, it is preferable that OR gates should be used as the logic gates 220-1 to 220-n 25 in the discharge controller 220. 20 Alternatively, exclusive OR gates are used such that the gate turn-on voltage is applied to the gate lines G1 to Gn at the same time in the same manner when the OR gates are used. Of course, the logic gates 220-1 to 220-n in the discharge controller 220 are not limited thereto, 5 but a plurality of switching elements that operate according to the external gate voltage control signal Sag and supply a separate gate turn-on voltage to the logic gates 220-1 to 220-n may be used. Here, the external gate voltage control signal Sag maintains a logic-low state during an image display period 10 1P, and a logic-high state for a predetermined time during a vertical blank period 1V. The operation of the display device that includes the gate driver having the above-described structure will now be described with reference to the drawing. 15 First, a vertical synchronization start signal STV is applied just before an image display period 1P starts. Therefore, the first stage 210-1 operates at the same time when the image display period 1P starts. Then, the first stage 210-1 outputs a gate turn-on voltage Von and supplies the gate turn-on 20 voltage Von to the first gate line G1 through the first logic gate 220-1. The plurality of thin film transistors T that are connected to the first gate line G1 are then turned on, and the first data signal DS1 that is applied to the plurality of data lines D1 to Dm is supplied to the pixel capacitors Clc and the 25 storage capacitors Cst. Hereinafter, second to n-th stages 21 210-2 to 210-n operate according to output of the previous first to n-1-th stages 210-1 to 210-n-1 and sequentially output a gate turn-on voltage Von. Further, by the second to n-th logic gates 220-2 to 220-n that are connected to the second to n-th stages 5 210-2 to 210-n, the second to n-th stages 210-2 to 210-n sequentially supply the gate turn-on voltage Von. As described above, since a signal in a logic low state is applied to first to n-th logic gates 220-1 to 220-n that are connected to the first to n-th stages 210-1 to 210-n, output of the first to n-th 10 stages 210-1 to 210-n becomes output of the first to n-th logic gates 220-1 to 220-n during the image display period 1P. Here, the operation of the stages 210-1 to 210-n is stopped by output of a next stage. To this end, a separate dummy stage (not shown) may be provided at the next stage of the final n-th stage 210-n. 15 Further, it is preferable that the stages whose operation is stopped output a gate turn-off voltage Voff in a logic low state. Then, as described above, when the vertical blank period V1 starts, the external gate voltage control signal Sag becomes a logic high. 20 Therefore, output of the first to n-th logic gates 220-1 to 220-n becomes a gate turn-on voltage Von in a logic high state. Accordingly, the gate turn-on voltage Von is applied to the first to n-th logic gates 220-1 to 220-n, which are connected to the first to n-th gate lines G1 to Gn, at the same time, such that all of the thin film transistors T in the 25 liquid crystal display panel 100 are turned on. 22 In this way, the dummy data signal DSd is applied to all of the pixel capacitors Clc and the storage capacitors Cst in the liquid crystal display panel 100, thereby eliminating the residual charges in the storage capacitors Cst. 5 As described above, the vertical blank periods are positioned between the image display periods during which images are displayed, the gate turn-on voltage is applied to all of the gate lines during the vertical blank periods, and the dummy data signal for discharging the storage capacitors 10 is applied so as to forcibly discharge residual charges in the storage capacitors, such that it is possible to prevent residual images from occurring. Although the invention has been described with reference to the accompanying drawings and the preferred embodiments, the 15 invention is not limited thereto, but is defined by the appended claims. Therefore, it should be noted that various changes and modifications can be made by those skilled in the art without departing from the technical spirit of the appended claims. 23 WHAT IS CLAIMED IS: 1. A method of driving a display device, the method comprising: sequentially 5 applying a gate turn-on voltage to a plurality of gate lines during a plurality of image display periods during which unit image frames are displayed, and sequentially applying a plurality of data signals, which correspond to the plurality of gate lines, to a plurality of data lines; and 10 applying the gate turn-on voltage to the plurality of gate lines during vertical blank periods provided between the image display periods, and applying a dummy data signal to the plurality of data lines. 15 2. The method of claim 1, wherein each of the vertical blank periods is longer than a period during which a gate turn-on voltage is supplied to one gate line, and shorter than the image display period. 20 3. The method of claim 1, wherein there are 24 to 120 image display periods for one second. 4. The method of claim 1, wherein the plurality of data signals are driven in an inversion mode. 25 24 5. The method of claim 1, wherein when the number of the plurality of gate lines is an odd number, odd number of gate turn-on voltages and dummy data signals are applied during each of the vertical blank periods. 5 6. The method of claim 1, wherein when the number of the plurality of gate lines is an even number, even number of gate turn-on voltages and dummy data signals are applied during each of the vertical blank periods. 10 7. The method of claim 1, wherein as the dummy data signal, a signal that corresponds to the maximum or minimum pixel gray value is used. 15 8. The method of claim 1, wherein the gate turn-on voltage is applied to the plurality of gate lines at the same time during each of the vertical blank periods. 9. 20 A display device comprising: a liquid crystal display panel including a plurality of gate lines and a plurality of data lines; a gate driver connected to the plurality of gate lines, sequentially supplying a gate turn-on voltage to the plurality of gate lines or simultaneously supplying the gate turn-on 25 voltage to the plurality of gate lines; and 25 a data driver connected to the plurality of data lines, supplying a plurality of data signals, which correspond to the plurality of gate lines, to the plurality of data lines, or supplying a dummy data signal to the plurality of data lines. 5 10. The display device of claim 9, wherein the gate driver includes: a plurality of stages sequentially supplying the gate turn-on voltage to the plurality of gate lines; and 10 a discharge controller provided between the plurality of stages and the plurality of gate lines and supplying the gate turn-on voltage, which is output by the gate driver, to the plurality of gate lines at the same time according to a control signal that is input from the outside. 15 11. The display device of claim 10, wherein the discharge controller includes a plurality of OR gates or exclusive OR gates that are connected to the plurality of gate lines, respectively. 20 12. The display device of claim 9, wherein the liquid crystal display panel further includes a plurality of thin film transistors, pixel capacitors, and storage capacitors that are provided at intersections between the plurality of gate lines 25 and the plurality of data lines, and 26 one electrode terminal of each of the pixel capacitors and the storage capacitors is connected to each of the thin film transistors, and the other electrode terminal thereof is connected to a common voltage. 5 27 ABSTRACT OF THE DISCLOSURE The invention relates to a display device and a method of driving the same. 5 The method of driving a display device includes sequentially applying a gate turn-on voltage to a plurality of gate lines during a plurality of image display periods during which unit image frames are displayed, and sequentially applying a plurality of data signals, which correspond to the plurality of gate lines, to a plurality of 10 data lines, and applying the gate turn-on voltage to the plurality of gate lines during vertical blank periods provided between the image display periods, and applying a dummy data signal to the plurality of data lines. 28 [FIG. 1] 5 200: GATE DRIVER 300: DATA DRIVER 400: DRIVING VOLTAGE GENERATOR 500: SIGNAL CONTROLLER [FIG. 3] DS POLARITY 10 [FIG. 4] DS POLARITY [FIG. 5] 15 210-1: FIRST STAGE 210-2: SECOND STAGE 210-3: THIRD STAGE 210-N: N-TH STAGE 300: DATA DRIVER 29