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IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 5, NO. 1, MARCH 2005
Validity of Constant Voltage Stress Based Reliability
Assessment of High- Devices
Byoung Hun Lee, Rino Choi, Jang Hoan (Johnny) Sim, Siddarth A. Krishnan, Student Member, IEEE,
Jeff J. Peterson, Senior Member, IEEE, George A. Brown, Life Senior Member, IEEE, and Gennadi Bersuker
Invited Paper
Abstract—Charge trapping in high- gate dielectrics affects
the result of electrical characterization significantly. DC mobility
degradation and device threshold voltage instability and C–V and
I–V hysteresis are a few examples. The charging effects in highgate dielectric also affect the validity of conventional reliability
test methodologies developed for SiO2 devices. In this paper, we
review high- materials specific phenomena that can affect the
validity of constant-voltage-stress-based reliability test methods to
address the direction of future reliability study on high- devices.
Index Terms—Bias temperature instability (BTI), charge trapping, high- dielectrics, hot-carrier injection (HCI), metal gate, reliability, time-dependent dielectric breakdown (TDDB).
I. INTRODUCTION
H
IGH- gate dielectrics are expected to have significant
charge trapping problems related to structural defects,
in particular, oxygen vacancies [1]–[4]. The small bandgap of
high- materials additionally contributes to charge trapping due
to enhanced tunneling probability. Also, many negative aspects
of charge trapping in high- device performances, such as dc
mobility degradation and device threshold voltage instability,
have been investigated in addition to C–V and I–V hysteresis
[5]. Even though the existence of charge trapping is acknowledged as a critical problem of high- devices, the implications
of charge trapping on the reliability evaluation has not been
fully investigated. In many cases, conventional reliability test
methodologies developed for SiO devices have been applied
to high- devices and the results have been interpreted based
on the models developed for silicon dioxide gate dielectrics.
However, the transient nature of the charge trapping in highdielectrics raises questions on the validity of conventional reliability tests. In this paper, we review specific phenomena of
high- materials that can affect the validity of constant-voltagestress-based reliability test methods, such as time-dependent dielectric breakdown (TDDB) and hot-carrier injection (HCI), to
Manuscript received October 6, 2004; revised November 14, 2004.
B. H. Lee is with SEMATECH, Austin, TX 78749 USA (e-mail: [email protected]), as an IBM assignee.
R. Choi, J. H. Sim, S. A. Krishnan, and G. A. Brown are with SEMATECH,
Austin, TX 78749 USA.
J. J. Peterson is with SEMATECH, Austin, TX 78749 USA, as an Intel assignee.
Digital Object Identifier 10.1109/TDMR.2005.845807
Fig. 1. Trace of drain current measured with pulse I–V measurement system.
NMOS with poly gate/HfSiO 3.5-nm stack is used and W/L is 10 m=1 m.
Interfacial oxide thickness is 1 nm in this sample.
address the direction of future reliability study on high- devices.
II. EFFECTS OF FAST TRANSIENT CHARGING
Transient charging effects refer to a time-dependent charge
trapping and detrapping in high- gate dielectrics observed
during the device operation or during the reliability stress
[6]–[8]. Even though the exact physical mechanisms responsible for transient charging are still under discussion, it can
be roughly classified into fast and slow charging, depending
on the employed characterization methods. In this section, the
implications of fast transient charging on the reliability test
methodology are discussed.
The fast transient charging can affect electrical measurements with a characteristic time in the order of microseconds
or longer, such as the single pulse – with the sufficiently
long pulsewidth or rise times, or the dc – and capacitance.
Fig. 1 shows rapid drain current reduction during the short
voltage pulse applied to the gate. Within 1 ms, more than
25% of the drain current has been lost due to the fast electron
trapping in the gate dielectric and subsequent threshold voltage
increase and associated inversion charge reduction [5]–[7].
The saturation level of transient charge accumulation appears
to be determined by the gate bias, which controls the Id,sat
degradation [5].
1530-4388/$20.00 © 2005 IEEE
LEE et al.: VALIDITY OF CONSTANT VOLTAGE STRESS BASED RELIABILITY ASSESSMENT OF HIGH- DEVICES
21
Fig. 2. Threshold voltage shift during the constant voltage stress and
relaxation showing abrupt V shift at the beginning of stress cycle. NMOS
with poly gate/HfSiO 3.5-nm stack is used and W/L is 10 m=1 m.
The fast transient charging has a significant implication to
reliability test, especially constant voltage stress. Due to the
fast electron trapping, the threshold voltage shift under a substrate injection constant voltage stress shows an instantaneous
increase at the beginning of the stress cycle as shown in Fig. 2.
Charges accumulated in the high- layer increase the electric
field in the top portion of the high- layer while the electric field
in the bottom portion of the high- gate stack is reduced, as illustrated in Fig. 3. In the case of SiO devices, the internal field
deformation due to accumulated charges in the dielectric layer
is a rather slow process that determines reliability characteristics of a given gate stack. Since the internal electric deformation
occurs instantly once the stress bias is applied in case of highgate stack and also, since these charge trappings are extremely
transient, the physical meaning of constant voltage stress such
as time-dependent dielectric breakdown (TDDB) test or charge
test on high- gate dielectric is quite difto breakdown
ferent from that of SiO gate dielectric. First, the electric field
distribution under high gate bias is quite different from the electric field distribution under low gate bias. Thus, extrapolation of
high field stress is not simple. Second, the charge trapping itself
is very transient and can be eliminated by applying a minimal
shift observed during
reverse direction electric field. Thus,
the constant voltage stress does not represent the reliability of
whole gate stack in normal device operation condition.
shift under constant voltage
In the case of high- devices,
stress is expected to show stronger dependence on the gate bias.
The electric field distribution and total amount of charge accumulation within the high- layer appear to be more affected by
.
the gate bias than the total amount of injected charge
shift due to charge trapping is less deFig. 4 shows that the
pendent on
[8]. Once a total amount of fast trapping and a
subsequent conduction band bending is determined by the gate
signifibias, further electrical stress does not change the
cantly as was seen in Fig. 2. This result further supports the
idea that there are two mixed events during the constant voltage
stress. At initial stage, fast transient charging deforms the electric field within high- dielectric and a subsequent stress builds
up more charge in high- dielectric, but the total amount of
charge is determined by the electric field distribution rather than
the density of trap sites.
It should be noted that the fast transient charging is mostly
reversible. The trapped charge can be removed with a minimal
Fig. 3. Band diagram illustrating the charge accumulation during dc stress
(substrate injection case): (a) internal electric field distribution when there is no
localized electron accumulation in high- dielectric; (b) internal electric field
distribution when there is a localized electron accumulation.
Fig. 4. V shift during the positive bias stress on nMOS with poly gate/HfSiO
3.5 nm stack. Interfacial oxide thickness is 1 nm in this sample. Triangle =
2:0 V, Circle = 2:3 V, Square = 2:6 V. The correlation between Q and V
shift is weak.
residual effects to the electrical characteristics of the highdielectric by turning the stress bias off or applying a negative
voltage in the range of 0.5 to 1.5 V [9], [10]. Considering
the fact that the primary purpose of TDDB test is to investigate the dielectric stability with respect to stress-induced defect
generation, the reversibility of charging, with minimum residual
permanent damage in the dielectric, means that the accelerated
constant voltage stress test is not adequate to address the long
term reliability of high- devices. Thus, the breakdown mechanism in the high- devices under high field stress conditions
is less likely related to the intrinsic characteristics of the highfilm as it can be a result of extended high field stress on very
localized portion of high- stack. Wide spreading of Weibull
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IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 5, NO. 1, MARCH 2005
Fig. 5. V shift during the 2.5-V stress on nMOS with poly gate/HfSiO
3.5-nm stack at various temperatures. As the measurement temperature goes
up, the turnaround effect is more pronounced due to enhanced hole trapping.
Fig. 6. V shift during the positive bias stress on nMOS with poly gate/HfSiO
3.5-nm stack at 150 C. As the gate bias increases, the turn around effect due
to enhanced hole trapping is more pronounced. However, the amount of V
recovery during the relaxation cycle is similar, indicating there is similar amount
of concurrent electron trapping.
slope reported in the literature indirectly supports this conjecture even though same results can be explained by immature
process of high- dielectric [11].
III. EFFECTS OF SLOW TRANSIENT CHARGING
The slow transient charging can affect the reliability measurements such as TDDB, HCI, and bias temperature instability
(BTI), which are performed over the duration of seconds or
longer. In this paper, a substrate injection stress for nMOS and
a gate injection stress for pMOS case, which are representative
of device operation condition, are discussed.
In the case of substrate injection at low field stress on highnMOS devices, hole trapping is negligible compared to electron
trapping. However, at high electric fields and high temperatures,
hole-related effects become significant due to hole generation
at polysilicon gate/high- interface by the injected hot electrons, and subsequent diffusion of these holes along the electric field gradient toward the bottom interface of high- layer
[12]. In general, due to small bandgap, the electric field stress
dependence and temperature dependence are much more pronounced for high- dielectric than what has been observed for
SiO . For thin oxide cases, localized charging, mixed charging
and charge loss had been recognized as a source of errors in the
reliability assessment [13]. The mixture of two different degradation mechanisms complicates the interpretation of reliability
test results. Extrapolations of the results of high electric field
test become less accurate for low electric field cases, i.e., operation condition because the dominant device degradation mechanisms are different for different stress regime.
The mixed contributions from the electron and hole trapping
at the high electric field and high temperature conditions causes
a strong turn-around effect of threshold voltage shift under positive bias stress for poly/high- devices as shown in Fig. 5. At
the same temperature, high electric field stress increases the hole
trapping at the interface and enhances the turn around effects
as shown in Fig. 6. Interestingly, no such turn around effect
has been observed at TiN/HfSiO devices [12]. The difference
between TiN/HfSiO and poly/HfSiO devices can be explained
by taking into account negligible electron-hole pair generation
at TiN/HfSiO interface. Because of smaller bandgap, electrons
Fig. 7. V shift during the constant voltage stress (V = 2:6 V) and hot
carrier injection stress (V = V = 2:6 V). nMOS with poly gate/HfSiO
3.5-nm stack at 150 C is used and detrapping is performed at 1 V.
0
passed through the conduction band of HfSiO releases less energy at the electrode and high- dielectric interface. Thus, surface plasmon energy is not enough to generate electron-hole pair
unlike with polysilicon/SiO interface [14].
Hot carrier stress is another example of complication due
to mixed degradation mechanism. Hot carrier stress has been
used in recent works to evaluate the lifetime of high- devices
[15]–[17]. However, it is found that there is a significant cold
carrier accumulation associated with electron trapping on the
pre-existing trapping sites during the hot carrier stress. As
shown in Fig. 7, both constant voltage stress and hot carrier
shift. Even though it is
stress show a similar amount of
not easy to separate the effect of cold carrier trapping and hot
carrier induced trapping, similar trapping and detrapping trend
between constant voltage stress and hot carrier stress indicates
that the effect of cold carrier trapping dominates the hot carrier
stress induced degradation. Small difference might be attributed
to hot carrier specific degradation, but give the nonuniform
stress condition, it is
electric field distribution under
difficult to quantify the contribution of hot carrier induced
shift. However, it is evident that the hot carrier lifetime extrapthan
olated in a conventional way is more dependent on
as the total amount of charge accumulation is proportional to
LEE et al.: VALIDITY OF CONSTANT VOLTAGE STRESS BASED RELIABILITY ASSESSMENT OF HIGH- DEVICES
23
gate bias [18]–[20]. In that sense, hot carrier stress is close to
a derivative of constant voltage stress that has issues described
above and the result of hot carrier stress is not a good indicator
of reliability for high- devices.
IV. REVERSIBILITY OF DEVICE DEGRADATION INDUCED BY
CHARGE TRAPPING
Most reliability tests for SiO device are designed based
on the assumption that the device degradations during the
reliability tests are not reversible and it can be accumulated
over time. In general, charge traps in SiO cannot be eliminated without additional passivation or annealing that are very
different from a normal device operation environment. One
distinct exception will be the NBTI test that shows some degree
of reversibility due to the recombination of hydrogen at the
Si–SiO interface even at room temperature operation condition. The reversibility of NBTI generated a lot of concerns such
as stress and sense interval problem and frequency dependence
of ac stress due to the recombination of hydrogen.
Unfortunately, the transient nature of stress-induced degradation of high- devices poses even bigger challenges in the reliability characterization. As opposed to the stress-induced damage
in the SiO based gate dielectrics, the device degradation due to
the electron trapping in high- materials is reversible in terms of
threshold voltage even though the reversibility varies depending
on the stress bias and the detrapping bias condition [21].
When the stress bias is turned off, charges accumulated
within high- dielectric are spontaneously detrapped due to
a weak built in potential within high- dielectric generated
by the accumulated charges itself. Figs. 2 and 6 showed that
shifted during the constant voltage stress is reversed
the
without an additional driving force. Additional detrapping bias
can enhance the rate of detrapping. As shown in Fig. 7, the
shift due to charge trapping can be eliminated by applying
a detrapping bias for a short period. As the detrapping bias
increases, the amount of residual charge decreases and reaches
to the initial value.
shift due to hot carrier injection
It is worth noting that the
is reversible as constant voltage stress. As shown in Fig. 7, the
relaxation characteristics of hot carrier injection induced
shift are very similar to that of constant voltage stress case while
the hot carrier injection case show residual charges slightly
higher than the constant voltage stress case. This result is
reasonable because hot carrier injection is basically dominated
by cold carrier injection. Even though there is a possibility to
accumulate the effect of hot carrier stress by applying periodic
de-trapping biases, the usefulness of hot carrier stress is very
limited for high- devices due to the mixed charge trapping
and the relaxation during the turn-off period [5], [22].
Up to now, the reversibility of stress induced device degradation has been examined in terms of threshold voltage shift.
There is some possibility that the other characteristics of highdevice such as leakage current may be permanently degraded
while the threshold voltage characteristics are reversible. To examine this assumption, stress-induced leakage current (SILC)
characteristics of TiN/Hf-silicate nMOS is investigated. SILC
is a good indicator for a permanent degradation of gate dielec-
Fig. 8. SILC measured on nMOS with TiN gate/HfSiO 3.5-nm stack is shown
at left axis while V shift measured at the same device is shown in the right
axis. Stress bias was 2.6 V and detrapping bias was 2.6 V. The average level
of SILC is saturated after slight increase at the beginning of stress cycle and
relaxation of SILC is related to V shift.
+
0
tric, especially after low electric field stress. Previously, a permanent defect generation in high- gate dielectric has been reported by Crupi et al. using SILC [23]. In their work, 1.5 V
gate bias was applied for 20 s right before measuring SILC to
detrap the negative charges accumulated during the positive bias
stress. Although detrapping characteristics are strongly dependent on the film stacks such as interfacial oxide thickness and
quality, and defect density in high- layer, this simple detrapping method seems not enough to eliminate the skew from the
residual charges. SILC characteristics of TiN/HfSiO nMOS device investigated in this work show that the SILC is also reversible to some degree. In this work, 2.6 V and 2.6 V gate
shift and SILC are monitored during
bias is applied and both
the consecutive stress cycle. Fig. 8 shows that the SILC deshift due to charge accumulation decreases
creases as the
shift can be reduring detrapping cycle at 2.6 V. However,
covered more quickly than SILC during detrapping cycle. This
result can be explained if a part of SILC is due to the tunneling
current enhanced by the accumulated charges in HfSiO layer
while there are other portions of SILC affected by unidentified
degradation mechanism, which is still reversible to some degree.
These results show that even SILC is partially reversible and the
physical mechanism of SILC is more complicated than SiO
cases.
In summary, the interpretations of dc reliability test on highdevice are not straightforward and sometimes misleading if the
reversibility is not considered. For example, constant voltage
TDDB yields worse lifetime than pulsed TDDB due to the
charge accumulation in the dielectric during the stress [24].
Thus, constant voltage TDDB is no longer a good representative of the reliability of high- devices and more thorough
investigation is necessary to identify proper reliability test
methods for high- devices.
V. CONCLUSION
The primary purpose of reliability tests on MOS devices is to
find long-term implications of normal device operation by im-
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IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 5, NO. 1, MARCH 2005
posing test conditions that accelerate a specific reliability degradation process. These reliability tests should be designed to intensify the specific degradation process. For example, the test
to
condition for hot carrier stress has been set as
maximize the impact ionization induced gate current. The test
condition for BTI on SiO device is designed to enhance the dissociation of the hydrogen bond at the silicon interface. If more
than one degradation mechanism is mixed, the value of the test
method itself diminishes. Also, reliability tests assume that the
degradation can be accumulated. If the device degradation due
to the reliability test is reversible, the results of the reliability
test should be interpreted considering the relaxation effects.
In this paper, we have shown that constant-voltage-based
reliability tests are affected by the reversibility of charge
trapping in high- dielectrics, more specifically Hf-silicate,
especially under the substrate injection condition. Both TDDB
and HCI showed a mixed degradation mechanism. Gate injection case adds more complexity because of enhanced hole
trapping, which is less reversible than the substrate injection
case. Even though the BTI test has not been discussed in this
paper, BTI results are also affected by the reversibility and
the mixed degradation, as it is a derivative of constant voltage
stress. The TDDB, HCI, and NBTI tests were developed to
identify the defect mechanism of SiO devices. However, the
physical mechanism of high- dielectric degradation may be
significantly different from that of SiO gate dielectric. Thus, a
simple extension of the reliability test developed for SiO device will not be adequate for high- devices. In order to define
a test condition that can segregate the specific degradation of
high- device, it is important to first identify the permanent
degradation mechanism that is unique to high- devices.
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Byoung Hun Lee received the B.S. and M.S. degrees
in physics from the Korea Advanced Institute of Science and Technology, Daejeon, Korea, in 1989 and
1992, respectively, and the Ph.D. degree in electrical
and computer engineering from the University of
Texas at Austin in 2000.
He worked at Samsung Semiconductor from 1992
to 1997, and has been with IBM since 2001. He has
authored and co-authored more than 140 journal and
conference papers in the various semiconductor research areas including gate oxide reliability, SOI device and process, strained silicon devices, and high- and metal gate process
and devices. He is currently on the assignment to SEMATECH as a Manager of
the advanced gate stack program, managing the clean project, high- dielectric
project, metal electrode project, dual metal gate CMOS integration project and
electrical characterization project.
LEE et al.: VALIDITY OF CONSTANT VOLTAGE STRESS BASED RELIABILITY ASSESSMENT OF HIGH- DEVICES
Rino Choi received the B.S. and M.S. degrees from
the Department of Inorganic Materials Engineering,
Seoul National University, Seoul, Korea, in 1992 and
1994, respectively, and the Ph.D. degree in from the
Materials Science and Engineering Program at the
University of Texas at Austin in 2002.
He worked for Daewoo Motors Company from
1994 to 1999, where he was a development and test
Engineer. Since 1999, he has studied various high-
dielectrics and published more than 50 journal and
conference papers. He has been continuing his
research on the electrical characterization and reliability of advanced gate
stacks at SEMATECH since 2002.
Jang Hoan (Johnny) Sim received the B.S. degree
in 2001 and M.S. degree in 2003 from the University of Texas and Austin in 2001 and 2003, respectively, and is pursuing the Ph.D. degree in electrical
and computer engineering at the University of Texas
at Austin.
He has been working at SEMATECH as an Intern.
His research work is on the device characterization of
HfSiON dielectric and fully silicided NiSi metal gate
and he is currently working on electrical characterization and reliability of high- and metal gate stack.
Siddarth A. Krishnan (S’05) received the B.Tech.
degree in materials science and engineering from
The Indian Institute of Technology, Chennai, India,
in 1999, and the M.S degree in materials science and
engineering from The University of Texas at Austin,
where he is currently pursuing the Ph.D degree in
electrical and computer engineering.
He has been working at SEMATECH as an Intern
in the gate stack program since May 2004. His research interests include high dielectrics (with particular emphasis on reliability), metal gate electrodes
for MOSFETs and device engineering for future technologies. He has authored
or co-authored over 25 journal and conference papers.
25
Jeff J. Peterson (SM’02) received B.S. degrees in
electrical engineering and computer engineering and
the M.S. degree in electrical engineering from the
University of Missouri, Columbia, in 1986 and 1988,
respectively. He received the Ph.D. degree in electrical engineering from the University of California,
Davis, in 2002.
Since 1989, he has worked for Intel Corporation in
flash design and new technology quality/reliability,
communications foundry process reliability and
strategic quality/reliability, and external research.
Currently, he is an Intel assignee to SEMATECH in the Advanced Gate Stack
group. His interests are in solid state materials and devices, oxide and high-
dielectric charge trapping and wearout mechanisms, column IV epitaxy and
characterization, high- gate stacks, emerging materials and devices, process
integration, and process reliability. He has authored or co-authored over 60
publications and presentations including the 1992 IRPS Best Paper Award. He
has been granted 10 patents with two patents pending.
Dr. Peterson is a member of Tau Beta Pi Engineering Honor Society, and a
member of the Electrochemical Society (ECS).
George A. Brown (SM’58) received the B.S.E.E. degree from the University of Pennsylvania, University
Park, in 1959 and the M.S.E. degree from Princeton
University, Princeton, NJ, in 1961.
He is a Fellow, Technical Staff at SEMATECH,
assigned to the Front End Processes division. At
SEMATECH, he is involved in the electrical and
reliability characterization of high- gate stack
and gate electrode materials. Prior to joining SEMATECH, he retired from Texas Instruments, Inc.,
as a Distinguished Member, Technical Staff with 37
years of service. Early in his career he was with RCA Laboratories, Princeton,
NJ, where he was involved in the development of the MOS transistor device.
He is a Life Senior Member of the IEEE and a member of the Electrochemical
Society.
Gennadi Bersuker received the M.S. and Ph.D. degrees in physics at the Leningrad State University and
Kishinev State University, respectively.
After graduation, he joined the Moldavian
Academy of Sciences, and then worked at Leiden
University, The Netherlands, and the University of
Texas at Austin. Since 1994, he has been working at
SEMATECH on process induced charging damage,
electrical characterization of Cu/low K interconnect,
high- gate dielectrics and advanced CMOS process
development.