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Chapter 6 (I) Designing Combinational Logic Circuits •Static CMOS •Pass Transistor Logic V1.0 4/25/03 V2.0 5/4/03 V3.0 5/15/03 EE141 1 Combinational Circuits Revision Chronicle 5/2: Add some NAND8 figures (to compare NAND8 circuits) from old Weste textbook to this slide. 5/4: Add 4 Pass-Transistor Logic Slides from Weste textbook Split Chapter 6 into two parts: Part I focuses on Static and Pass Transistor Logic. Part II focuses on Dynamic Logic 5/15: Add the Transmission Gate slides (x5) from Kang’s textbook 2 EE141 Combinational Circuits Combinational vs. Sequential Logic In Combinational Logic Circuit In Out Out Combinational Logic Circuit State Combinational Output = f(In) Sequential Output = f(In, Previous In) 3 EE141 Combinational Circuits Static CMOS Circuits •At every point in time (except during the switching transients) each gate output is connected to either VDD or Vss via a low-resistive path (PUN, PDN) •The outputs of the gates assume at all times the value of the Boolean function, implemented by the circuit (ignoring the transient effects during switching periods). •This is in contrast to the dynamic CMOS circuit class, which relies on temporary storage of signal values on the capacitance of high impedance circuit nodes. 4 EE141 Combinational Circuits Static Complementary CMOS VDD In1 In2 PUN InN In1 In2 InN PMOS only (good for transfer 1) F(In1,In2,…InN) PDN NMOS only (good for transfer 0) Pull-up Network (PUN) and Pull-down Network (PDN) are Dual Logic Networks 5 EE141 Combinational Circuits Threshold Drops in NMOS and PMOS -- Check Candidates for PUN and PDN VDD PUN VDD S D G VDD D 0 VDD G VGS S CL VDD 0 PDN D VDD G S 0 VDD - VTn CL VDD |VTp| VGS S CL G CL D 6 EE141 Combinational Circuits Complementary CMOS Logic Style 7 EE141 Combinational Circuits NMOS Transistors in Series/Parallel Connection Transistors can be thought as a switch controlled by its gate signal NMOS switch closes when switch control input is high A B X Y Y = X if A and B A X B Y Y = X if A OR B NMOS Transistors pass a “strong” 0 but a “weak” 1 8 EE141 Combinational Circuits PMOS Transistors in Series/Parallel Connection PMOS switch closes when switch control input is low A B X Y Y = X if A AND B = A + B A X B Y Y = X if A OR B = AB PMOS Transistors pass a “strong” 1 but a “weak” 0 9 EE141 Combinational Circuits Example 1: NAND2 Gate (Use DeMorgan’s Law) 10 EE141 Combinational Circuits Example2: NOR2 Gate VDD PDN : G A B Connect to GND PUN : F A B A B Connnet to VDD G ( In1, In 2, In3,) F ( In1, In 2, In3,) 11 EE141 Combinational Circuits Design of Complex CMOS Gate VDD B A C D F D A (B C) A D B C 12 EE141 Combinational Circuits Constructing a Complex Gate VDD VDD C F SN4 F SN1 A D SN3 D B C B SN2 A SN2 A B SN1 D C F (a) pull-down network (b) Deriving the pull-up network hierarchically by identifying sub-nets A D B C SN2 SN1 (c) complete gate 13 EE141 Combinational Circuits Static CMOS Properties Full rail-to-rail swing: High noise margins Logic levels not dependent upon the relative device sizes: Ratioless Always a path to Vdd or GND in steady state: Low output impedance Extremely high input resistance; nearly zero steadystate input current (input to CMOS gate) No steady-state direct path between power and ground: No static power dissipation Propagation delay function of output load capacitance and resistance of transistors 14 EE141 Combinational Circuits Switch Delay Model Req A A Rp A Rp Rp B Rn Rp CL Cint A Rn A Cint A NAND2 Rp A B Rn B INV CL Rn Rn A B CL NOR2 15 EE141 Combinational Circuits Input Pattern Effects on Delay Rp A Rp B Rn CL B Rn A Cint Delay is dependent on the pattern of input (Assume Rp = 2 Rn for same size of transistors) Low-to-high transition: Both inputs go low – Delay is 0.69 (Rp/2) CL One input goes low – Delay is 0.69 (Rp) CL High-to-low transition: Both inputs go high (required for NAND) – Delay is 0.69 (2Rn)CL 16 EE141 Combinational Circuits Transistor Sizing Assumes Rp = 2Rn at same W/L Rp 2 A Rp B Rn 2 A 2 Rn B Rp 4 B 2 CL Rp 4 Cint A Cint 1 Rn Rn A B CL 1 NAND is preferred than NOR implementation!! EE141 17 Combinational Circuits Delay Dependence on Input Patterns NAND2 is true OUT connects to GND 3 Input Data Pattern Delay (psec) A=B=01 69 A=1, B=01 62 A= 01, B=1 50 0.5 A=B=10 35 0 A=1, B=10 76 A= 10, B=1 57 A=B=10 2.5 Voltage [V] 2 A=10, B=1 1.5 1 -0.5 A=1, B=10 0 100 200 300 time [ps] A=1, B=10 (for both Cint and CL) A=1, B=01 (Consider Body effect) EE141 400 NMOS = 0.5m/0.25 m PMOS = 0.75m/0.25 m CL = 100 fF 18 Combinational Circuits Transistor Sizing a Complex CMOS Gate A B 8 C 8 4 D 4 OUT = D + A • (B + C) A D 2 RN / 2 1 B 2C 2 RN / 2 (wide, only one for critical case) 19 EE141 Combinational Circuits Fan-In Considerations 4-input NAND Gate 20 EE141 Combinational Circuits Fan-In Considerations A B C Distributed RC model (Elmore delay) D R4 A R3 B C3 + (R1+R2+R3)C3 R2 C C2 + (R1+R2+R3+R4)CL R1 D C1 =0.69 Reqn(C1+2C2+3C3+4CL) CL tpHL = 0.69(R1C1+(R1+R2)C2 Propagation (H L) delay deteriorates rapidly as a function of fan-in no. : Quadratically in the worst case. 21 EE141 Combinational Circuits tp as a Function of Fan-In 1250 Quadratic (H->L) 1000 tp (psec) 750 tpH 500 tp L 250 tpL H 0 2 4 6 8 fan-in 10 12 14 16 (L H) Linear Increase in Intrinsic Capacitance, Assume Only one PMOS is On for critical case 22 EE141 Combinational Circuits (tpHL, tpLH) as a Function of Fan-Out Gates with a fan-in greater than or equal to 4 becomes excessively slow and should be avoided! 23 EE141 Combinational Circuits tp as a Function of Fan-In and Fan-Out Fan-in: quadratic due to increasing resistance and capacitance Fan-out: each additional fan-out gate adds two gate capacitances to CL To the preceding stage) 24 EE141 Combinational Circuits Fast Complex Gates: Design Technique 1 Transistor sizing Increase Intrinsic parasitic cap and create CL of the preceding stage Progressive sizing InN CL MN Distributed RC line: In3 M3 C3 •M1 > M2 > M3 > … > MN (the FET closest to the output is the smallest) In2 M2 C2 •Not simple in Layout! In1 M1 C1 25 EE141 Combinational Circuits Fast Complex Gates: Design Technique 1 26 EE141 Combinational Circuits Fast Complex Gates: Design Technique 2 Input reordering: Put late arrival signal near the output node. critical path In3 1 M3 charged CL In2 1 M2 C2 charged In1 M1 01 C1 charged Delay determined by time to discharge CL, C1 and C2 critical path 01 In1 M3 CLcharged In2 1 M2 C2 discharged In3 1 M1 C1 discharged Delay determined by time to discharge CL 27 EE141 Combinational Circuits Fast Complex Gates: Design Technique 3 Logic Restructuring (A) F =NAND8 Gate (C) In general, C > B > A in speed EE141 (B) 28 Combinational Circuits Design Technique 3: Logic Restructuring Tradeoff between Area and Speed (and Power?) (from Neil Weste, 2nd Ed, 93) EE141 29 Combinational Circuits Fast Complex Gates: Layout Technique (A): 4 internal cap 2 output diff cap (B): 4 internal cap 4 output diff cap (A) Is better than (B) (A) EE141 (B) 30 Combinational Circuits Optimizing Performance in Combinational Networks Out In 2 1 N CL N Delay pi g i f i (in units of tinv) i 1 For given N: Ci+1/Ci = Ci/Ci-1 To find N: Ci+1/Ci ~ 4 How to generalize this to any combinational logic path? E.g., How do we size the ALU datapath to achieve maximum speed? 31 EE141 Combinational Circuits Logical Effort Inverter has the smallest logical effort and intrinsic delay of all static CMOS gates Logical effort of a gate presents the ratio of its input capacitance to the inverter capacitance when sized to deliver the same current Logical effort increases with the gate complexity 32 EE141 Combinational Circuits Logical Effort Logical effort is the ratio of input capacitance of a gate to the input capacitance of an inverter with the same output current VDD A VDD A 2 2 B F 2 F A A VDD B 4 A 4 2 F 1 A B Inverter g=1 1 B 1 2 2-input NAND g = 4/3 2-input NOR g = 5/3 33 EE141 Combinational Circuits Logical Effort From Sutherland, Sproull 34 EE141 Combinational Circuits Estimated Intrinsic Delay Factor 35 EE141 Combinational Circuits Logical Effort CL Delay t p k RunitCunit 1 Cin t p 0 p g f (Assume = 1) p – intrinsic delay : gate parameter g – logical effort : gate parameter f – effective fanout Normalize everything to an inverter: ginv =1, pinv = 1 Divide everything by tinv (everything is measured in unit delays tinv) 36 EE141 Combinational Circuits Delay in a Logic Gates Gate delay: d=h+p Effort delay Intrinsic delay Effort delay: h=gf Logical Effort Effective fanout = Cout/Cin •Logical effort is a function of topology, independent of sizing •Effective fanout (electrical effort) is a function of load/gate size 37 EE141 Combinational Circuits 4/ 3; p = 2 Logical Effort of Gates = D: g tN AN = g r: e t er 1; p= 1 v in 3 pu 4 In 2- Normalized Delay 5 Effort Delay 2 1 Intrinsic Delay 1 EE141 2 3 Fanout f 4 5 38 Combinational Circuits Normalized delay (d) Logical Effort of Gates t pNAND g = 4/3 p=2 d = (4/3)f+2 t pINV g=1 p=1 d = f+1 F(Fan-in) 1 2 3 4 5 6 7 Fan-out (f) 39 EE141 Combinational Circuits Add Branching Effort Branching effort: b Con path Coff path Con path 40 EE141 Combinational Circuits Multistage Logic Networks gi fi N pi g i f i Delay pi i 1 i 1 (assume 1) N •Stage Effort: hi = gifi •Path Electrical Effort: F = Cout/Cin •Path Logical Effort: G = g1g2…gN •Branching Effort: B = b1b2…bN •Path effort (total): H = GFB •Path delay (total) D = Sdi = Spi + Shi 41 EE141 Combinational Circuits Optimum Effort per Stage When each stage bears the same effort: hN H hN H Stage efforts: g1f1 = g2f2 = … = gNfN Effective fanout of each stage: f i h g i Minimum path delay Dˆ gi f i pi N ( H 1/ N ) P 42 EE141 Combinational Circuits Optimal Number of Stages For a given load, and given input capacitance of the first gate Find optimal number of stages and optimal sizing D NH 1/ N Npinv D H 1/ N ln H 1/ N H 1/ N pinv 0 N Substitute ‘best stage effort’ hH 1/ Nˆ 43 EE141 Combinational Circuits Example: Optimize Path 1 g=1 f=a a g = 5/3 f = b/a 5 g=1 f = 5/c g = 5/3 f = c/b Effective fanout, F = 5 G = 25/9 H = GF=125/9 = 13.9 h = 1.93 (optimal stage effort) = a = 1.93 b = ha/g2 = 2.23 c = hb/g3 = 5g4/f = 2.59 EE141 c b 4 H 44 Combinational Circuits Example – 8-input AND 45 EE141 Combinational Circuits Method of Logical Effort Compute the path effort: F = GBH Find the best number of stages N ~ log4F Compute the stage effort f = F1/N Sketch the path with this number of stages Work either from either end, find sizes: Cin = Cout*g/f Reference: Sutherland, Sproull, Harris, “Logical Effort, Morgan-Kaufmann 1999. 46 EE141 Combinational Circuits Summary Sutherland, Sproull Harris 47 EE141 Combinational Circuits Pass-Transistor Logic 48 EE141 Combinational Circuits Pass-Transistor Logic Inputs B Switch Out A Out Network B B • N transistors • No static consumption 49 EE141 Combinational Circuits Pass Transistor Logic Basics Logic Function: F PiVi i P1 (V1 ) P2 (V2 ) Pn (Vn ) Pi Control Signals Vi Pass Signals 0,1, X i , X i , Z Z : High Impedance B Example: AND Gate A B A, B: A is Input signal, B is the Control Signal F = AB + 0B = AB 0 50 EE141 Combinational Circuits Example: Design of XNOR2 (a) Truth table (b) Pass-network Karnaugh map (c) Logic function A as the control signals B as the passed signals F A (B) A ( B) 51 EE141 Combinational Circuits Example: Implementation of XNOR2 (a) Transmission Gate (b)NMOS (c)Cross-couple 52 EE141 Combinational Circuits Example2: Construct Boolean Functions •Truth Table: •Implement: 53 EE141 Combinational Circuits NMOS-Only Logic 3.0 In 1.5m/0.25m VDD x 0.5m/0.25m Out 0.5m/0.25m Voltage [V] In Out 2.0 x 1.0 0.0 0 0.5 1 1.5 2 Time [ns] Suffer from •Vt degradation (Vx = Vdd- Vt(x)) •Body effect (Vsb, Vx has value and Vt(x) is bigger than Vt(0)) 54 EE141 Combinational Circuits NMOS-only Switch C = 2.5V C = 2.5 V M2 A = 2.5 V A = 2.5 V B B Mn CL M1 VB does not pull up to 2.5V, but 2.5V - VTN Threshold voltage loss causes static power consumption NMOS has higher threshold than PMOS (body effect) 55 EE141 Combinational Circuits NMOS Only Logic: Level Restoring Transistor VDD VDD Level Restorer Mr B A Mn M2 X Out M1 •Advantage: Full Swing •Restorer adds capacitance, takes away pull down current at X •Ratio problem among (Mr and Mn) 56 EE141 Combinational Circuits Restorer Sizing Voltage [V] 3.0 •Upper limit on Restorer Transistor size 2.0 W/Lr =1.75/0.25 W/L r =1.50/0.25 1.0 W/Lr =1.0/0.25 0.0 0 100 200 W/L r =1.25/0.25 300 Time [ps] 400 500 57 EE141 Combinational Circuits Solution 2: Single Transistor Pass Gate with VT=0 VDD VDD 0V 2.5V VDD 0V Out 2.5V WATCH OUT FOR LEAKAGE CURRENTS 58 EE141 Combinational Circuits Complementary/Differential Pass Transistor Logic (CPL/DPL) A A B B Pass-Transistor F Network (a) A A B B B Inverse Pass-Transistor Network B B A F B B A A B F=AB A B F=A+B F=AB AND/NAND A F=AÝ (b) A A B B F=A+B B OR/NOR A F=AÝ EXOR/NEXOR 59 EE141 Combinational Circuits Differential Cascode Voltage Switch Logic (DCVSL) (p.267) VDD M1 VDD M2 Out A A B B Out PDN1 PDN2 VSS VSS Differential Cascode Voltage Switch Logic (DCVSL) 60 EE141 Combinational Circuits DCVSL Example Out Out B B A B B A XOR-NXOR gate 61 EE141 Combinational Circuits DCVSL Transient Response V olta ge [V] 2.5 AB 1.5 0.5 -0.5 0 AB A,B 0.2 A,B 0.4 0.6 Time [ns] 0.8 1.0 62 EE141 Combinational Circuits Solution 3: Use of Transmission Gate C A C A B B C C C = 2.5 V A = 2.5 V B CL C=0V 63 EE141 Combinational Circuits Analysis of TG (Transmission Gate) G NMOS: D S S D VDS ,n VDD Vout VGS ,n VDD Vout PMOS: VDS , p Vout VDD VGS , p VDD G I D I DS ,n I SD, p Req ,n VDD Vout I DS ,n Req , p VDD Vout I SD, p Req ,TG Req ,n || Req , p 64 EE141 Combinational Circuits Analysis of TG (I) 65 EE141 Combinational Circuits Analysis of TG (II) 66 EE141 Combinational Circuits Resistance of Transmission Gate 67 EE141 Combinational Circuits Application1: Inverting 2-to-1 Multiplexer S A VDD S M2 S VDD F S M1 F B S F (S A S B) GND A S S B 68 EE141 Combinational Circuits Application2: 6-T(ransistor) XOR Gate Truth Table B B 0 0 1 1 A 0 1 0 1 F A A A A 0 1 1 0 B M2 A A F M1 B M3/M4 B B=0: Pass A Signal B=1: Inverting A Signal 6T has the inverter of B 69 EE141 Combinational Circuits Application3: Transmission Gate Full Adder (to be discussed in Chapter 11) P VDD Ci A P A A P B VDD Ci A P Ci VDD S Sum Generation Ci P B VDD A P Co Carry Generation Ci A Setup P Similar delays for Sum and Carry 70 EE141 Combinational Circuits Delay in Transmission Gate Networks 2.5 2.5 V1 In 2.5 Vi Vi-1 C 0 2.5 C 0 Vn-1 Vi+1 C 0 Vn C C 0 (a) Req Req V1 In Req Vi C Vn-1 Vi+1 C C Req Vn C C (b) m Req Req Req Req Req Req In C CC C C CC C (c) 71 EE141 Combinational Circuits Delay Optimization Buffer can be (a) Inverter pairs (b) One inverter + Final correcting inverter 72 EE141 Combinational Circuits Summary Fan-in and Fan-out of gates play an important role in CMOS circuit speed. Concept of Logic Efforts can generalize the invert chain design to complex gate chain design. Pass Transistor Logic leads low-power, lowfootprint designs, but it should be used with special care. 73 EE141 Combinational Circuits