Download propdef3

yes no Was this document useful for you?
   Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Document related concepts

Crystal radio wikipedia, lookup

Flexible electronics wikipedia, lookup

Wien bridge oscillator wikipedia, lookup

Distributed element filter wikipedia, lookup

Microprocessor wikipedia, lookup

Radio transmitter design wikipedia, lookup

Rectiverter wikipedia, lookup

RLC circuit wikipedia, lookup

Electronic engineering wikipedia, lookup

Invention of the integrated circuit wikipedia, lookup

Regenerative circuit wikipedia, lookup

Thermal copper pillar bump wikipedia, lookup

MOS Technology SID wikipedia, lookup

Opto-isolator wikipedia, lookup

Valve RF amplifier wikipedia, lookup

Index of electronics articles wikipedia, lookup

Integrated circuit wikipedia, lookup

Microelectronics Integration:
Design, Analysis and
Zeynep Dilli
Ph.D. Program Dissertation Proposal
Introduction & Motivation: 3-D Integration
Current trend in electronics: Tighter integration at every integration
Device  Gate  Chip  …  Board  Main Board  System
Limitations: Speed, compactness, signal clarity, robustness…
“Smart Dust” systems
Ideally self-contained, self-powered and small
May require mixed-signal integration
3-D stacking might be the ideal answer
Stacks with cap chips…
…with intertier vias
…with sidewall
3-D Integration: Advantages &
Disadvantages (Compared with 2-D)
Net system size reduction
Increased active Si area/chip
Delay reduction: faster clocks
or higher bandwidth
Increased heat-dissipation
Increased design complexity.
Shorter interconnects
Lower parasitic & load
Potential intra-system noise
Potential substrate noise
Heterogeneous integration
More freedom in geometric
Lower power consumption.
Challenge to the Designer
3-D integration is a subject that
ties together chip design, chip
physics, device design, circuit
design, electromagnetics, and
geometrical layout problems.
Proof of concept: A 3-D integrated selfpowering system
 Circuit performance in 3-D integration
 Passive devices for self-contained 3-D
Self-Powered Electronics by
3-D Integration: Proof of Concept
3D system concept: Three tiers
Sensor (Energy harvesting: Photosensor)
Storage (Energy: Capacitor)
Electronics (Local Oscillator and Output Driver)
Process & Circuit
0.18 μm fully-depleted SOI process
3 metals
p-type substrate, ~1014
Implants: Threshold adjustment, CBN and CBP (5x1017),
source-drain, PSD and NSD (0.5x1019, 1x1019)
Process information
Silicon islands
50 nm thick
Three tiers
Top two tiers
turned upsidedown
Figure adapted from MIT_LL
3D01 Run Application Notes
Photodiodes: Design Issues
Photocurrent=Responsivity [A/W] x Incident Power
Responsivity= Quantum efficiency x λ [μm] /1.24
problem: The material depth is very small
For red light, λ [μm] /1.24 = 0.51
Incident Power = Intensity [W/μm2] x Area
Sunlight intensity ≈ 1x10-9 W/μm2
 Quantum Efficiency: η = [# electron-hole pairs]/ [# incident photons]
Depends on reflectance, how many carrier pairs make it to the outer circuit,
and absorption
 At 633 nm (red light), absorption coef. ≈3.5e-4 1/nm
 amount of photons absorbed in 50 nm depth is (1-exp(-αd)) ≈ 0.017
η = 0.017 x reflectance x ratio of non-recombined pairs ≈ 0.017 x
x 0.51 x 1x10-9 x Area[μm2]
= 6.63 pA/μm2
 Photocurrent=0.013
Photodiodes: Design Issues
x 0.51 x 1x10-9 x Area[μm2] = 6.63 pA/μm2
Photosensitive area: pn-junction depletion region width (Wd) times length
Available implants: Body threshold adjustment implants (p-type CBN and
n-type CBP, both 5x1017 cm-3); higher-doped source-drain implants and
capacitor implants; undoped material is p-type, ~1014 cm-3.
Two diode designs: CBN/CBP diode and pin diode (CBP/intrinsic junction)
 Photocurrent=0.013
CBN/CBP diode Wd=0.0684 μm; A=0.5472 μm2
Pin-diode Wd ≈ 1.5 μm; A=15 μm2; possibly problematic
To increase: Higher-intensity light; optimal wavelength (higher wavelength
increases λ/1.24, but decreases absorption)
Layout Constraints: As many diodes as possible;
diodes in regular arrays; need three bonding pads of a
certain size; assigned area 250 μm by 250 μm only
Layout: 2062 CBN/CBP diodes: 7.48 nA; 52 pin diodes: 5.17 nA
 Expect about 12 nA
Photodiodes: CBN/CBP Diode Layout
Photodiodes: pin diode layout
Layout: Tier 3, Diodes and Pads
Layout: Tier 2, Capacitor
Top plate: Poly
Bottom plate: N-type
capacitor implant, CAPN
Extracted value: 29 pF
Expected value: 30 pF
Layout: Tier 1, Local Oscillator
Circuit Operation
Cstorage is charged up to a stable level depending on iph.
Circuit Operation
Vrail=270 mV, fosc=1.39 MHz for iph=15 nA.
3-D System, Further Research, 1
Test the device once fabrication is completed:
 Self-contained
system, 250 μm x 250 μm x 700 μm
Design a version to be fabricated at LPS
 Greater
active photosensor depth
 Voltage regulator to prevent diode forward bias
current overtaking the photocurrent
Investigate rectifying antennas as alternate
power source
 Preliminary
investigation done on circuit board level
 See further work on passive structures
3-D System, Further Research, 2
Compare yield of 3-D system with planar system of the
same footprint area
Codify self-powering system design methodology
Rectifying-antenna based:
Photodiode power generation ability: Diode design and chip optical
design (microlenses/AR coatings…)
Charge storage system: Capacitor, high-k dielectric use
Power regulation circuit requirement
Antenna properties: Possible low-k dielectric use
Need for a transformer
Rectifier diode design
Tied to load circuit characteristics
Proof of concept: A 3-D integrated selfpowering system
 Circuit performance in 3-D integration
 Passive devices for self-contained 3-D
3-D Integration: Performance Study
 Intra-chip
 Generation
and dissipation
 Substrate
 External Interference
Compare performance with planar integrated
circuits and connections
Performance: Speed
Bonding pads, wires: Extra load + parasitics
Left: “External” ring oscillator, 11 stages (two
stages are shown)
Both are comprised of minimum-size transistors,
simulated speed for 31 stages: 132 MHz.
Right: Internal ring oscillator, 31 stages, output to
divide-by-64 counter
Internal Osc.
External Osc.
One-stage delay
(equivalent to 1.16
GHz for 3 stages)
(equivalent to 1.46
MHz for 3 stages)
internal, ~330 ns
for external dev.
Speed ratio: 794.5
Load ratio: ~1000
3-D Connections
Chip-to-chip communication between different chips with vertical vias that
require 12m x 12m metal pads
Cadence-extracted capacitance for a pad 9.23 fF: Same order of magnitude
as inverter load cap
3-D Connections: “Symmetric” Chip
Structures that can
be connected in
3D and planar
counterparts for
3-D Connections: “Symmetric” Chip
Same 31-stage planar ring oscillator with counter output
Also 31-stage 3-D ring oscillator with counter output
(On the figure, groups of 5-5-5-5-5-6).
The proper pairs of pads
have to be connected to
each other through vertical
through-chip vias postfabrication for the circle to
Simulation results:
Planar: 142 MHz
3-D, six “layer”s: 122 MHz (six
vertical pads as extra load)
To counter input
“symmetry” axis
Performance: Heat
Coupled simulation at device and chip level to characterize chip
heating: Generation, distribution and dissipation
Performance: Heat
  (To ) 2 T  H
Modified heat flow equation:
T 6  o T f S f
 H
t f 1 l f
Integrated over a volume to
obtain a “KCL” eqn.:
i , j ,k
i , j ,k
l 1
i , j ,k
) (T
i , j ,k
i 1, j ,k
Rith 1 , j ,k
) (T
i , j ,k
i , j 1,k
Rith, j  1 ,k
) (T
i , j ,k
i , j ,k 1
Rith, j ,k  1
 Iil, j ,k (Ti ,l j ,1k )
General Algorithm: Solve device equations for a range of temperatures; set up the
chip thermal network including heat generation; assume initial temperatures and
solve the thermal network; obtain heat generated by each transistor at that
temperature; reevaluate heat generated by each transistor, repeat until convergence
Also Possible: Use solver to suggest layout solutions for heat dissipation
Performance: Heat
Device operation characteristics depend
on temperature (e.g. I-V characteristic of
a diode)
Affects circuit operation (e.g. foscof a ring
Performance: Noise
Substrate Noise
 Modeled
as substrate currents [1] or lumpedelement networks [2]
 Characterized with test circuits [3] or Sparameter measurements [4]
[1] Samavedam et al., 2000
[2] Badaroglu et al., 2004
[3] Nagata et al., 2001, Xu et al., 2001
[4] Bai, 2001
Performance: Signal Integrity
On-chip interconnects on lossy substrate: capacitively
and inductively coupled [1]
Characterized with S-parameter measurements
Equivalent circuit models found by parameter-fitting
[1] Zheng et al, 2000, 2001; Tripathi et al, 1985, 1988…
Performance: Signal Integrity
Substrate properties and return current paths
affect interconnect characteristics
 Three
modes of operation, affecting loss and
dispersion [1]
 Mutual inductance from a return current with a
complex depth to calculate interconnect p.u.l
inductance [2]
Effect of a second substrate stacked in proximity
not investigated
Effect of vertical interconnects not investigated
[1] Hasegawa et al, 1971
[2] Weisshaar et al, 2002
Performance: Further Research, 1
Speed: 3-D integrated chip in design
 Heating: Planar heating characterization
chip in fabrication; 3-D heating
characterization chip being designed
 Noise: Design a planar chip to model and
characterize the substrate noise coupling
within; design a 3-D integrated chip to
compare noise performances
Performance: Further Research, 2
Signal Integrity: Adapting the heat-elements
network to coupled interconnect models
 Evaluate
the sensitivity of different interconnect layouts
to external pulses
Set up a coupled network
Use random current sources as external pulses to generate a
coupling map
Design interconnect chips for experimental verification
 Interconnect
equivalent circuit model/parameter
alterations for 3-D integration
Investigate capacitive and inductive coupling to a nearby
conductive, electrically disconnected substrate in addition to the
associated substrate
Derive transmission line parameters
Design chips for experimental verification
Proof of concept: A 3-D integrated selfpowering system
 Circuit performance in 3-D integration
 Passive devices for self-contained 3-D
On-Chip Inductors and Transformers
Self-contained integrated
systems may require passive
Communication with other
units in the network: on-chip
Power harvesting: Rectifying
antennas and transformers
Various analog circuits--mixers, tuned amplifiers,
VCOs, impedance matching
networks: Inductors,
transformers, self-resonant LC
On-Chip Inductors and Transformers
Planar inductor design
Number of turns
Total length
First/last segment length
Trace width
Planar inductor
Define an
equivalent circuit,
to measurements
 Separate physicsbased approaches
for serial or shunt
Trace separation
Metal layer
Substrate doping
Substrate shields
Stacked or coiled structure
De-embedding and Extraction
L( ) 
m(1/ Y11 )
m(1/ Y11 )
Q( ) 
e(1/ Y11 )
An on-chip inductor has frequency
ranges where it behaves
inductively or capacitively:
-----Ref. frame after Open is taken out-------
--------Measured reference frame for DUT_full------------
A Qualitative Look at the Inductance Curve
Different Metal Layers
M3: Lowest capacitance, highest Q factor
Planar vs. Stacked Inductors
58072 micron2 vs. 22500 micron2
Tuning an Inductor with Light
Bottom right: Shunt capacitance
increases; fsr drops ~150-200 MHz
Top right: Substrate resistance
decreases: peak impedance increases
Exploiting Self-Resonance
Certain circuits need LC tanks
 Mixers, tuned
 LC filters
LNAs (as a tuned load)
There is some interest on intentionally
integrating inductors with capacitors to obtain an
LC tank
Use the equivalent circuit model in a circuit
design to exploit this effect and investigate
optimization; verify experimentally
Passives: Further Research
3-D inductors in chip stacks
 Investigate
multiple-substrate inductor
 Electromagnetic modeling, experimental
 Low-k dielectrics
Tunable Self-Resonant Structures
 Controlled
tuning methodology
 Electrical
 Electromagnetic
 Circuit
3-D Self-contained System Design
 3-D System Performance Analysis
 Speed
 Noise
 Signal
Passive Structures for Self-Contained
 3-D
 Tunable passives
…And on another track…
Engineering education research
Helped Direct:
Maryland Governor’s Institute of Technology program, Summer 2001
Design of ENEE498D, Advanced Capstone Design
Presented paper in ITHET 2004
Departmental outreach programs
Co-authored textbook
Benjamin Dasher Best Paper Award in FIE 2002
GE program for high school teachers, MERIT students, WIE summer
Attending PHYS 708: Physics Education Research Seminar
Engineering education is an open research field as well
Considering several questions adapted from PER: Student knowledge
body characterization; concept lists for EE…