Download RANDOM NUMBER GENERATION (GAUSSIAN DISTRIBUTION

ISSN: 2277-5536 (Print); 2277-5641 (Online)
RANDOM NUMBER GENERATION (GAUSSIAN DISTRIBUTION,
UNIFORM, EXPONENTIAL AND VITAL MODEL)
AND MODELING OF DELAY USING VHDL
Soleyman Shirzadi1, Seyede Tahere Hashemi2*, Mohammad Saber Setoodeh Kia3
Page | 489
1
Department of Electrical Engineering, Technical & Vocational University, Kermanshah, Iran.
Department of Electrical Engineering, Acecr, Institute of higher Education, Kermanshah, Iran.
*
Corresponding Author: Seyede Tahere Hashemi
2,3
ABSTRACT:
Since Very High Speed Integrated Circuit Hardware Description Language (VHDL) is one of the most
practical languages in the contemporary era, and is considered a high-level language, learning programs
which facilitate the relationship between language and the software have attracted the attention of
designers. One of the programs and basic commands require for designers is random number for
modeling completely randomized time delay in accordance with reality. VHDL alone does not inherit
such capacity. In the present paper, writing command codes which generate randomized numbers require
for designer are addressed for including randomized numbers with normal distribution, randomized
numbers with exponential distribution, randomized numbers with Gaussian distribution and also VITAL
model in the input. Then, these numbers have been transformed in to times and direction of them is
investigated in basic digital blocks.
KEYWORDS:
Exponential distribution; Gaussian distribution; Random delay; Uniform distribution; VHDL.
INTRODUCTION:
With growing and integrating of digital circuits, designing and analyzing the performance of them have
been more complex. So, the need for a high-level hardware language that can perform a general and
robustly accurate algorithm is more and more sensed (Gao et al., 2010; khandelwal, 2007; Chiang and
Kawa, 2007).
One of the most important hardware design tools is VHDL which has many applications in army industry,
communication, electronic, and computer sciences.
Programming languages like C, Pascal, and FORTRAN that are utilized for computer applications are
sequential. Mean's that program line codes will run in hierarchical form. However, in real hardware,
different parts of circuit operate in parallel and synchronized form and operation of each part is
independent of others. In fact, typical programming languages with hierarchical nature, is not applicable
to describe the hardware that may built with multiple parts that their output will change at the same time.
A high-level hardware description language (HDL), considering the hardware operation, must have the
ability to operate in parallel form. Moreover, the language must have the ability to modeling and operate
with different values that are employed in real circuit. Also, all modeling and simulating procedures are
done with respect to time. This time attribute, is not the real time but time from circuit operation
perspective.
The VHDL language is one of well-known HDL applied to the design chips with special application and
FPGA chip (Zwolinski, 2004; Litovski et al., 2001). In first, it has been ordered by USA Department of
Defense and designed for documenting the information of digital circuits and chips hired in military
equipment.
DAV International Journal of Science Volume-4, Issue-4 August 2015
ISSN: 2277-5536 (Print); 2277-5641 (Online)
The term "HDL" is called to the programming language that operates to model apart of hardware. This
hardware description language includes two modeling:
 Structured modeling
 Behavior modeling
In the former, modeling is accomplished on the basis of the structure, internal- and external-connections
Page | 490 and structures, and connections between two different hardware parts; and its main target is to investigate
the structure of hardware.
In the latter, modeling is done according to the behavior of hardware. In other words, it describes abstract
characteristics of hardware behavior regardless of its internal structure and components. This means that
the outputs depend to inputs (Zwolinski, 2004).
In the former, designers encounter the problems that created during the manufacturing process, such as
wrong size of transistor parameters as we expected. These approximations and many other factors cause
delay in different internal parts of hardware which its accurate value will change in each run (Liou et al.,
2002; Erba et al., 2001).
We need to learn random delay syntax in order that hardware description in VHDL becomes consistent
with the fact. In default, VHDL is unable to generate random numbers with specified distribution. In this
paper, with the help of quasi random syntax of VHDL and spread it, quite randomized numbers with
specified and Gaussian distribution is generated.
RANDOM PULSE GENERATOR:
Uniform Function
In probability theory and statistics, the continuous uniform distribution or rectangular distribution is a
family of symmetric probability distributions.
The probability that a uniformly distributed random variable falls within any interval of fixed length is
independent of the location of the interval itself but it is dependent on the interval size, as long as the
interval is contained in the distribution's support.
The support is defined by the two parameters, a and b, which are its minimum and maximum values.
The probability density function of the continuous uniform distribution is given in Equation 1.
 1
ba

f ( x)  
 0

for a  x  b
for x  a or x  b
(1)
In terms of mean μ and variance σ2, the probability density may be written as Equation 2.
 1
 2 3

f ( x)  
 0


for   3  x     3
(2)
otherwise
Restricting a=0 and b=1, the resulting distribution U(0,1) is called a standard uniform distribution.
VHDL package along with many math functions also includes a pseudo-random number generator. A
pseudo-random number generator uses the techniques following a repeatedly and predictable process and
doesn't consider all conditions for being an absolute random function. This pseudo-random generator will
always produce the same chain.
It is very common to use an integer like present time to randomize the seed. VHDL doesn’t have such
ability. Proposed VHDL overcomes the problem with storing seed among different runs.
DAV International Journal of Science Volume-4, Issue-4 August 2015
ISSN: 2277-5536 (Print); 2277-5641 (Online)
A shared variable (the variable that is visible to all functions in the package) called ʺsseedʺ initializes with
calling the 'seed' function, where the seed is read from a file, after the change, it written to the same file.
So that every time a simulation runs, the seed will be different. It runs only once per simulation. A
pseudo-random number generator uses ʺsseedʺ to generate number between 0 and 1. The ʺrndʺ function
has randomly generated the number ʺrʺ with uniform distribution between 0 and 1, same standard uniform
Page | 491 distribution (Zwolinski, 2004).
The proposed generator code is shown in Figure 1.
package sseed is
impure function rnd return real;
end package sseed;
package random is
alias sseed is WORK.sseed;
impure function …….(t : TIME) return TIME;
end package random;
…
impure function rnd return REAL is
.......
Begin
r := mult*REAL(vseed);
quotient := r/divid;
vseed := NATURAL(floor(r - (floor(quotient)*divid)));
return (REAL(vseed)/divid);
end function rnd;
Fig. 1. Generating uniform distribution function in VHDL code.
Negexp (Negative Exponential) Functions
An exponential function is a function of the form Equation 3.
f ( x)  b x
(3)
The input variable x occurs as an exponent – hence the name.
Where the base b is not specified, the term exponential function is almost always understood to mean
the natural exponential function. The function is often written as exp(x), where e is a number
approximately 2.718281828, is called Euler's number.
In general, the variable x can be any real or complex number or even an entirely different kind
of mathematical object.
The exponential function ex can be defined by the power series that given in Equation 4.
e x  n0

xn
x 2 x3 x 4
 1 x 
 
 ...
n!
2! 3! 4!
(4)
Using an alternate definition for the exponential function leads to the same result when expanded as
a Taylor series.
If every (x) replaced with (–x), it would be a reflection about the y-axis. We also know that when we raise
a base to a negative power, the one result is that the reciprocal of the number is taken and the only
differences regard whether the function is increasing or decreasing, and the behavior at the left hand and
right hand ends. This is called negative exponential function.
DAV International Journal of Science Volume-4, Issue-4 August 2015
ISSN: 2277-5536 (Print); 2277-5641 (Online)
In this work, a negative exponential function (negexp) to select random numbers and convert it to time is
applied. The average time to next event will be determined, but rather uniform distribution, half of the
time events will be between zero and average time, and half will be between average time and extreme.
The diagram of this distribution is shown in Figure 2.
Page | 492
Fig. 2. Negative exponential diagram.
In this method, ʺnegexpʺ function gets a time as average value and converts it to an integer, then produce
a randomized integer about this average value then return this to the next event as an integral number of
nanoseconds.
Figure 3 shows this converting process.
.....
library IEEE;
use IEEE.math_real.all;
package body random is
impure function negexp(t : TIME) return TIME is
Begin
return INTEGER(-log(sseed.rnd)*(REAL(t / NS))) * NS;
end function negexp;
end package body random;
Fig. 3. Exponential function in VHDL code.
Gauss-rng (Standard Normal Distribution) Functions
In probability theory, the normal or Gaussian distribution is a very common continuous probability
distribution. Normal distributions are important in statistics and are often used in the natural and social
sciences to represent real-valued random variables whose distributions are not known.
DAV International Journal of Science Volume-4, Issue-4 August 2015
ISSN: 2277-5536 (Print); 2277-5641 (Online)
The normal distribution is remarkably useful because of the central limit theorem. In its most general
form, under some conditions (which include finite variance), it states that averages of random
variables independently drawn from independent distributions converge in distribution to the normal, that
is, become normally distributed when the number of random variables is sufficiently large. Physical
quantities that are expected to be the sum of many independent processes (such as measurement errors)
Page | 493 often have distributions that are nearly normal.
The probability density of the normal distribution is given in Equation 5.

1
f (x , ) 
e
 2
( x )2
2 2
(5)
Here, µ is the mean or expectation of the distribution (and also its median and mode). The parameter σ is
its standard deviation with its variance then σ2. A random variable with a Gaussian distribution is said to
be normally distributed and is called a normal deviate.
The simplest case of a normal distribution is known as the standard normal distribution. This is a special
case where μ=0 and σ=1 and it is described by probability density function as depicted in Equation 6.
 ( x) 
e
1
 x2
2
(6)
2
For generating the random delay, we use the Gaussian distribution function, which is more reasonable
(Bhardwaj et al., 2006; Savic et al., 2005). We know that Standard Gaussian distribution has a range from
negative extreme to positive extreme. To limit these numbers, with acceptable approximation, we
consider larger number of 'm' as 'm' and smaller number of '–m' as '–m'.
As shown in Figure 4, ʺGauss_rngʺ collects an average 'm', then with limiting the produced numbers from
'–m' to 'm' and shifting the gauss function about '0' with the amount of 'm', give's an interval of produced
numbers from '0' to '2m' with maximum density about 'm'. This function delivers the desired number in
this interval to the event as time.
Fig. 4. Gaussian function diagram.
In Figure 5, is shown generates a random number by ʺgauss_rngʺ function.
…
library IEEE;
use IEEE.math_real.all;
package body random2 is
impure
function
gauss_rng(m:real)
returnof
realScience
is
DAV
International
Journal
variable v1, v2, r, q, p : real;
begin
loop v1:= (real(sseed.rnd))*2.0-1.0;
v2:= (real(sseed.rnd))*2.0-1.0;
r:= v1*v1+v2*v2;
exit when r < 1.0;
end loop;
Volume-4, Issue-4 August 2015
ISSN: 2277-5536 (Print); 2277-5641 (Online)
Page | 494
Fig. 5. Standard Gaussian function in VHDL code.
Gauss_rngt(μ; σ) Function ( General Normal Distribution)
Every normal distribution is a version of the standard normal distribution whose domain has been
stretched by a factor σ (the standard deviation) and then translated by μ (the mean value) as depicted in
Equation 7.
f (x , ) 
1

(
x

)
(7)
The probability density must be scaled by 1/σ so that the integral is still 1.
If Z is a standard normal deviate, then X = Zσ + μ will have a normal distribution with expected
value μ and standard deviation σ. Conversely, if X is a general normal deviate, then Z = (X − μ)/σ will
have a standard normal distribution.
Using the following commands, uniform random function converts to random function with Gaussian
distribution with mean (μ) and standard deviation (σ), and then the resulting number is converted to time.
Thus, we will have a completely random number with Gaussian distribution based on picoseconds, so we
will have a different selected number that differs from previous one by calling the ʺgauss_rngt(μ; σ)ʺ
syntax. Necessary syntaxes shown in Figure 6.
…..
q:= log2(r);
z:= (sqrt((0.0-2.0)*q/r))*v1;
p:= s*z+u;
…..
impure function gauss_rngt(t1:time; t2:time) return TIME is
begin
return integer(gauss_rng((real(t1/ps)),(real(t2/ps)))*1.0) * PS;
end function gauss_rngt;
Fig. 6. Gaussian function in VHDL code with means (μ) and standard deviation (σ).
DAV International Journal of Science Volume-4, Issue-4 August 2015
ISSN: 2277-5536 (Print); 2277-5641 (Online)
SIMULATION RESULTS:
So, for each distribution functions mentioned above, testbench VHDL code written, about 5000
completely random data created of exp. Function and 15000 random data of Gaussian function are
produced and simulated by Modelsim software. Simulation results are shown in Figure 7. Generated data
stored in a text file and diagram related to each operation depicted by SPSS software. The diagrams in
Page | 495 Figure 8 (a), (b), (c) and (d) show the simulated results for ʺnegexp(100)ʺ function, ʺnegexp(200)ʺ
function, ʺnegexp(300)ʺ function and ʺnegexp(500)ʺ function, respectively. The diagrams in Figure 9 (a),
(b), (c) and (d) show the simulated results for ʺgauss_rngt(100,20)ʺ function, ʺgauss_rngt(200,20)ʺ
function, ʺgauss_rngt(200,50)ʺ function and ʺgauss_rngt(300,50)ʺ function, respectively. Also, details of
the results are expressed in Table 1 and Table 2.
Fig. 7. Simulation results, (a) gauss_rngt(200,20), (b) gauss_rngt(300,50).
Table 1. Descriptive of exponential Functions
Parameters
exp(100)
99.59
Mean
96.85
95% Confidence Interval for Mean (Lower Bound)
102.32
95% Confidence Interval for Mean (Upper Bound)
0
Minimum
902
Maximum
902
Range
exp(200)
196.52
191.02
202.03
0
2014
2014
Table 2. Descriptive of Gaussian distributions
Parameters
gauss(100,20) gauss(200,20)
100.39
199.94
Mean(μ)
100.02
199.56
95% Confidence Interval for Mean (Lower Bound)
100.77
200.32
95% Confidence Interval for Mean (Upper Bound)
23.545
23.662
Std. Deviation (σ)
exp(300)
298.54
290.00
307.07
0
3187
3187
exp(500)
505.30
491.47
519.13
0
4354
4354
gauss(200,50)
198.88
197.94
199.83
59.037
gauss(300,50)
299.99
299.04
300.94
59.488
DAV International Journal of Science Volume-4, Issue-4 August 2015
ISSN: 2277-5536 (Print); 2277-5641 (Online)
Minimum
Maximum
Range
0
160
160
0
260
260
0
350
350
0
450
450
Page | 496
Fig. 8. Exponential function results,
(a) negexp(100), (b) negexp(200), (c) negexp(300), (d) negexp(500).
DAV International Journal of Science Volume-4, Issue-4 August 2015
ISSN: 2277-5536 (Print); 2277-5641 (Online)
Page | 497
Fig. 9. Gaussian function results,
(a) gauss_rngt(100,20), (b) gauss_rngt(200,20), (c) gauss_rngt(200,50), (d) gauss_rngt(300,50).
So far, the program for generating random numbers and converting to time or in other words producing
random delay presented. Then, this random delay applies in other applicable programs such as a Full
Adder. In next sections, we use both random generation with ʺnegexpʺ and ʺgauss_rndʺ functions to
create a more real single-bit Full Adder.
SINGLE-BIT FULL ADDER WITH RANDOM DELAY (D):
Each of the random number generating functions ("gauss_rnd" and "negexp") may be employed for
simulating of the random delay in digital blocks. In this section, the way of utilizing these functions is
explained in digital blocks. For instance, describing an a-bit full adder along with the random delay block
DAV International Journal of Science Volume-4, Issue-4 August 2015
ISSN: 2277-5536 (Print); 2277-5641 (Online)
(D) in each output is accomplished (Sokolovi´c et al., 2009; Pedroni, 2010). The block diagram of the full
adder together with the random delay block is portrayed in figure 10 (a). In figure 10 (b) and (c), the sum
and carry circuit of the a-bit full adder along with D blocks are illustrated. As well, VHDL code of the abit full adder using "negexp" and "gauss_rnd" function are expressed in figure 11 (a) and (b),
respectively.
Page | 498
Fig. 10. (a) Single-bit Full Adder block with Random Delay,
(b) Carry block diagram with Random Delay, (c) Sum block diagram with Random Delay.
architecture exp of FullAdderD is
signal d, e, f, g, h :std_ulogic;
begin
d <= a xor b after negexp(3 ns);
sum <= e xor cin after negexp(3 ns);
e <= (a and b) after negexp(3 ns);
f <= (a and Cin) after negexp(3 ns);
g <= (b and Cin) after negexp(3 ns);
h <= (e or f) after negexp(3 ns);
carry <= (h or g) after negexp(3 ns);
end architecture exp;
(a)
architecture gauss of FullAdderD is
signal d, e, f, g, h :std_ulogic;
begin
d <= a xor b after gauss_rngt(3 ns);
sum <= e xor cin after gauss_rngt(3 ns);
e <= (a and b) after gauss_rngt(3 ns);
f <= (a and Cin) after gauss_rngt(3 ns);
g <= (b and Cin) after gauss_rngt(3 ns);
h <= (e or f) after gauss_rngt(3 ns);
carry<= (h or g) after gauss_rngt(3 ns);
end architecture gauss;
(b)
Fig. 11. (a) FullAdder VHDL code with Exponential function (negexp),
(b) FullAdder VHDL code with Gaussian function (gauss_rnd).
VITAL FUNCTION:
In a real circuit, it is known that passing from 0 to 1 or from 1 to 0 are not immediate in inputs and
possess some delay. VHDL models assume that these passes are immediate. However, in reality, these
passes are limited. So, if one of the inputs of a gate is ascending and other dissenting simultaneously, we
expect that output goes to a state that neither logical 0 nor logical 1. Standard VHDL logic package
doesn’t have such state. 'X' generally represents a condition that can be either a one or a zero (Zwolinski,
2004; Dietrich et al., 2010).
In order to show the results must be considered with caution, we model the full adder in another way.
VITAL (VHDL first step toward ASIC libraries No4/1076 at 1994) allows to time simulations in gate
level with considering such passes. It does this by providing a pair of the VHDL modeling package.
Figure 12 displays a block diagram function with random delay in output and vital delay in input.
DAV International Journal of Science Volume-4, Issue-4 August 2015
ISSN: 2277-5536 (Print); 2277-5641 (Online)
Page | 499
Fig. 12. Function block diagram with Random delay and vital delay.
For example, a vital model for an inverter is ʺvitalINV(a, b, (delay, delay));ʺ. ʺVital…ʺ function is defined
in vital_primitives package.
Pair parameters (delay, delay), are a delay from 0 to 1 and a delay from 1 to 0 for each input receptively.
Usually, these two parameters have different values. Inside VITAL models, ascending and descending
passes are considered and appropriate outputs are produced.
FULL ADDER FUNCTION MODELING WITH VITAL:
For more explanation, vital function is applied at inputs of the a-bit full adder and VHDL code is written.
The diagram block of the sum and carry with a random delay (D) and vital delay in all inputs are depicted
in figure 13. Then, according to the figure 13, the VHDL code of the sum output is exhibited by the vital
and negexp function. Figure 14 shows this code.
Fig. 13. (a) Carry block diagram with random delay and vital delay,
(b) Sum block diagram with random delay and vital delay.
architecture vt1 of fulladderd is
signal e, f, g, h, o, w, x, y, z : std_ulogic;
signal l, m, n : std_ulogic;
begin
vitalXOR2(l, a, b, (negexp(2 ns), negexp(2 ns)), (negexp(2 ns), negexp(2 ns)));
m <= l after negexp(3 ns);
vitalXOR2(n, m, cin, (negexp(2 ns), negexp(2 ns)), (negexp(2 ns), negexp(2 ns)));
sum <= n after negexp(3 ns);
….
DAV International Journal of Science Volume-4, Issue-4 August 2015
ISSN: 2277-5536 (Print); 2277-5641 (Online)
Fig. 14. Part of Full Adder VHDL code with Exponential function and vital function.
CONCLUSIONS:
In modern designs, with more complexity of integrated circuits, the need for a high-level hardware
Page | 500 description language like VHDL is extremely sensed. Although comprehensive at different levels of
designing, VHDL has its own deficiencies. For example, syntaxes of the VHDL are not enough for
generating completely random numbers required for simulating of real gate delay models. In this paper,
random numbers with uniform, exponential and Gaussian distribution using VHDL Pseudo-random
generator have been engineered. Designers will able to complete their VHDL package manipulating these
syntaxes and achieve close to more real designs.
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DAV International Journal of Science Volume-4, Issue-4 August 2015