Download Power-on Sequence Testing

Ruggedized Camera Encoder
July 28, 2017
P14571
Hornyak, Jason, Moreno, O’Connor, Streat
CoaXPress HSMC Subsystem Test Plan Rev.A
Author: Lennard Streat, Computer Engineering, RIT
Multi-Disciplinary Senior Design I
RIT Ruggedized Camera Encoder (P14571)
1|Page
[email protected]
Ruggedized Camera Encoder
July 28, 2017
P14571
Hornyak, Jason, Moreno, O’Connor, Streat
Table of Contents
1. Module 1: MSD I - Software Proof-of-Concept Test Plan
 Software Sub-systems
 Test Equipment
 Customer Requirements Supported
 Proof-of-Concept Timeline
2. Module 2: MSD II – Preliminary Hardware Testing
 Overview
 Test Point Probing
 Power-on Sequence Testing
 Data Collection
 Risk Factors
3. Module 3: MSD II –Hardware-Software Integration Testing
 Design Verification
2|Page
[email protected]
Ruggedized Camera Encoder
July 28, 2017
P14571
Hornyak, Jason, Moreno, O’Connor, Streat
I.
Software Proof-of-Concept
Software Sub-systems
This phase of testing will be executed during the summer break. The goal of this test
phase is to act as a proof-of-concept phase, which will segue into the final verification
testing phase. Within this phase, the hardware description language (HDL) code that will
enable the host FPGA to communicate with the CoaXPress HSMC board will be designed inpart and tested. The deliverable from this phase is a fully test-benched design for all subsystems. It must be noted that this phase is simply a software phase. The major subsystems that will be designed and tested are as follows:
1. 8B/10B Encoding/Decoding IP Core
2. PoCXP Controller
a. Shutdown detection
b. Power-on sequence (device detection) control
c. ADC value interpreter
d. I2C Interface
The following table serves as a test-case checklist for this phase:
Test Case #
SPOC 1.1
SPOC 1.2
SPOC 1.3
SPOC 1.4
SPOC 1.5
3|Page
Test Case
Data is properly encoded.
This test requires that a
known image be encoded
and verified against the
expected output. Verify
that the output is
balanced—proper number
of logic-level transitions.
Data is properly decoded.
This test is dependent
upon test SPOC 1.1 to be
completed first.
The 8B/10B core properly
encodes clocked input.
This test is dependent
upon test SPOC 1.1.
The 8B/10B core properly
decodes clocked input.
This test is dependent
upon SPOC 1.3.
Data buffering and
multiplexing.
Expected Results
Output is balanced,
proper 8B/10B data.
[link]
Output matches
input to SPOC 1.1.
[link]
See SPOC 1.1. All
output is placed in
an output buffer.
See SPOC 1.2. All
data is read from an
input buffer.
Data RX/TX from/to
multiple sources.
[email protected]
Reviewer/Notes
Ruggedized Camera Encoder
July 28, 2017
P14571
Hornyak, Jason, Moreno, O’Connor, Streat
Note: SPOC means “Software Proof-of-Concept.” Also, SPOC 1.5 is geared toward making the
CXP-HSMC sub-system extensible. This will enable the system to be capable of interfacing with
multiple cameras.
Test Case #
Test Case
Expected Results
SPOC 2.1
The PoCXP controller
properly detects the
shutdown condition. Note:
For device safety, this
should be tested within the
physical limits of the
hardware, instead of
outside of the
aforementioned limits.
Device shuts down
at predefined
voltage input value.
SPOC 2.2
The PoCXP controller
properly detects the
connection of a device.
SPOC 2.3
I2C interfacing. To test this
IP, a development board
may be connected to
another I2C enabled device.
SPOC 2.4
ADC interpretation. This
test may be verified by
displaying the output to an
LCD display or several (3-5)
seven segment decoders.
Reviewer/Notes
Device detects
connection of CXP-6
compliant load. Sets
the PoCXP control
signal high.
Properly transmits
data serially in an
I2C compliant
manner. Receives
data as well.
Interprets the ADC
values as accurate
voltage levels.
Test Equipment
To test the software (HDL) interface that will exist between the CXP HSMC and the
host processor, several pieces of physical equipment will be utilized:
1. DE1-SoC Development and Education Board
a. Provides the visual display
2. MPR121 Capacitive Touch Sensor (I2C Enabled Sensor)
3. LCD Display (Serial Enabled)
4. Valid camera configuration commands (These must be acquired from the customer)
4|Page
[email protected]
Ruggedized Camera Encoder
July 28, 2017
P14571
Hornyak, Jason, Moreno, O’Connor, Streat
Customer Requirements Supported
This testing phase is geared toward completing the following customer
requirements (directly or indirectly):
1. CR5.1—Uses CoaXPress.
a. CR3.1—Have real-time video analytics
b. CR3.2—Have 1080p30 video stream
2. CR8.1—Interact with 4 cameras
Proof-of-Concept Timeline
This portion of the project is slated to be completed or at least primarily completed
by the beginning of the fall semester. The major risk factor is the 8B/10B encoding as this
may be challenging to properly test and integrate. Implementation may, or may not be
challenging, as this code may be provided by the customer (D3 Engineering). The I2C
interface may be challenging for similar reasons as the 8B/10B encoding.
5|Page
[email protected]
Ruggedized Camera Encoder
July 28, 2017
P14571
II.
Hornyak, Jason, Moreno, O’Connor, Streat
Preliminary Hardware Testing
Overview
The objective of this section is to present the preliminary hardware testing that will
be done at the beginning of the second phase of the project schedule—the implementation
phase. Testing in this phase will primarily center on ensuring that the PCB was properly
spun and meets the physical requirements defined in the Detailed Design document for the
CXP HSMC sub-system (see Test Point Probing section). Power-on sequencing will also be
nominally tested (described in the Power-on Sequence Testing section)—the system must,
by default, not provide power to the PoCXP interface for each coaxial connector. Also, to
bypass the need for completely working and integrated software, the control signals will be
manually switched using a test setup (described in the Data Collection section).
Test Point Probing
The test points of the CXP HSMC are listed below (the schematic may be referenced to
view the physical connectivity of the test points):
TP Ref.
Type
TP15/16
13mm test point
TP8
(Red) loop test point
TP3
(Red) loop test point
TP9
(Red) loop test point
TP10
(Red) loop test point. (See
PoCXP indicator LED also)
TP1
13mm test point
TP13
13mm test point
TP12/11
13mm test point
TP14
13mm test point
6|Page
Purpose
Tests the SDA and SCL
lines of the I2C
interface, respectively.
Tests the 3.3V input
power rail from the
HSMC connector.
Tests the 1.2V output
from the LM3671-1.2
buck converter.
Tests the 12V input
power rail from the
HSMC connector.
Tests the 24V output
from the TPS55340
boost converter.
Tests the uplink to the
first CXP output.
Tests the PoCXP switch
logic level.
Tests the current sense.
Kelvin connected.
PoCXP shutdown TP.
[email protected]
Reviewer/Notes
Ruggedized Camera Encoder
July 28, 2017
P14571
Hornyak, Jason, Moreno, O’Connor, Streat
Note: “TP Ref.” is used to refer to the “Test Point schematic reference”, or the name of the
test point on the original schematic.
Power-on Sequence Testing
The testing of the power-on sequence for the device, at the hardware level, must
ensure that, given the proper control signals are sent to the HSMC port, the device should
respond in the desired manner. Tests, corresponding with the power-on sequencing are
listed below:
Test Case #
Test Case
Expected Results
PHT 1.1
The PoCXP is checked at
its default state.
This test should be
satisfied by the
probe testing.
PHT 1.2
PHT 1.3
PHT 1.4
The PoCXP is checked after
the PoCXP control signal is
enabled for the first CXP
connection (EQCO 0). Step
must be repeated for the 3
remaining coaxial
connectors.
The PoCXP device is
disabled. This step must
follow PHT 1.2.
Full load condition.
Reviewer/Notes
Only the first CXP
port should output
power.
No CXP ports should
receive power.
The PoCXP is
enabled for all ports.
Power degradation. This
test is executed as a part of
PHT 1.4. Note: this test
All power rails
PHT 1.5
requires repeating all test
remain within the
point probing from the
expected tolerances.
prior section, Test Point
Probing.
Note: For testing this phase, a sufficiently rated resistor will be connected to the output—it
will have a value of 4.7k Ohms and rated to dissipate 13W power or greater.
Data Collection
Measurements for this portion of the test process will be recorded in alongside the
respective test point. Total system power should also be measured via a current and
voltage measurement and P = VI calculation. Using this result, final power consumption (for
7|Page
[email protected]
Ruggedized Camera Encoder
July 28, 2017
P14571
Hornyak, Jason, Moreno, O’Connor, Streat
the worst case) may be determined. From this test process a preliminary datasheet should
be compiled. The remainder of this section addresses the tools and setup necessary to test
the power-on sequencing. The following equipment and setup is needed to complete the
hardware testing phase:
1. Resistor rated to dissipate 13W power—to load the PoCXP output of each coaxial
connector; this allows for output current (and therefore, power) measurements to be
made.
2. Multichannel oscilloscope—to measure the output of the system at the PoCXP output.
3. Multimeter—to probe the test points.
4. DC power supply—to provide the ability to control the PoCXP control signals.
Risk Factors
The primary anticipated sources of risk include the improper or unsafe testing of
the CXP HSMC board. If the test setup is not properly constructed, there is the chance that
the board will be damaged. Another risk factor is the PCB manufacturing process—if the
design was manufactured improperly, the design may need to have a botch fix made or
worse, be re-spun. In addition to this is the risk of the board having faulty components.
Both of the aforementioned risks are unavoidable, but may require that each major part (in
the event of a test failure) be tested.
8|Page
[email protected]
Ruggedized Camera Encoder
July 28, 2017
P14571
Hornyak, Jason, Moreno, O’Connor, Streat
III. Hardware-Software Integration Testing
Design Verification
The CoaXPress HSMC subsystem will be considered as a fully functional design
when the software layer is properly meshed with the hardware layer. In the event that the
major risks are overcome, this will result in a properly working system. If both of the prior
test phases (see preceding sections) have been properly completed, the integration phase
should be relatively trivial. The major risks should be mitigated at this phase. One source of
risk may be the impact of timing within the software on the safe operation of the device. To
avoid possible high-cost risks, control signals should be switched such that disabling
devices takes priority over enabling devices. Another high importance risk is the impact of
failure in the CXP HSMC subsystem upon the host processor—it is recommended that some
fail-safe be coded into the host to shut down the connection from the CXP board to itself.
The downside to solving this risk is that it would require external circuitry to the FPGA in
addition to additional I/O.
Note: This test plan ensures that the CXP system will be capable of supporting the
requirements on the hardware and software levels.
9|Page
[email protected]