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EE Lecture Administrative issues Midterm exam postponed to Thurs. Nov. th o You can only bring one x paper with your own written notes please do not photocopy o No books, class or any other kind of handouts/notes, calculators, computers, PDA, cell phones.... o Midterm includes material covered to end of lecture EECS Lecture Data Converters DAC Design Page EE Lecture D/A converters D/A converters Various Architectures continued Charge scaling DACs continued RR type DACs Current based DACs Static performance of D/As Component matching Systematic amp random errors Practical aspects of currentswitched DACs Segmented currentswitched DACs DAC dynamic nonidealities DAC design considerations Data Converters DAC Design Page EECS Lecture Summary of Last Lecture Data Converters Data converter testing continued Dynamic tests continued Relationship between DNL amp SNR, INL amp SFDR Effective number of bits ENOB D/A converters Various Architectures Resistor string DACs Serial charge redistribution DACs Charge scaling DACs RR type DACs Current based DACs Data Converters DAC Design Page EECS Lecture Charge Scaling DAC Utilizing Split Array reset C C b C b /C C b C b C b C b Vref Vout Cse rie s all LSB arra y C a ll MS B a rr ay C C Split array reduce the total area of the capacitors required for high resolution DACs E.g. bit regular binary array requires unit Cs while split array amp needs unit Cs Issue Sensitive to parasitic capacitor EECS Lecture Data Converters DAC Design Page Charge Scaling DAC Advantages Low power dissipation capacitor array does not dissipate DC power Output is sample and held no need for additional S/H INL function of capacitor ratio Possible to trim or calibrate for improved INL Offset cancellation almost for free Disadvantages Process needs to include good capacitive material with standard digital process Requires large capacitor ratios Not inherently monotonic more later EECS Lecture Data Converters DAC Design not compatible Page Resistor Ladder MSB amp Binary Weighted Charge Scaling LSB Example bit DAC bit MSB DAC R string bit LSB DAC binary weighted charge scaling Component count much lower compared to full Rstring Full R string resistors Segmented R Cs unit caps EECS Lecture Segmented DAC reset C b C b C b C b C b C b C Vout .......... bit resistor ladder bit binary weighted charge redistribution DAC Switch Network Page Data Converters DAC Design Current Based DACs RR Ladder Type RR DAC basics R Simple R network divides both voltage amp current by V I R V/ I/ R I/ Increase of bits by replicating circuit EECS Lecture Data Converters.DAC Design Page .DAC Design Page RR Ladder DAC Iout VB R R R R R R R R R R VEE Emitterfollower added to convert to high output impedance current sources EECS Lecture Data Converters. DAC Design Page .Consolidate first two stages I VB Q I Q Aunit Aunit I Q Aunit IT QT Aunit I VB Q Aunit I Q Aunit IIT Aunit VEE R R R R R R VEE R R R R R EECS Lecture Data Converters.RR Ladder DAC How Does it Work Consider a simple bit RR DAC Iout VB xAunit xAunit xAunit xAunit VEE R R R R R R EECS Lecture Data Converters.DAC Design Page RR Ladder DAC How Does it Work Simple bit DAC . DAC Design Page . page EECS Lecture Data Converters. Razavi. IEEE Press.Consolidate next two stages RR Ladder DAC How Does it Work I VB Q I Aunit IIT Q Aunit Aunit I VB Q Aunit IIIT Q Aunit VEE R R R R R VEE R R R I I I I I I IT I T ot al . I To t al EECS Lecture Data Converters. Data Conversion System Design.Simple bit DAC. I T ot a l . .DAC Design Page RR Ladder DAC How Does it Work Consider a simple bit RR DAC Iout VB Aunit Aunit Aunit Aunit I VEE R I R R R I I R I R I In most cases need to convert output current to voltage Ref B. DAC Design Page .Issue error due to opamp offset EECS Lecture Data Converters.DAC Design Page RR Ladder DAC Opamp Offset Issue R out in Vos Vos R T ot al If R T ota l l a r g e. out in Vos Vos R RTotal Vos Vout If RT ota l n o t l a rg e R out in Vos Vos R T ot al P r ob l em S i nce RT ota l i s co d e d ep en d an t ou Vos t w ou l d b e co de d ep en da n t Offset Model G i ves r i s e t o I N L amp DN L EECS Lecture Data Converters.Generate virtual ground current summing node so that output impedance of current sources do not cause error .Convert current to voltage .RR Ladder DAC RTotal R Vout VB I VEE R I R R I R R R R I R I I R I R I I I Transresistance amplifier added to . DAC Design Page Current based DAC Unit Element Current Source DAC Iout Iref Iref Iref Iref Iref Unit elements or thermometer B current sources amp switches Suited for both MOS and BJT technologies Monotonicity does not depend on element matching and is guaranteed Output resistance of current source gain error Cascode type current sources higher output resistance less gain error Data Converters.DAC Design Page EECS Lecture .RR Ladder Summary Advantages Resistor ratios only x Does not require precision capacitors Disadvantages Total device emitter area Not practical for high resolution DACs AEunitx B INL/DNL error due to amplifier offset EECS Lecture Data Converters. DAC Design Page Current Source DAC Binary Weighted Iout B Iref Iref Iref Iref Binary weighted B current sources amp switches B unit current sources but less of switches Monotonicity depends on element matching not guaranteed EECS Lecture Data Converters.Current Source DAC Unit Element R Vout Iref Iref Iref Iref Output resistance of current source Use transresistance amplifier gain error problem .Error due to current source output resistance eliminated .New issues offset amp speed of the amplifier EECS Lecture Data Converters.DAC Design Page .Current source output held virtual ground . Conroy et al. . pp.DAC Design Page .Static DAC Errors INL / DNL Static DAC errors mainly due to component mismatch Systematic errors Contact resistance Edge effects in capacitor arrays Process gradients Finite current source output resistance Random variations Lithography etc Often Gaussian distribution central limit theorem Ref C. . JSSC Aug. EECS Lecture Data Converters.DAC Design Page Current Source DAC DNL/INL Due to Element Mismatch Vout Iref Iref Iref Iref I Iref I Iref Iref Simplified example bit DAC Assume only two of the current sources mismatched amp EECS Lecture Data Converters. Statistical Design Techniques for D/A Converters. x pdf fx...x pdf fx.xn Gaussian pdf EECS Lecture . Page Data Converters.DAC Design ..x pdf fxm.Current Source DAC DNL/INL Due to Element Mismatch DN L m DN L seg men t m V L S B V LSB seg men t V L S B V LSB I I R IR IR Analog Output Iref R DN L I / I LSB DN L I I R IR IR DN L I / I L S B IN Lmax I / I L S B xIref R Digital Input Page EECS Lecture Data Converters. pdf fx pdf fx pdf fx.DAC Design Component Mismatch Probability Distribution Function Component parameters Random variables Each component is the product of many fabrication steps Most fabrication steps includes random variations Overall component variations product of several random variables Assuming each of these variables have a uniform pdf distribution Joint pdf of a random variable affected by two uniformly distributed variables convolution of the two uniform pdfs. p x e x . . .g. . . PX x X e dx X e rf Integral has no analytical solution found by numerical methods EECS Lecture . X/ Data Converters.DAC Design x / Page Yield Probability density px In most cases we are interested in finding the percentage of components e.DAC Design Page .Gaussian Distribution Probability density px . . . . . R falling within certain bounds P X x X X X x . . . . . . . variance EECS Lecture where is the expected value and standard deviation E X Data Converters. . PX x X . . . . . . . yield Fraction of opamps with Vos lt V X/ . . . . EECS Lecture PX x X . . . . . . . . . . Page Data Converters. . yield EECS Lecture Data Converters. . X/ . . . . .DAC Design Example Measurements show that the offset voltage of a batch of operational amplifiers follows a Gaussian distribution with mV and .DAC Design Page . . . . . . . . . Find the fraction of opamps with Vos lt mV X/ . . . . .Yield X/ . of average for resistors .g. . . . Let us assume in this example Rs measured amp . . EECS Lecture Data Converters. R R After fabrication large of devices measured amp graphed typically if sample size large shape is Gaussian R E. . . .Component Mismatch Example Resistors layouted out sidebyside No. R R R R R dR R R R dR dR R Are a For typical technologies amp geometries . fall within OHM or .DAC Design EECS Lecture Page .DAC Design Page Component Mismatch Probability density px Example Two resistors layouted out sidebyside . of resistors . . to for resistors In the case of resistors is a function of area Data Converters. only random error B Vref Rmedi an Iref i Ri Iref D N Li i median median Ri R R medi an w h ere Rmedian Ri o B Iref i Ri I ref dR R median dR Ri median DNL dRi Ri To first order DNL of unit element DAC is independent of resolution Note Similar results for other unitelement based DACs EECS Lecture Data Converters. of all converters meet the spec EECS Lecture Data Converters.DAC Design Page DNL Unit Element DAC E.g.. Resistor string DAC D NL dR Ri i Example If dR/R .DAC Design Page . Resistor string DAC Assumption No systematic error. what DNL spec goes into the DAC datasheet so that .DNL Unit Element DAC E.g. .x. . . LSB i EECS Lecture Data Converters. what DNL spec goes into the datasheet so that .. . PX x X . . .Yield X/ . . . . .DAC Design DNL Unit Element DAC E. Page Data Converters. .g. . . of all converters meet the spec Answer From table for . . . . DNL dR/R . . . . . DNL /. . . . . . ..DAC Design Page . . . EECS Lecture PX x X . X/ . Resistor string DAC D NL dR Ri Example If dR/R . X/ . . . . .. . . . . DNL . . var i a nce n N / E d E dn Error is maximum at midscale N/ IN L B w i th N B n/N . BNnE Nn. INL depends on both DAC resolution amp element matching While DNL is to first order independent of DAC resolution and is only a function of element matching Ref Kuboki et al. n .r. n n Input LSB NB E An r n/N NAB ArAB r. E B N. r . / EECS Lecture Data Converters.DAC Design Page . A .DAC Design Page DAC INL E n n N N INL/ B.DAC INL Analysis N Output LSB AnE B E A Ideal n Nn Variance n.r./ T o f i n d ma x.r . EECS Lecture Data Converters. TCAS.n/N.B Variance of E r .. Bmax .bits . LSB Computed INL INLmax . Bmax .bits .DAC Design Page Simulation Example Bit converter DNL and INL DNL LSB .Untrimmed DAC INL Example Assume the following requirement for a DAC INL B INL INL . a number of systematic errors prevents achievement of above results EECS Lecture Data Converters.bits .DAC Design . Bmax . / . LSB midscale Why is the results not as expected per our derivation Page bin EECS Lecture Data Converters. LSB Find maximum resolution for B log Bmax . / . LSB B Random generator used in MatLab bin INL LSB .bits Note In most cases. . .Ioff Ion Digital Input DNL depends on transition Example to to DNL dref/ref DNL dref/ref Page EECS Lecture Data Converters.Ion . Iout Analog Output Iref . Ion. .Ioff . . Ion .INL amp DNL for Binary Weighted DAC Iout INL same as for unit element DAC DNL depends on transition Example to to B Iref DNL d/ DNL d/ Iref Iref Iref Consider MSB transition EECS Lecture Data Converters.Ion Ion .Ioff . . .Ion I Iref I Iref I I Iref Iref Ion . .Ioff .DAC Design Page DAC DNL Example bit DAC . Ioff .Ioff Ioff.DAC Design . Ion . DAC Design Page Id Id ...Current mismatch due to threshold voltage variations Larger gateoverdrive less threshold voltage mismatch effect EECS Lecture Data Converters.. LSB Page EECS Lecture Data Converters..Device W/L ratio matching Larger device area less mismatch effect .DAC Design MOS Current Source Variations Due to Device Matching Effects Id Id Id dId Id Id Id Id dId dW L dVth W Id VGS Vth L Current matching depends on . DAC Output LSB DNL .Binary Weighted DAC DNL DNL for a Bit DAC Worstcase transition occurs at midscale DNL B B DNL/ . LSB INL . . B DNLma x B / INLmax B DNLmax Example B. .DAC Design Page Unit Element versus Binary Weighted DAC Unit Element DAC Binary Weighted DAC DN L IN L IN L B B DN L IN L B Number of switched elements S B SB Key point Significant difference in performance and complexity EECS Lecture Data Converters.. Example bit Binary Weighted Advantages Can be very fast Reasonable area for resolution lt bits Disadvantages Accuracy depends on device W/L amp Vth matching EECS Lecture Data Converters..DAC Design Page .CurrentSwitched DACs in CMOS Iout Iref dId Id dW L W L Switch Array d Vth VGS Vth . / .DAC Design Page Another Random Run DNL LSB INL LSB bin bin DNL and INL of Bit converter / .Unit Element versus Binary Weighted DAC Example B Unit Element DAC Binary Weighted DAC DN L IN L B DN L B INL B Number of switched elements S B S B Significant difference in performance and complexity EECS Lecture Data Converters. LSB.DAC Design Page . Now by chance worst DNL is midscale. Close to statistical result . LSB EECS Lecture Data Converters. . . Note EECS Lecture Data Converters. Lin and K. Lin and K.quot IEEE Journal of SolidState Circuits. mm. quotA b.DAC Design Page . December . MSample/s CMOS DAC in . . Bult.. December . .quot IEEE Journal of SolidState Circuits. vol. pp. vol.DAC Design Page Bit DAC DNL/INL Comparison Plots RMS for Simulation Runs Ref C. Note EECS Lecture Data Converters. MSample/s CMOS DAC in .Bit DAC DNL/INL Comparison Plots Simulation Runs Overlaid Ref C. Bult. quotA b. mm. pp. . vol. Kato.. Miyakawa. IEEE Transactions on Circuits and Systems. K.. K. Nonlinearity analysis of resistor string A/D converters. June ..CAS. no. N.DAC Design Page Segmented DAC Combination of UnitElement amp BinaryWeighted Objective Compromise between unitelement and binaryweighted DAC MSB B bits B bits LSB Unit Element Binary Weighted Approach B MSB bits B LSB bits unit elements binary weighted VAnalog BTotal BB INL unaffected same as either architecture DNL Worst case occurs when LSB DAC turns off and one more MSB DAC element turns on Same as binary weighted DAC with B of bits Number of switched elements B B EECS Lecture Data Converters. Matsubara.. EECS Lecture Data Converters.DAC Design Page .. S. p.DAC INL/DNL Summary DAC choice of architecture has significant impact on DNL INL is independent of DAC architecture and requires element matching commensurate with overall DAC precision Results assume uncorrelated random element variations Systematic errors and correlations are usually also important and may affect final DAC performance Ref Kuboki. B . DNLLSB .Comparison Example B .DAC Design Practical Aspects CurrentSwitched DACs Unit element DACs ensure monotonicity by turning on equalweighted current sources in succession Typically current switching performed by differential pairs For each diff pair. B . . . .DAC Design . MSB B B LSB DNL I NL B I NL B Assuming S B B INLLSB . . only one of the devices are on switch device mismatch not an issue Issue While binary weighted DAC can use the incoming binary digital word directly. . of switched elements Page DAC Architecture BB Unit element Segmented Segmented Binary weighted EECS Lecture Data Converters. . unit element requires a decoder Binary Thermometer Page N to N decoder EECS Lecture Data Converters. Segmented CurrentSwitched DAC Example bit MSBLSB bit MSB Unit element DAC bit binary weighted DAC Note bit MSB DAC requires extra to bit decoder Digital code for both DACs stored in a register EECS Lecture Data Converters.DAC Design Page .DAC Design Page Segmented CurrentSwitched DAC Contd bit MSB Unit element DAC bit binary weighted DAC Note bit MSB DAC requires extra to bit decoder Digital code for both DACs stored in a register EECS Lecture Data Converters. Segmented CurrentSwitched DAC Contd MSB Decoder Domino logic Example D.DAC Design Page . OUT Domino Logic Register Latched NAND gate CTRL OUTINB EECS Lecture IN Register Page Data Converters.DAC Design Segmented CurrentSwitched DAC Reference Current Considerations Iref is referenced to VDD Problem Reference current varies with supply voltage Iref VDDVref / R EECS Lecture Data Converters... DAC Design Page .Segmented CurrentSwitched DAC Reference Current Considerations Iref is referenced to Vss GND Iref Vref Vss / R EECS Lecture Data Converters.DAC Design Page Segmented CurrentSwitched DAC Considerations Example bit MSB Unit element DAC amp bit binary weighted DAC To ensure monotonicity at the MSB LSB transition First OFF MSB current source is routed to LSB current generator LSB MSB EECS Lecture Data Converters. Early Late .g. . MSB early DAC Output Ideal .DAC Design Page Dynamic DAC Error Timing Glitch Consider binary weighted DAC transition DAC output depends on timing Plot shows situation where the control signals for LSB amp MSB LSB/MSBs on time LSB early. MSB late LSB late. . . Time .DAC Design Page . EECS Lecture Data Converters.DAC Dynamic NonIdealities Finite settling time Linear settling issues e. RC time constants Slew limited settling Spurious signal coupling Coupling of clock/control signals to the output via switches Timing error related glitches Control signal timing skew EECS Lecture Data Converters. ltlt .Glitch Energy Glitch energy worst case proportional to dt x B dt error in timing amp B associated with half of the switches changing state LSB energy proportional to T/fs Need dt x B ltlt T or dt ltlt B T Examples fs MHz B dt ps ltlt ltlt .DAC Design Page .DAC Design Page DAC Dynamic Errors To suppress effect of nonidealities Retiming of current source control signals Each current source has its own clocked latch incorporated in the current cell Minimization of latch clock skew by careful layout ensuring simultaneous change of bits To minimize control and clock feed through to the output via GD amp GS of the switches Use of lowswing digital circuitry EECS Lecture Data Converters. Timing accuracy for data converters much more critical compared to digital circuitry EECS Lecture Data Converters. JSSC December . pp. J. J. W. Current copiers D. pp.DAC Implementation Examples Untrimmed segmented T. Groeneveld et al. Miki et al. EECS Lecture Data Converters. A.DAC Design Page . JSSC December . van de Plassche. Vsupply segmented EECS Lecture Data Converters. pp. JSSC December . Dynamic Element Matching for HighAccuracy Monolithic D/A Converters. pp.DAC Design Page x array tech. Van den Bosch et al. An MHz bit CMOS D/A Converter. A SelfCalibration Technique for Monolithic HighResolution D/A Converters.. A GSample/s Nyquist CurrentSteering CMOS D/A Converter. Dynamic element matching R. JSSC March . Two sources of systematic error .DAC Design Page .DAC Design Page CurrentSwitched DACs in CMOS Assumptions RxI small compared to transistor gateoverdrive To simplify analysis Initially. all device currents assumed to be equal to I VGSM VGSM RI VGSM VGSM RI VGSM VGSM RI VGSM VGSM RI I k VGSM Vth Iout VDD VG M I M I M I M I M I RI I I VGS Vth M EECS Lecture RxI RxI RxI RxI Example unit element current sources Data Converters.Voltage drop due to finite ground bus resistance EECS Lecture Data Converters.Finite current source output resistance . . INL LSB Sequential current source switching Symmetrical current source switching Input Example unit element current source DAC. EECS Lecture Data Converters.assume gmR/ If switching of current sources arranged sequentially INL .LSB If switching of current sources symmetrical INL .. .LSB INL reduced by a factor of .DAC Design Page .CurrentSwitched DACs in CMOS R I I k VGSM Vth I VGSM Vt h I gmM VGSM Vth Iout VDD M RgmM I I I RgmM RgmM I I I RgmM RgmM I I I RgmM R gmM I I I RgmM I M I M I M I M I RxI RxI RxI RxI Example unit element current sources Desirable to have gm small EECS Lecture Data Converters. .DAC Design Page CurrentSwitched DACs in CMOS Example INL of Bit unit element DAC . . DAC Design Page . DNL LSB .DAC Design Two sources of systematic error .LSB If switching of current sources symmetrical DNLmax .Finite current source output resistance . . .CurrentSwitched DACs in CMOS Example DNL of unit element DAC .assume gmR/ If switching of current sources arranged sequentially DNLmax . Sequential current source switching Symmetrical current source switching Input Example unit element current source DAC.Voltage drop due to finite ground bus resistance EECS Lecture Data Converters.LSB EECS Lecture DNLmax unchanged Page Data Converters.