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1
An In-Phase-Coupled Class-C Quadrature VCO
with Tunable Phase Error
Yuxiang Zhang and Chirn Chye Boon

Abstract—This letter presents the design and analysis of a novel
in-phase-coupled (IPC) Class-C Quadrature Voltage-Controlled
Oscillator (QVCO) with tunable phase error. The IPC QVCO
employs a novel coupling structure that generates in-phase
coupling signal while consuming negligible power itself. IPC
scheme enables the QVCO to achieve better phase noise and phase
error compare to that of the conventional QVCO. The phase error
of the proposed IPC QVCO is also tunable. The proposed IPC
QVCO is fabricated using 0.18 µm CMOS technology and the
measured output frequency range is from 2.5 GHz to 2.97 GHz. At
2.623 GHz, with 3.6 mW power consumption, the phase noise at
1MHz offset achieves -126.8 dBc/Hz while the phase error before
phase error tuning is 0.5º. The measured phase error tuning range
is  17º.
Index
Terms—in-phase-coupled
(IPC),
quadrature
voltage-controlled oscillator (QVCO), CMOS, tunable phase
error, negligible coupling power.
I. INTRODUCTION
Q
UADRATURE signal generation is becoming more
essential in modern transceiver design. There are several
methods to generate quadrature signal, such as using
divide-by-two divider, poly-phase network and QVCO. Among
these approaches, the cross-coupled QVCO has been widely
used due to its low power consumption and wide frequency
tuning range [1]. As analyzed in [2] and [3], due to the phase
difference of the coupling signal introduced in the conventional
parallel QVCO or series QVCO, the phase noise is degraded.
Alternatively, coupling can be implemented through substrate
connection [4], which requires non-conventional CMOS
technology. On the other hand, after first introduced in [5],
Class-C VCO has attracted much interest due to its excellent
phase noise performance and larger amplitude compare with
conventional LC VCO with the same power consumption.
However no Class-C QVCO has been proposed and
demonstrated yet.
Recently, a few IPC schemes are introduced [3,6,7]. The
in-phase coupling naturally eliminates the trade-off between
the phase noise and the phase accuracy as shown in [3].
However, the phase error of these proposed IPC QVCO is not
tunable and the IPC scheme proposed in [3] is frequency
dependent. In addition, the coupling circuitry proposed in [6]
consumes considerable power.
In this letter, a novel IPC Class-C QVCO with tunable phase
error is presented to achieve ultra low phase noise, phase error
and power consumption. The designed prototype targets for
ISM band application and is implemented in 0.18 µm CMOS
technology.
II. PROPOSED TUNABLE PHASE ERROR IPC CLASS-C QVCO
The schematic of the proposed IPC Class-C QVCO is shown
in Fig 1. When Vbias2  Vbias3 , the two Class-C VCO cores
are identical thus the output amplitude VA and DC offset are the
same. The coupling structure consists of 8 identical transistors
whose drain terminals are all connected to VDD. As the DC
offset of the VCO's output is lower than VDD due to the resistor
R 2 , these coupling transistors work either in off or saturation
region. As shown in Fig 2, these transistors only turn on when
V gs  V th . As both the size and the conduction angle of the
coupling transistor are designed to be small, the current
consumption of these transistors are much smaller than that of
the VCO core. Simulation shows for the proposed IPC QVCO
the rms current of each coupling transistor is only about 10 µA.
The Fourier transform for each coupling transistor's current is
obtained and for simplicity suppose that the Q of the LC tank is
high enough thus only the fundamental component is of
interest. The current amplitude can thus be calculated as:
I C  K  ( VA  sin

2

(1)
 Vth )
where K is a constant decided by the physical properties of the
coupling transistor and  is the phase difference between V g
and V s of the coupling transistor where 0     . The phase
of the current is the same as the corresponding V g s .
Suppose the phase of the four outputs I+, I-, Q+ and Q- of
the QVCO are  0  t  1 ,  0  t  1   ,  0  t   2 and
 0  t   2   respectively, where  0 is the angular frequency
and 0  2  1  2 . Following the analysis above, the current
of MC1 and MC2, IC1 and IC2, can be expressed as:
I C 1  I C 1  sin( 0 
Zhang Yuxiang is a Ph.D student with School of Electrical and Electronical
Engineering, Nanyang Technological University, Singapore 639798
([email protected])
Boon Chirn Chye is with School of Electrical and Electronical Engineering,
Nanyang Technological University, Singapore 639798 ([email protected])
2

1   2

 )
2
2
1   2
I C 2  I C 2  sin( 0 
 )
2
where I C 1 and I C 2 are calculated by (1).
(2)
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VDD
I+
I+
VTUNE
VAR2
VAR1
C1
VAR4
VAR3
C2
I-
MC3
MC4
MC1
VDD MC2
Q+
I+
MN1
MN2
R1
R1
MN3
R1
R1
MN4
Vbias3
Vbias2
Q+
MC5
VDD
MC7
Vbias1
I0
C5
I-
C4 Q-
Q+ C3
Vbias1
I0
MC6
MC8
Q-
C6
I-
Fig. 1. Schematic of the proposed IPC Class-C QVCO
According to the generalized equation for multiple injections
introduced in [3], frequency of the Q+ branch and I+ branch
can be calculated. Since the frequencies of these two branches
are equal, it can be shown that 1  2   2
25
1.0
Vgs1 (V)
15
0
10
-0.5
IC1 (µA)
20
0.5
5
1.0
0
19
19.5
20.5
20
K  Vth

I 0  ( Q   I )  ( A  2 B )  ( I  Q )
(6)
As shown in Fig 3(a), simulation result matches the calculation
with (6). Generally, larger free-running frequency difference
leads to larger phase error. Equation (6) also indicates that 
can be tuned by setting Vbias2  Vbias3 thus making  I and
 Q to be different.
Phase tuning scheme has been proposed in [2] for
conventional parallel QVCO. However the effect of the
parasitic elements is ignored. Furthermore, as shown in [2], a
smaller m is essential for good phase noise performance but it
will increase the phase error. This trade-off limits the range of
m which determines the phase tuning range for a limited tuning
voltage. The phase tuning scheme proposed in [8] requires
extra inductor and varactor which occupy large area while the
tuning range is also limited.
For the proposed phase tuning scheme, m does not affect the
phase noise performance as I inj is in-phase with the injected
current. Hence the proposed IPC QVCO does not suffer from
the tradeoff between phase noise and phase error due to m.
Furthermore, no extra inductor or varactor is required. In this
work, for the same  I and  Q , a larger K leads to a smaller
t (ns)
Fig. 2. Gate-source voltage and current of coupling transistorMC1.
Thus the current injected into Q+ branch is:
I inj  I C 1  I C 2   2  K  ( VA 
2  Q  [ I 0  ( A  2 B ) 2 ]  ( Q  I )
2

where A  KVA and B  2  K  Vth 2 . To verify (6), the
proposed QVCO is designed with ideal elements whose
parasitic capacitance is eliminated for simulation purpose. The
difference between  I and  Q is introduced with various K.
2
2
 Vth  )  sin( 0  t   2 ) (3)
2

which is in-phase with the current of the Q+ branch. Similar
results can be obtained for all the four branches thus the IPC is
achieved. According to analysis in [5] and [6], phase noise will
not degrade compare with the stand-alone VCO. Furthermore,
the simulated rms Impulse Sensitivity Function (ISF) value of
the proposed IPC Class-C QVCO is smaller by 20% compared
to conventional parallel QVCO structure with the same
coupling transistors. In addition, in the proposed circuit the
outputs of the VCO core is connected to 2 transistors' gate and
source, such connection allows a good central symmetrical
layout to be implemented, thus mismatch can be reduced to
achieve good phase error and phase noise performance.
It is also worth to note the coupling factor m is defined as the
ratio between I inj and the oscillation current. For the proposed
phase error as can be derived from (6). Conversely, a smaller K
leads to larger phase error thus a wider phase tuning range can
be achieved. In practice, the voltage accuracy of Vbias2 and
Vbias3 is limited, hence there exists a trade-off between phase
tuning range and phase accuracy. The simulated  versus
Vbias2  Vbias3 for different K is shown in Fig 3(b).
(a)
16
|ϕ| (º)
VTUNE

Q-
(b)
30
K=40 µS
K=30µS
8
Simulated
Calculated
K=40µS
|ϕ| (º)
R2
2
Simulated
20
Measured
10
K=30µS
K=100 µS
K=50µS
0
0.2
0.6
1.0
|ω1-ω2|/ω1 (10-4)
0
5
15
10
|Vbias2-Vbias3| (mV)
20
Fig. 3. Calculated, simulated and measured  for different K versus (a)
mismatch of free-running frequency and (b) Vbias2  Vbias3
IPC Class-C QVCO, m can be calculated as:
m
2  K  ( VA 
2
2
 Vth  )  I 0
2

(5)
which is proportional to K.
Analysis above is based on the assumption that
Vbias2  Vbias3 . However, when this is not valid, the
difference in parasitic capacitance will result in difference
between  I and  Q , the free-running frequencies of the two
VCO core. According to analysis above phase error arises if
f Q   f I  is still valid. The phase error  can be calculated as:
III. MEASUREMENT RESULTS
The proposed IPC Class-C QVCO is fabricated in
GlobalFoundries CMOS 0.18 µm technology. The die
photograph is shown in Fig 4.
The tuning range of the proposed IPC Class-C QVCO is
from 2.5 GHz to 2.97 GHz and the power consumption is 3.6
mW with a 1.2-V power supply. A 20 GSa/s WaveMaster
8600A oscilloscope is used to measure the I/Q signal in the time
domain and the phase error is calculated. The maximum phase
error of the proposed IPC Class-C QVCO over the operation
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range is 5º/2º before and after phase error tuning respectively.
Fig 5 shows the measured spectrum and waveform of the
proposed IPC Class-C QVCO at 2.623 GHz frequency with
Vbias2  Vbias3 . The phase error is 0.5º. After introducing
voltage difference between Vbias2 and Vbias3 manually for
measurement, phase error changes. The maximum phase shift
happens when Vbias2 is larger than Vbias3 by 20 mV with a
corresponding phase error of 17º. The shift in oscillation
frequency is less than 1MHz while the amplitude shifts by 8
mV.
f0 (GHz)
Power(mW)
Phase noise
(dBc/Hz)
Phase error
FoM (dBc)
5
4.2
-121@
1 MHz
0.6 º
189
FoM  10  log10  [(
63
11.4
-95@
1MHZ
0.7 º
180
9.3
9
-121@
3 MHz
8º
182
5.5
2.5
-114@
1 MHz
5º
185
3
2.7
3.6
-126.8@
1 MHz
0.5 º
190
f0 2
1
) 
]
f
L{ f }  Pdc
Table I summarizes the major performance of the proposed
IPC Class-C QVCO with other state-of-the-art QVCOs with
various coupling topology. As shown in the table, the proposed
work achieved the best FoM and phase error. Compare with the
proposed IPC QVCO, the phase error tuning scheme proposed
in [8] has only phase tuning range  11º.
IV. CONCLUSION
In this letter, a novel IPC Class-C QVCO is proposed. The
mechanism of the in-phase coupling and the quadrature signal
generation is analyzed. While consuming negligible power
itself, the IPC scheme ensures the QVCO to achieve good phase
noise and phase error simultaneously. According to the
mechanism analyzed, a phase error tuning scheme for the
proposed IPC Class-C QVCO was established. The proposed
IPC QVCO is fabricated with 0.18 µm CMOS technology and
the measured frequency tuning range is from 2.5 GHz to 2.97
GHz with phase error tuning range of  17º and FoM of 190
dBc.
Fig. 4. Die photograph of the proposed IPC Class-C QVCO
REFERENCE
Fig. 5. Measured waveform and spectrum of the proposed IPC Class-C QVCO
at 2.623 GHz before phase error tuning.
[1]
The measured and simulated phase noise of the proposed IPC
Class-C QVCO at 2.5 GHz is shown in Fig. 6. The measured
phase noise at 1 MHz offset frequency is -126.8 dBc/Hz.
[2]
[3]
[4]
[5]
[6]
[7]
Fig. 6. Measured and simulated phase noise of the proposed IPC Class-C
QVCO.
[8]
TABLE I
COMPARISONS OF QVCO'S PERFORMANCE
[9]
Tech (µm)
[6]
[7]
[8]
[9]
0.13
0.065
0.18
0.18
This
Work
0.18
C.C. Boon, M.A. Do, K.S. Yeo and J.G. Ma, “Fully Integrated CMOS
Fractional-N Frequency Divider for Wide-Band Mobile Applications
with Spurs Reduction”, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 52,
no.6, pp. 1042-1048, 2005.
I. R. Chamas and S. Raman, "A Comprehensive Analysis of Quadrature
Signal Synthesis in Cross-Coupled RF VCOs,” IEEE Trans. Circuits Syst.
I, Reg. Papers, vol. 54, no.4, pp. 689-704, 2007.
A. Mirzaei eta al., “The quadrature LC oscillator: a complete portrait
based on injection locking,” IEEE J. Solid-State circuits, vol.42, no. 9, pp.
1916-1932, 2007.
Emad Ebrahimi and Sasan Naseh, “A Colpitts CMOS Quadrature VCO
Using Direct Connection of Substrates for Coupling,” IEEE Trans. Very
Large Scale Integration (VLSI) systems, vol. 21, pp. 571-574, 2013.
A. Mazzanti and P. Andreani, " A 1.4mW 4.90-to-5.65GHz Class-C
CMOS VCO with an Average FoM of 194.5dBc/Hz" in IEEE int.
Solid-State Circuits Conf. Dig. 2008, pp 474-429
Yung-Chung Lo, and Jose Silva-Martinez, “A 5-GHz CMOS LC
Quadrature VCO With Dynamic Current-Clipping Coupling to Improve
Phase Noise and Phase Accuracy,” IEEE Trans. Microwave theory and
techniques, vol. 61, pp. 2632-2640, 2013.
X. Yi, C. C. Boon, H. Liu, J. F. Lin and W. M. Lim, " A 57.9-to-68.3 GHz
24.6 mW Frequency Synthesizer With In-Phase Injection-Coupled
QVCO in 65 nm CMOS Technology", IEEE J. Solid-State circuits,
vol.49, no. 2, pp 347-359, 2014.
I. R. Chamas and S. Raman " Analysis and Design of a CMOS
Phase-Tunable Injection-Coupled LC Quadrature VCO (PTIC-QVCO)"
IEEE J. Solid-State circuits, vol.44, no. 3, pp 784-796,. 2009.
H. Tong, S. Cheng, Y. C. Lo, A. I. Karsilayan and J. Silva-Martinez, "An
LC quadrature VCO using capacitive source degeneration coupling to
eliminate biomodel oscillation." IEEE Trans. Circuits Syst. I, Reg.
Papers, vol. 59, no. 9, pp. 1871-1879,. 2012.