Download CMS phase 2 pixel electronics

CMS phase 2 pixel electronics
Pixel electronics system
Fig. 1. On-detector pixel electronics system shown for pixel barrel configuration.
The general architecture/implementation of the pixel electronics system is schematically indicated in
Fig. 1 for a typical barrel layout. Hybrid pixel detector modules are made from multiple (e.g. 2 x 4)
pixel Read-Out Chips (ROC) bump bonded to a single pixel sensor. Readout and control signals plus
power is connected to the ROCs with wire-bonding to a thin and light Printed Circuit Board (PCB)
glued on the back side of the pixel sensor. Low mass cables connect the pixel modules to the global
readout, control and powering systems. The heat generated by the pixel chips (and sensor) is
evacuated via a heat distribution layer to thin CO2 cooling pipes.
The optional use of Through Silicon Vias (TSV), to get readout signals and power of the ROC out on
the back side of the pixel chips will also be investigated to build more compact pixel detector
modules with reduced dead area/material. In this case the PCB will be located on the back side of
the pixel ROCs and connect to these via coarse/standard pitch bump bonding.
A hermetic pixel detector with 4 barrel layers and 10 end-cap disks on each side is built from
individual pixel modules. It is proposed to build the complete pixel detector with a minimal number
(2-4) of different pixel module types to minimize design complexity and cost of the final pixel
detector system. Pixel modules will have a scalable number of Electrical readout links (E-links) to
match required readout data rates across different pixel layers and locations.
A significantly improved pixel resolution and resolving capability for high multiplicity tracks in high
density jets is required for the phase 2 upgrade. Two basic pixel sizes of 50 x 50um2 and 25 x 100um2
(same pixel area) have been found to be the most promising compromise between significantly
improved tracking/vertex performance and what can realistically be implemented in a next
generation pixel readout chip and pixel sensor. This pixel size is also compatible with available bump
bonding technologies. With an appropriate bump-bonding pattern the same ROC can be used for the
different pixel aspect ratios. Elongated pixels (25x100um2) are optimal in some parts of the pixel
detector (e.g. end of barrel layers with inclined tracks) and square pixels (50x50um2) are optimal in
other parts (middle of barrel and forward disks with near perpendicular tracks). Using exactly the
same pixel electronics (ROC plus pixel modules) for bump bonding to the different pixel sensors
allows a flexible optimization to be made according to the best possible knowledge of optimal
physics performance, as this will evolve over the coming years. For outer pixel layers, with lower hit
rates and less stringent requirements for resolution, larger pixel sizes can be used with the same
electronics by powering down unused pixel channels in the ROC when pixel bump pads are made
compatible with the defined 50um bump-bonding grid.
Fig. 2. 50um Bump bonding grid, and disabling pixel cells, for different pixel sizes and aspect ratios.
It is at the time of writing not yet determined what the final pixel sensor technology (and sensor
thickness) will be. The pixel electronics will therefore be designed with high flexibility in mind to
accommodate appropriate charge collection and low detection threshold for a defined set of sensors
technologies (planar, 3D). For sensor technologies with relatively small signals (or large capacitance)
the bias currents of the analogue front-end of the ROC will have to be increased (implying increased
power consumption) to maintain sufficiently low detection thresholds and noise levels. It can also be
envisaged to use different sensor technologies in different parts of the pixel system.
The phase 2 pixel detector will for HL-LHC conditions have to sustain pixel hit rates of up to
2GHz/cm2 for the innermost pixel layer. The ~10 times higher hit rates, compared to today’s LHC, in
combination with the proposed increased trigger rate from 100KHz to 500KHz or 1MHZ implies that
50 – 100 times more data will have to be readout of the new pixel detector. For a ~2cm x 2cm pixel
chip in the inner barrel a readout bandwidth of up to 4Gbits/s will be required per ROC for a 1MHz
trigger rate.
The lowest possible material budget is critical for the physics performance of such new high
resolution pixel detector. In addition to the dependency on chosen pixel sensor thickness (100–
200um) and thickness of the ROC (100 -200um), the material budget is mainly driven by the power
consumption of the pixel detector electronics (the ROC) and the related cooling plus power
distribution and readout services. Electronics services (power, optical links) will to the extent
possible be located close to the pixel detector but outside its main acceptance.
The pixel detector electronics will have to work reliably for 10 years under extremely hostile
radiation conditions of up to 10MGy and 2 1016 hadrons/cm2. This is unprecedented radiation levels
for electronics of this complexity. A large part of the required R&D efforts will be assigned to design
and qualify front-end electronics to work reliably under such harsh radiation conditions. Radiation
levels are so high that it may possibly be required to exchange parts of the pixel detector (inner
layers) after a limited number of years (e.g. 5 years) at full HL-LHC luminosity. Extensive radiation
hardness studies in the coming 2-3 years will determine if a partial replacement strategy will be
necessary.
Assumed that general pixel detector layout is described somewhere else. Otherwise this needs to
be included.
Pixel Readout chip:
The pixel readout chip is the critical building block of the pixel electronics system. ~6 times smaller
pixels, ~10 times higher hit rates and radiation levels in combination with 5-10 times higher trigger
rates, compared to LHC, makes it a significant challenge to design the ROC. It has therefore been
emphasized to start the R&D activities related to the ROC as early as possible. The use of a modern
high density IC technology with sufficient radiation tolerance is critical. A modern 65nm CMOS
technology has been found particular promising to cope with these challenges. It has the required
density to cope with the 6 times higher pixel density and the ~100times larger buffering
requirements (10x hit rates, 10x trigger latency). Initial radiation tests have been very promising with
additional careful verifications required for total dose levels above the 2-3MGy level where
significant radiation effects are encountered [ref1: Radiation tolerance of 65nm]. Operation
temperature (e.g. -20oC) of the pixel detector, and regular periods at higher temperature (e.g. room
temperature), have significant effects on annealing of the accumulated radiation effects in the basic
CMOS transistors.
The 65nm technology node has been chosen by both the CMS and ATLAS phase 2 pixel upgrade
projects as baseline technology and a cross experiment collaboration, named RD53 [Ref2: RD53
proposal], has been formed. This formal collaboration with 19 participating institutes has a good
balance between ATLAS and CMS participation. It will make the required radiation
testing/qualification of the proposed IC technology and develop the required IC circuits to build the
next generation pixel ASIC that will have an unprecedented complexity of up to 1 billion transistors.
A large pixel prototype chip with 50 x 50um2 pixels will be designed and prototyped within this
collaboration framework within the initial 3 year R&D program. In addition, RD53 develops a pixel
chip and system simulation and verification framework with defined readout and control protocols.
A common pixel chip architecture, that is fully digital after the basic threshold detection and charge
digitization in the analogue pixel cell, has been defined as shown in Fig. 3.
Fig. 3. RD53 digital pixel chip architecture.
Digital hit processing, including the critical trigger latency buffer, is implemented within the pixel
array in local pixel regions (e.g. 2 x 2 or 4 x 4 pixels) followed by data merging, data formatting and
readout after the first level trigger accept. Buffering requirements have been analysed with a
statistical model [Ref3: Statistical model] and simulations and have been verified to be compatible
with the proposed extended CMS trigger latency of 10us (and optionally 20us) as summarized in Fig.
4. A buffer depth of 16 pixel clusters for a 4 x 4 pixel region is sufficient to guarantee a hit loss
probability below 10-3 for a 10us trigger latency and below 10-2 for an optional 20us latency for the
absolute highest hit rate of 2GHz/cm2 .
Fig 4. Pixel Region (PR) latency buffer usage and associated hit losses as function of buffer size, pixel
region organization and trigger latency.
The physical size of the pixel chip will be optimized as a compromise between practical pixel
detector layout considerations, pixel chip yield and bump-bonding considerations. A pixel chip size of
2.3 x 2.3 cm2 with ~85% active pixel area (~15% required for end of column readout, control
interface and wire bonding pads) has been found appropriate for the proposed pixel detector layout
and is compatible with chip sizes that can be produced reliably in the 65nm technology.
Pixel module
Pixel detector modules will be designed for the highest possible flexibility to enable the construction
of a pixel detector with a minimum set of different module sizes/types. Each pixel module type can
be implemented with pixel sensors of different pixel size and pixel shape. In addition the pixel
modules will have a given number of readout links available that can be utilized according to the
needs of each pixel layer and specific location.
The basic pixel module designs will be driven by layout and readout constraints of the highly
demanding inner barrel layers and the outer layers. A narrow module is specifically made for the
inner layers and a larger module is made for the outer barrel layers and the forward disks.
A. Narrow module of 1 x 4 pixel chips (2.3cm x 9.2cm) for inner barrel layers
B. Wide module of 2 x 4 pixel chips (4.6cm x 9.2cm) for outer pixel layers and forward disks
Fig. 5. Pixel modules optimized for inner and outer layers of pixel barrel.
Modules will be assembled in a similar fashion as the current and phase 1 upgrade pixel detector
modules [ref4: CMS phase 1 pixel upgrade TDR]. The use of large pixel chips to construct pixel
modules with reduced pixel bonding costs and higher effective sensitive area has been well
demonstrated by the ATLAS pixel IBL upgrade [ref5: ATLAS IBL upgrade TDR]. If TSVs in the ROC can
be used (question of access, yield and cost) a more compact module can possibly be designed.
Pixel readout and control
Hit rates and the corresponding required readout rates varies largely (more than factor 10)
depending on the location in the pixel detector. The very high readout rates required for HL-LHC, in
combination with the fact that optical links cannot be used directly on the pixel modules because of
the very high radiation levels (and small space), implies that a significant material contribution will
be associated to the data transport out of the pixel detector volume. There is therefore a significant
interest in being capable of adapting the number of high speed electrical readout links used per
module to the expected hit rates, with sufficient safety margins. Each pixel module/ROC will
therefore have a given number of E-links available that can be used according to estimated hit/data
rates (and adopted trigger rate). For the absolute highest expected hit rates in the inner barrel layer
a readout bandwidth of up to 4Gbit/s per ROC will be required for a 1MHz trigger rate. Further
studies will determine if the required readout data rates can be reduced by implementing intelligent
cluster extraction/compression on the pixel ROC. The potential data reduction is of the order of a
factor 2 with the “cost” of implementing complex intelligent logic on the ROC that must be
guaranteed to work efficiently for different pixel sensor types/configurations and must work reliably
in a harsh radiation environment with significant levels of Single Event Upsets (SEU). Triple Modular
Redundancy (TRM) will be required in all critical functions of the ROC.
It is proposed to use a second generation of the radiation hard GBT link chip [ref6: GBT], called the
Low Power GBT (LPGBT), for the conversion to high speed optical links at 10Gbits/s. The LPGBT chip
and associated VCSEL laser/driver are not expected to have sufficient radiation tolerance to be used
in the central part of the pixel detector itself. It is proposed to place the optical link conversion in the
forward region on service cylinders as done for the phase 1 pixel upgrade [ref4: CMS phase 1 pixel
upgrade TDR] as indicated in Fig. 6 below.
Fig. 6. Use of service cylinder for opto and power services as done for the CMS phase1 pixel upgrade
[Ref4: CMS phase 1 pixel upgrade TDR].
The Electrical links (E-links) from the ROC to the LPGBT will for this configuration be limited to a
maximum length of 2m. It is proposed to use 1.2Gbits/s electrical links on very light twisted pair
cables to opto service modules. Highly optimized cable drivers and receivers will be used for the Elinks to minimize the mass of the cable and “squeeze” the highest possible link bandwidth through
such a low-mass cable. Active cable equalization will be used to get a data link rate that is several
times higher than the basic analog bandwidth of the cable (This is an extensively used technique for
commercial high speed networking via twisted pair cables). It is also considered appropriate to use
E-link bandwidths limited to 1-2 Gbits/s as it is known that the high speed performance of the ROC
chips may be significantly affected by the very high radiation levels. For highest hit rate regions of
the pixel detector up to 4 such 1.2Gbits/s links will be required per ROC for a trigger rate of 1MHz (2
per ROC at 500KHz trigger). The ROC will be designed with up to 8 such 1.2Gbits/s E-links per chip to
have large margins for when more detailed information on hit rates and readout rates will become
available. For the outer pixel layers the required readout rate per ROC will be below the 1.2Gbits/s
available on an E-link. The ROC will therefore have a built in data merging function where data from
2-4 ROCs can be merged into one E-link as illustrated in Fig. 7.
Fig. 7. Highly flexible readout link interface with up to 8 E-links per ROC, with active cable
equalization, and the possibility of merging data from 2-4 ROCs into one E-link.
Pixel powering and cooling
It is known that an appropriate low mass power distribution system for the phase 2 pixel detector
will pose significant challenges and will require a focussed R&D effort to arrive at a viable and
acceptable solution. It is estimated that with the use of a modern 65nm CMOS technology the
power consumption of the pixel chip can be maintained at a power dissipation density of the order
of 0.3 – 0.5W/cm2, similar to or limited to a factor two higher than the current CMS pixel detector.
Modern low power design techniques and design tools will be employed to get the absolute lowest
power dissipation for such a complex high rate pixel chip. The exact power density of a final pixel
chip is currently very hard to predict as many delicate and detailed design choices and optimizations
will have to be made. Detailed characterization and obtaining a better understanding of radiation
induced transistor leakage is on-going, but not yet finalized.
The relatively large power supply currents needed by low voltage - low power integrated circuits
(power consumption in IC has a Vdd2 relationship) pose significant challenges for the power delivery
to the pixel chips. It is excluded to deliver the required low voltages and high currents with a passive
power distribution system from the low voltage power supplies outside the experiment. DC-DC
power conversion based on inductors is excluded on the pixel modules themselves because of the
very high radiation levels and very tight constraints on material/space. Remaining powering options
to be explored are: A: Distributed DC-DC conversion scheme with air-core inductor based DC-DC
conversion in the vicinity (~2m) of the pixel detector in combination with switched capacitor power
conversion on the pixel chip itself; B: Serial powering with on-chip shunt regulators. A serial
powering scheme per pixel module with on-chip shunt regulators currently appears as the most
attractive solution, but many important and delicate aspects needs to be extensively studied and
verified before this can be considered as an optimal/viable solution. A combination of serial
powering with on-chip switched capacitor power conversion/regulation is a particular interesting
option.
The phase 2 pixel cooling system will be based on well proven concepts from the CO2 cooling system
used for the phase 1 pixel upgrade. The cooling system will need extensive detailed optimizations on
how best to transfer the heat from the pixel modules to the small diameter high pressure CO2
cooling pipes with minimum mass. It is highly preferred to maintain a mounting/cooling scheme that
allows broken pixel modules to be replaced. An alternative of a glued mounting approach will also
be evaluated for possible gains in material budget. Finally an option of pre-assembled pixel staves
with integrated cooling and readout links and power distribution services will be investigated.
References
[1]: Radiation tolerance of 65nm
TWEPP2011.
Characterization of a commercial 65 nm CMOS technology for SLHC applications.
S.Bonacini et al., 2012 JINST 7 P01015
http://iopscience.iop.org/1748-0221/7/01/P01015
Latest presentation in RD53 meeting (not publicly available):
https://indico.cern.ch/event/296570/session/7/contribution/9/material/slides/
No official publication on this yet from RD53.
Common paper from CPPM & CERN in the pipeline ?
[2]: RD53 collaboration: www.cern.ch/RD53
[3]: E. Conti et al., Pixel chip architecture optimization based on a simplified statistical and analytical
model .
TWEPP2013
2014 JINST 9 C03011
http://iopscience.iop.org/1748-0221/9/03/C03011
[4]: CMS Technical Design Report for the Pixel Detector Upgrade.
CERN-LHCC-2012-015 ; CMS-TDR-10. – 2012.
https://cds.cern.ch/record/1481838
[5]: ATLAS Insertable B-Layer Technical Design Report.
CERN-LHCC-2010-013 ; ATLAS-TDR-19.
https://cds.cern.ch/record/1291633
[6]: GBT (No references yet for LPGBT):
GBT manual:
https://espace.cern.ch/GBT-Project/GBTX/Manuals/gbtxManual.pdf
ACES2014:
http://indico.cern.ch/event/287628/session/1/contribution/12/material/slides/1.pdf
TWEPP2009: OLD !
The GBT Project.
https://cds.cern.ch/record/1235836
TWEPP2014: Possible GBT paper in the pipeline.