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INTRODUCTION
1). Amplifier Circuit.
Before considering op-amps, let us first briefly go over some amplifier fundamentals.
An amplifier has an input port and an output port. (A port consists of two terminals, one
of which is usually connected to the ground node.) In a linear amplifier, the output signal
= A X input signal, where A is the amplification factor or “gain.” Depending on the
nature of the input and output signals, one can single out four general types of amplifier
gain: voltage gain (voltage out / voltage in), current gain (current out / current in),
transresistance (voltage out / current in) and transconductance (current out / voltage in).
The introduction will be limited to the voltage/voltage type of amplifier, since most opamps are of this type.
The circuit model of a typical amplifier is shown in Picture 1 (center dashed box, with
an input port and an output port). The input port plays a passive role, producing no
voltage of its own, and is modeled by a resistive element Ri called the input resistance.
The output port is modeled by a dependent voltage source AVi in series with the output
resistance R0, where Vi is the potential difference between the input port terminals.
Picture 1 shows a complete amplifier circuit, which consists of an input voltage source Vs
in series with the source resistance Rs, and an output “load” resistance RL. From this
figure, it can be seen that we have voltage-divider circuits at both the input port and the
output port of the amplifier. In principle, this requires us to re-calculate Vi and V0
whenever a different source and/or load is used:
 Ri
Vi  
 Rs  Ri

Vs

 RL 
 AVi
Vo  
 Ro  RL 
3
(1)
(2)
V0
output port
Ri
Vi
input port
+
-
+
R0
+
-
RL
+
RS
Vs
Source
-
-
Amplifier
Load
Picture 1. Circuit model of a typical amplifier circuit
2). The Operational Amplifier: Ideal Op-Amp Model
The amplifier model shown in Picture 1 is redrawn in Picture 2 showing the standard
op-amp notation. An op-amp is a “differential to single-ended” amplifier, i.e. it amplifies
the voltage difference Vp – Vn = Vi at the input port and produces a voltage VO at the
output port that is referenced to the ground node of the circuit in which the op-amp is
used.
jp
+
Vp
-
+
Vi
Ri
+
Vp
-
+
-
RO
AVi
+
Vn
-
Vi
+
VO
-
+
-
AVi
+
Vn
-
jn
Picture 2. Standard op-amp
Picture 3. Ideal op-amp
4
+
VO
-
The ideal op-amp model was derived to simplify circuit analysis and is commonly
used by engineers for first-order approximation calculations. The ideal model makes
three simplifying assumptions:
Gain is infinite: A = 
Input resistance is infinite: Ri = 
Output resistance is zero: RO= 0

(3)

(5)
Applying these assumptions to the standard op-amp model results in the ideal op-amp
model shown in Figure 3. Because Ri = and the voltage difference Vp – Vn = Vi at the
input port is finite, the input currents are zero for an ideal op-amp:
in = ip = 0
(6)
Hence there is no loading effect at the input port of an ideal op-amp:
Vi = Vs
(7)
In addition, because RO = 0, there is no loading effect at the output port of an ideal opamp:
VO = A Vi
(8)
Finally, because A = and VO must be finite, Vi = Vp – Vn = 0, or
Vp = Vn
(9)
Note: Although Equations 3-5 constitute the ideal op-amp assumptions, Equations 6 and
9 are used most often in solving op-amp circuits.
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3. Connections of the OP AMP (OP05)
Null offset- 1
8
NC
Vn- 2
-
7
+15V
Vp- 3
+
6
VO
5
Null offset
–15V - 4
Picture 4. OP05 Connections
Study the chip layout of Picture 4. The standard procedure on DIP (dual in-line
package) "chips" is to identify pin 1 with a notch in the end of the chip package. The
notch always separates pin 1 from the last pin on the chip. In the case of the OP05, the
notch is between pins 1 and 8.
Pin 2 is the inverting input, Vn. Pin 3 is the non-inverting input, Vp. The amplifier output,
VO is at pin 6. These three pins are the three terminals that normally appear in an OP
AMP circuit schematic diagram. Even though the ± 15V connections must be completed
for the OP AMP to work, they usually are omitted from the circuit schematic to improve
clarity.
The null offset pins (1 and 5) provide a way to eliminate any "offset" in the output
voltage of the amplifier. The offset voltage is an artifact of the integrated circuit. The
offset voltage is additive with VO (pin 6 in this case), can be either positive or negative
and is normally less than 10 mV. Because the offset voltage is so small, in most cases we
can ignore the contribution offset voltage makes to VO.
Pin 8, labeled "NC", has no connection to the internal circuitry of the OP05, and is not
used.
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Exercise № 1.
Non-Inverting Amplifier.
1. What is a non-inverting amplifier? Give a quantitative and qualitative description,
general function and characteristics.
2. Build the scheme shown in the Picture 5. Measure frequency characteristics (Bode
diagram) and the gain A for a) RF/R3 = 1; b) RF/R3 = 10; c) RF/R3 = 100; d) RF/R3 =
1000. Make sure that your measurements are not limited by the limitations of the OpAmp. Introduce, if necessary, the voltage divider (section VD in the picture 5) to set input
voltages more accurate. What would be the gain for the “open-loop” circuit (no feed
back)? Compare measured characteristics to the calculated ones.
3. Measure the slew rate, i.e. the maximum slope dVout/dt the amplifier can deliver, with
the gain A equal to either 11 or 1. Use reasonably high input voltage Vin.
4. Measure the step response with gain A equal to 100 and 1000 for different amplitudes
of input voltage. What would be the result for the impulse response? Explain the results
using the Bode diagram.
VD
+
R1
RF
Vout
R3
R2
Vin
Picture 5. Non-inverting amplifier
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Exercise № 2.
The pole-zero compensation.
1. What is a pole-zero compensation? Give a quantitative description in terms of transfer
function (see picture 6).
2. Build the scheme shown in the picture 6. The section A is a low-pass filter linked with
a section B (a buffer) to decouple the part C (a compensating scheme) from part A.
Values of Rin, C, R1, C1, R2, C2 are offered to be chosen by students. It is suggested for
dstudents to use 50 k Ω potentiometers for R1 and R2.
3. Measure the impulse response at position I and II when the scheme is compensated.
4. Explain the role of the buffer. What would happen if it were absent?
C. Compensation Scheme
C2
A. Low-pass filter
Rin
C1
B. Buffer
R2
I
+
Vin
II
R1
+
Vout
C
I
II
Picture 6. The pole-zero compensation scheme
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