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DYNAMIC LOGIC Dynamic CMOS • In static circuits the output is connected to either GND or VDD via a low resistance path. – fan-in of n requires 2n (n N-type + n P-type) devices • Dynamic circuits use temporary storage of signal values on the capacitance of high impedance nodes. – requires on n + 2 (n+1 N-type + 1 P-type) transistors Dynamic Gate Clk Clk Mp off Mp on Out In1 In2 In3 CL PDN A C B Clk Me Clk Two phase operation Precharge (Clk = 0) Evaluate (Clk = 1) 1 Out ((AB)+C) off Me on Conditions on Output • Once the output of a dynamic gate is discharged, it cannot be charged again until the next precharge operation. • Inputs to the gate can make at most one transition during evaluation. • Output can be in the high impedance state during and after evaluation (PDN off), state is stored on CL Properties of Dynamic Gates • Logic function is implemented by the PDN only – number of transistors is N + 2 (versus 2N for static complementary CMOS) • Full swing outputs (VOL = GND and VOH = VDD) • Non-ratioed - sizing of the devices does not affect the logic levels • Faster switching speeds – reduced load capacitance due to lower input capacitance (Cin) – reduced load capacitance due to smaller output loading (Cout) – no Isc, so all the current provided by PDN goes into discharging CL Properties of Dynamic Gates • Overall power dissipation usually higher than static CMOS – no static current path ever exists between VDD and GND (including Psc) – no glitching – higher transition probabilities – extra load on Clk • PDN starts to work as soon as the input signals exceed VTn, so VM, VIH and VIL equal to VTn – low noise margin (NML) • Needs a precharge/evaluate clock Issues in Dynamic Design 1: Charge Leakage CLK Clk Mp Out CL A Clk Me Evaluate VOut Precharge Leakage sources Leakage is dominated by the subthreshold current Solution to Charge Leakage Keeper Clk Mp A Mkp CL Out B Clk Me Same approach as level restorer for pass-transistor logic Issues in Dynamic Design 2: Charge Sharing Clk Mp Out A CL B=0 Clk CA Me CB Charge stored originally on CL is redistributed (shared) over CL and CA leading to reduced robustness Charge Sharing Example Clk Ca=15fF B Cc=15fF A A B B C C Clk Out CL=50fF !B Cb=15fF Cd=10fF Charge Sharing Assume that initial voltage Vx=0 and Vout=VDD VDD case 1) if V out < VTn VDD Mp Clk Mp Out Out CL Ma A A CL Ma X X M B = 0 B = 0 Mb b Clk Me Me C Caa Cb Cb Vx increases up to VDD-VTn when Ca is small comparing to CL C L VDD = C L Vout t + Ca VDD – V Tn V X or Ca V out = Vout t – V DD = – -------- V DD – V Tn V X CL case 2) if V out > VTn Ca --------------------- Vout = –V DD C + C a L as CL VDD=CL VOUT + Ca VOUT VOUT = VDD CL / (CL+Ca) Vx increases less up to VOUT when Ca is larger Solution to Charge Redistribution Clk Mp Mkp Clk Out A B Clk Me Precharge internal nodes using a clock-driven transistor (at the cost of increased area and power) Issues in Dynamic Design 3: Backgate Coupling Clk Mp A=0 Out1 =1 CL1 Out2 CL2 B=0 Clk Me Dynamic NAND Static NAND When In goes up from 0 to VDD, output of static NAND gate (Out2) goes down from VDD to 0 and pulls down Out1 through the capacitive coupling In Backgate Coupling Effect 3 2 Out1 1 Clk 0 In Out2 -1 0 2 Time, ns 4 6 Issues in Dynamic Design 4: Clock Feed Through Clk Mp A CL So voltage of Out can rise above VDD. B Clk Out Coupling between Out and Clk input of the precharge device due to the gate to drain capacitance. Me The fast rising (and falling edges) of the clock couple to Out. Clock Feed Through Clock feed through Clk Out 2.5 In1 In2 1.5 In3 In & Clk 0.5 In4 Clk Out -0.5 0 0.5 Time, ns More noise is generated as a result of clock coupling 1 Clock feed through Other Effects • Capacitive coupling between output wires pulls down prestored charges • Substrate coupling • Minority charge injection • Supply noise (negative ground bounce may discharge the output) Cascading Dynamic Gates V Clk Clk Mp Clk Mp Out1 In Clk Out2 In Out1 Me Clk Output signal loss VTn Me V Out2 t Only 0 1 transitions allowed at inputs! So do not connect these gates directly Domino Logic Clk In1 In2 In3 Clk Mp 11 10 PDN Me Out1 Clk Mp Mkp Out2 00 01 In4 In5 Clk PDN Me Here we guarantee proper 0 to 1 transitions between gates Why Domino? Clk Ini Inj Clk PDN Ini Inj PDN Ini Inj PDN Like falling dominos! Ini Inj PDN Properties of Domino Logic • Only non-inverting logic can be implemented • Very high speed – static inverter can be skewed, only L-H transition so make PMOS of inverter stronger – Input capacitance reduced so smaller logical effort Designing with Domino Logic VDD VDD VDD Clk Mp Clk Mp Out1 Mr Out2 In1 In2 In3 PDN Clk Me PDN In4 Clk Inputs = 0 during precharge Me Can be eliminated! but be aware of the short circuit path from delayed clock Footless Domino VDD Clk VDD Mp Clk Mp Out1 0 0 Clk Mp Out2 1 0 In1 1 VDD Outn 1 0 In2 1 0 In3 1 0 The first gate in the chain needs a foot switch Precharge is rippling – short-circuit current A solution is to delay the clock for each stage Inn 1 0 1 Differential (Dual Rail) Domino off Clk Out = AB 1 on Mp Mkp Mkp 0 Clk Mp 1 A !A 0 !B B Clk Me Solves the problem of non-inverting logic Out = AB np-CMOS Clk In1 In2 In3 Clk Mp PDN Me 11 10 Out1 Clk Me In4 In5 PUN Possible coupling in longer runs to dynamic node 00 01 Clk Mp Out2 (to PDN) Only 0 1 transitions allowed at inputs of PDN Only 1 0 transitions allowed at inputs of PUN NORA Logic Clk In1 In2 In3 Clk Mp 11 10 Out1 PDN Clk Me In4 In5 PUN use np-CMOS blocks 00 01 Clk Me to other PDN’s Mp Out2 (to PDN) to other PUN’s
