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CHARACTERIZATION OF PLANAR AND VERTICAL N-CHANNEL MOSFET
IN NANOMETER REGIME
IMA BINTI SULAIMAN
A project report submitted in partial fulfillment of the
requirements for the award of the degree of
Master of Engineering (Electrical – Electronics and Telecommunications)
Faculty of Electrical Engineering
Universiti Teknologi Malaysia
MAY 2007
iii
“To my beloved family and friends, thanks for being there, throughout this journey”
iv
ACKNOWLEDGEMENT
In the name of Allah, Most Merciful, Most Compassionate. It is by God’s
willing, I was able to complete this project within the time given. This project would
not have been possible without the support of many people. Firstly, I would like to
take this opportunity to thank my supervisor, Associate Professor Dr. Razali bin
Ismail for his guidance, patience and support for me throughout the period of time in
doing this project. My deepest gratitude also goes out to my examiners, Dr. Abu
Khari A’ain and Dr Abdul Manaf for their constructive comments and suggestions in
evaluating my project.
A very special thanks to my family and all my friends for always being there
for me and giving their love and support when I most needed it. Lastly I would like
to thank all staff and lecturers of Faculty of Electrical Engineering, Universiti
Teknologi Malaysia for their help and support.
v
ABSTRACT
In recent years, there is more and more design on MOSFET that has been
developed to fulfill the market need. This project focused on the comparison of
planar and vertical n-channel MOS transistor characteristic with effective channel
length of 100nm down to 50nm. Planar and vertical n-channel MOS transistors with
effective channel length ranged from 50nm to 100nm has been developed.
Simulation of the device design is done by using Silvaco-DevEdit. Short channel
effect (SCE) is investigated through out the device simulation. SCEs affect on
device and circuit performance in off-state leakage current and VT roll-off. At the
device simulation process, using Silvaco Atlas, the electrical parameter is extracted
to investigate the device characteristic. Several design analysis are performed to
investigate the effectiveness and robustness of the method in order to prevent the
varying threshold voltage or short channel effect of a MOSFET device. A single
channel vertical NMOS shows better VT roll-off and better subthreshold swing at
~85mV/decade. On the other hand, planar NMOS has lower threshold voltage value
which is suitable for low voltage devices. With these advantages from each NMOS
analysis, one can decide which device to use to achieve required specification for
specific usage in future.
vi
ABSTRAK
Satu kajian telah dijalankan untuk membandingkan ciri-ciri antara MOSFET
saluran-n jenis mendatar dan menegak. Setiap peranti mempunyai saluran efektif
sepanjang 50nm hingga 100nm telah dibangunkan.
Peranti telah direka
menggunakan Slvaco-DevEdit. Kesan kurang sempurna dalam rekaan MOSFET
seperti kesan saluran pendek telah dikaji. Kesan yang berlaku adalah seperti arus
bocor dan kejatuhan voltan ambang. Pada simulasi peranti, menggunakan SilvacoAtlas, parameter elektrikal telah diekstrak untuk megkaji ciri-ciri peranti. Beberapa
analisa peranti dilakukan untuk menyiasat keberkesanan kaedah yang telah
digunakan dalam mengurangkan perubahan voltan ambang atau kesan saluran
pendek
bagi
sesebuah
MOSFET.
NMOS
menegak
bersaluran
tunggal
memperlihatkan kejatuhan voltan ambang yang lebih baik dan ayunan sub-ambang
dalam lingkungan 85mV/dekad.
Manakala, NMOS mendatar memiliki voltan
ambang yang lebih rendah yang bersesuaian dengan peranti bervoltan rendah.
vii
TABLE OF CONTENT
CHAPTER
1
2
TITLE
PAGE
TITLE
i
DECLARATION
ii
DEDICATION
iii
ACKNOWLEDGEMENT
iv
ABSTRACT
v
ABSTRAK
vi
TABLE OF CONTENT
vii
LIST OF TABLES
x
LIST OF FIGURES
xi
LIST OF ABBREVIATION
xiv
LIST OF APPENDICES
xv
INTRODUCTION
1
1.1 Introduction
1
1.2 Objectives
4
1.3 Scope of Project
4
1.4 Project Plan
5
1.5 Organization of the Report
6
LITERATURE REVIEW
7
2.1 Introduction
7
viii
2.2 Planar MOSFET
2.2.1 Works on planar MOSFET
2.3 Vertical MOSFET
2.3.1 Vertical MOSFETs based on selective
8
9
13
15
epitaxy
2.3.2 Vertical MOSFETs with etched sidewalls
17
2.3.3 Works on vertical MOSFET
18
2.4 Characteristics of an NMOS transistor
22
2.5 Short channel effects
23
2.6 MOS device physics in short-channel regime
23
2.7 Threshold voltage
26
2.7.1 Threshold reduction
3
27
2.8 Leakage current
28
2.9 Subthreshold characteristic
30
2.10 VT roll-off
32
2.11 Summary
33
METHODOLOGY
34
3.1 Process simulation
34
3.2 Process development
36
3.2.1 Work area
36
3.2.2 Adding silicon base region
37
3.2.3 Creating gate oxide
39
3.2.4 Adding contacts for source/drain
41
3.2.5 Adding substrate contact
42
3.2.6 Polysilicon gate formation
43
3.2.7 Source/drain doping
45
3.2.8 Creating mesh
49
3.2.9 Final device
51
3.3 Device simulation
54
3.3.1 Output characteristic
55
3.3.3 Transfer characteristic
56
ix
4
3.4 Summary
56
EXPERIMENTAL RESULTS AND ANALYSIS
57
4.1 Results
57
4.1.1 Output characteristic
57
4.1.2 Transfer characteristic
59
4.1.3 Threshold voltage
60
4.1.4 Leakage current
61
4.1.5 Subthreshold slope
62
4.1.6 Drain saturation slope
63
4.2 Analysis
4.2.1 Varied gate oxide thickness
64
4.2.1.1 Threshold voltage
64
4.2.1.2 Subthreshold slope
65
4.2.1.3 Leakage current
66
4.2.1.4 Conclusion
67
4.2.2 Varied body doping concentration
5
64
68
4.2.2.1 Threshold voltage
68
4.2.2.2 Subthreshold slope
69
4.2.2.3 Leakage current
70
4.2.2.4 Conclusion
71
4.3 Summary
72
CONCLUSION AND FUTURE WORK
73
5.1 Conclusion
73
5.2 Suggestion for Future Works
74
REFERENCES
75
APPENDICES
78
x
LIST OF TABLES
TABLE NO
3.1
TITLE
Summary of NMOS process flow
PAGE
35
xi
LIST OF FIGURES
FIGURE NO
TITLE
PAGE
1.1
Moore’s Law on increasing performance
3
1.2
Moore’s Law on decreasing cost
3
2.1
Cross section of a planar NMOS.
8
2.2
Simulation structure of the symmetrical MOSFET
9
with design parameters
2.3
Simulation structure for the asymmetric MOSFET
10
2.4
Schematic images of the device-design concepts for
11
the lateral S/D-junction control techniques. (a)
Conventional. (b) Thick offset spacer. (c) Notch,
offset spacer and reverse S/D
2.5
Schematic device cross section in the simulations: (a)
12
the asymmetric Schottky barrier MOSFET (ASB
structure); (b) the conventional Schottky Barrier
MOSFET (CSB structure)
2.6
Vertical MOSFET
13
2.7
Schematic cross section of VFET
15
2.8
Schematic cross section of VOXFET
16
2.9
Cross-section showing the concept of dielectric pocket
17
in a vertical MOSFET
2.10
Schematic cross sections of vertical nMOSFETs (a)
18
with deep drain junction and (b) with shallow drain
junction.
2.11
Structure of bVMOS
19
xii
2.12
Schematic cross section of a surround-gate vertical
21
MOSFET fabricated with the FILOX process
2.13
Transfer characteristic of an NMOS transistor
22
2.14
Drain current family of characteristic of an NMOS
22
transistor
2.15
Depletion region of an NMOS
27
2.16
Sources of current leakage in an n-channel MOSFET
29
2.17
(a) ID-VG curve and (b) inverse ID-VG that shows
31
subthreshold slope, S
3.1
Flow of process simulation
35
3.2
Work area’s depth and length values for (a) planar
36
NMOS and (b) vertical NMOS
3.3
Workspace for planar NMOS
37
3.4
Silicon region for (a) planar NMOS and (b) vertical
38
NMOS
3.5
Base impurity, boron, added to the silicon
39
3.6
SiO2 layer for (a) planar NMOS and (b) vertical
40
NMOS
3.7
Contacts for (a) planar NMOS and (b) vertical NMOS
41-42
3.8
Substrate electrode panel
43
3.9
Polysilicon gate region for (a) planar NMOS and (b)
44
vertical NMOS
3.10
Adding impurities to gate to create highly doped
45
region
3.11
Impurity added to create source for (a) planar NMOS
46
and (b) vertical NMOS
3.12
Impurity specification to create drain for (a) planar
47
NMOS and (b) vertical NMOS
3.13
Net doping for (a) planar NMOS and (b) vertical
48
NMOS
3.14
(a) Mesh parameters and (b) refinement on mesh for
49
planar and vertical NMOS
3.15
Mesh on (a) planar NMOS and (b) vertical NMOS
50
xiii
3.16
Completed planar NMOS
51
3.17
Completed (a) single channel vertical NMOS and (b)
52
full vertical NMOS
3.18
(a) Planar NMOS and (b) vertical NMOS with
53
effective channel length of 100nm
4.1
ID-VDS curve for planar and single channel vertical
58
NMOS
4.2
ID-VGS curve for planar and single channel vertical
59
NMOS
4.3
Threshold voltage for planar and single channel
60
vertical NMOS
4.4
Leakage current for planar and single channel vertical
61
NMOS
4.5
Subthreshold slope for planar and single channel
62
vertical NMOS
4.6
Drain saturation slope for planar and single channel
63
vertical NMOS
4.7
Threshold voltage with varied gate oxide thickness for
65
planar and vertical NMOS
4.8
Subthreshold slope with varied gate oxide thickness
66
for planar and vertical NMOS
4.9
Leakage current with varied gate oxide thickness for
67
planar and vertical NMOS
4.10
Threshold voltage with varied body doping
69
concentration for planar and vertical NMOS
4.11
Subthreshold slope with varied body doping
70
concentration for planar and vertical NMOS
4.12
Leakage current with varied body doping
concentration for planar and vertical NMOS
71
xiv
LIST OF ABBREVIATION
ASB
-
Asymmetric Schottky barrier source/drain MOSFET
BTBT
-
Band-to-band tunneling
bVMOS
-
Vertical MOSFET with internal block layer
CMOS
-
Complementary MOS
CSB
-
Conventional Schottky Barrier MOSFET
DIBL
-
Drain induced barrier lowering
DITM
-
Drain-induced tunneling modulation
DOT
-
Drain on top
DT
-
Direct-tunneling
FILOX
-
Fillet local oxidation
GIDL
-
Gate-induced drain leakage
MOSFET
-
Metal-oxide semiconductor filed effect transistor
NMOS
-
N-channel MOSFET
PECVD
-
Plasma-enhanced chemical vapor deposition
PMOS
-
P-channel MOSFET
SCE
-
Short channel effect
SEG
-
Selective epitaxial growth
SOI
-
Silicon on insulator
SOT
-
Source on top
xv
LIST OF APPENDICES
APPENDIX
TITLE
PAGE
A
Family of ID-VDS curve program
78
B
ID-VGS at VDS=0.1V program
80
C
Extract results from simulation
82
CHAPTER 1
INTRODUCTION
This project uses Silvaco DevEdit and Atlas as a primary fabrication process
and simulation tool. First part of the report will elaborate more on the project
background and fabrication process will be discussed regarding the development of
planar and vertical n-channel MOSFET. This chapter also mention on the objective
and scope of the project.
1.1
Introduction
Future high performance devices for higher speed and lower power
consumption would require active device dimensions in the sub-100 nm regime.
Chip complexity, chip performance, feature size, and the numbers of transistors
produced each year are a few of the parameters of the semiconductor industry that
have changed exponentially over the last 50 years. The size reduction is in great
improvement to MOSFET operation until the late 1990s with no deleterious
consequences. The difficulties with decreasing the size of the MOSFET have always
2
been associated with the semiconductor device fabrication process. A steady path of
constantly shrinking device geometries and increasing chip size has been followed by
the integrated circuit industry for more than 30 years. This strategy has been driven
by the increased performance that the smaller devices make possible and the
increased functionality that larger chips provide.
Moore, one of the founders of Intel, observed in an article in the April 19,
1965 issue of Electronics magazine that innovations in technology would allow a
doubling of the number of transistors in a given space every year (in an update article
in 1975, Moore adjusted the rate to every two years to account for the growing
complexity of chips), and that the speed of those transistors would increase. What is
less well-known is that Moore also stated that manufacturing costs would
dramatically drop as the technology advanced. Moore's prediction, now popularly
known as Moore's Law, had some startling implications, predicting that computing
technology would increase in value at the same time it would actually decrease in
cost. This was an unusual idea at the time since, in a typical industry, building a
faster, better widget with twice the functionality also usually means doubling the
widget’s cost. However, in the case of solid-state electronics, the opposite is true:
Each time transistor size shrinks, integrated circuits (ICs) become cheaper and
perform better.
There are two main reasons that smaller MOSFETs are desirable in today’s
world. First, smaller MOSFETs allow more current to pass and second, it has
smaller gates, thus lower capacitance. These two factors bring to lower switching
times and higher processing speeds. Logic gates incorporating smaller MOSFETs
have less charge to move as smaller MOSFETs have lower gate capacitance and the
amount of charge on a gate is proportional to its capacitance. There is another reason
for scaled down MOSFETs, which is smaller MOSFETS can be packed more
densely, resulting smaller chips and chips with more computing power in an area.
3
Figure1.1: Moore’s Law on increasing performance
Figure 1.2: Moore’s Law on decreasing cost
4
1.2
Objectives
The main objective of the project is to develop a planar and vertical n-channel
MOSFET (NMOS) with a range of effective channel length of 100nm down to 50
nm. Many design aspects has to be considered when the MOSFET device is scaled
down into deep submicron regime. Short channel effects will appear whenever the
MOSFET device is scaled down and gate oxide has to be thin enough to increase the
device performance.
The objectives of the study are listed as follows:
1. To develop planar and vertical n-channel MOSFET using TCAD.
2. To study the characteristic and to compare the performance between
planar and vertical MOSFET.
3. To analyze planar and vertical NMOS in nanometer regime
1.3
Scope of Project
Basic design structure has been implemented in designing the device in this
project. Generally, this project consists of two parts, which are the fabrication and
the simulation process.
1)
Process simulation
The process used to fabricate the planar and vertical NMOS transistor will be
simulated using Silvaco-DevEdit. It is used to create the device structure, adding
dopant, defining electrodes and creating the mesh.
It uses an advanced mesh
5
refinement algorithm that produces a geometry based initial mesh with further
adoption based on the impurity profiles.
2)
Device simulation
The result from the process simulation is used as the input for the device
simulation process using Silvaco-Atlas. From here, the device characteristics can be
examined. It is an easier way to study the effects of process parameters on the device
performance and furthermore we can optimize the device structure and fabrication
process.
For this project, the device characterization will concentrate on short channel
effect and extracted values such as threshold voltage, leakage current, subthreshold
slope and drain saturation slope.
1.4
Project Plan
This project will be carried out in two semesters. The first part of the project
is done in the first semester where the understandings of literature review and
methodology that will be used are done. Gathering information about the study is a
crucial part of this part since thorough understanding is needed in order to really
implement the proposed approach. Most of the information is obtained from articles
and journal that can be downloaded from the Institute of Electrical and Electronic
Engineering (IEEE) website and Engineering Village 2 website. The second part of
the project is to design and simulate the devices and analyze the results.
6
1.5
Organization of the Report
This report consists of four chapters which are the introduction, literature
review, methodology and result. The first chapter presents introduction to the study
and why this study is being conducted. It also gives the objectives and scope of the
study. Chapter 2 provides reviews on planar and vertical MOSFET. Chapter 3
discusses on the methodology used to carry out the study systematically. While in
Chapter 4, it discusses the results from the simulation using Silvaco-Atlas. Chapter 5
is the conclusion and suggestion for future works.
CHAPTER 2
LITERATURE REVIEW
This chapter will discuss briefly about the theory and research from other
researchers related to the project. The issue of short channel effect is discussed and
several solutions involving advanced fabrication technique are performed.
2.1
Introduction
Over the past 20 years, the channel length of MOS transistors halved at
intervals of approximately every two or three years, which has led to a virtuous circle
of increasing packing density resulting more complex electronic products, increasing
performance with higher clock frequencies and decreasing costs per unit silicon area.
With this, throughout the year, advanced fabrication technique has been revealed and
also several designs were created by researchers to overcome these challenges. For
this project, device used are planar and vertical NMOS. As in the market today, we
can see the demand of cheaper chips, using lower voltage and faster transistor
response trigger the multiple device design to use to fulfill nowadays request. Each
8
design device has its pros and cons, but each of them is unique enough to suppress
short channel effect problems and optimizing the device performance.
2.2
Planar MOSFET
Over the years, planar MOS transistor has been the pioneer of a transistor. It
has been used for decades until scaling has reached it limits, and need to find other
structural design to meet with the latest technology demand. In longer channel
region (above 100µm) it is easier to fabricate the planar MOSFET. But when it
comes to nanometer regime, several advanced technique and also other device design
is needed to compress the short channel effect.
Basically, the planar MOS is a simple and straight forward design. The
channel is in horizontal condition as the drain and source is on the surface of the
substrate. The gate is on the substrate with a thin oxide layer in between, and
represents the channel length physically.
Figure2.1: Cross section of a planar NMOS.
9
2.2.1
Works on planar MOSFET
A novel asymmetric MOSFET structure is proposed by Tsutomo et al (2006),
which
provides
an
excellent
tradeoff
between
current
drivability
and
manufacturability for planar MOSFET technology. To achieve this, the "corner
effect" is utilized to suppress short channel effects, while degradation in current
drivability caused by the corner effect is avoided by an asymmetric design. Using
simulation, it is shown that this structure enlarges the tolerance for the junction depth
of source/drain extensions by a factor of three, without sacrificing current drivability,
compared to the optimal symmetric structure also found in this work.
This
asymmetric structure is a superior design strategy for planar MOSFETs and can be
considered as one of the most promising candidates for 32nm-node MOSFETs.
Figure 2.2: Simulation structure of the symmetrical MOSFET with design
parameters.
10
Figure 2.3: Simulation structure for the asymmetric MOSFET
For symmetric planar MOSFETs with extremely shallow junctions, junction
depth tolerance must be reduced to about ±1nm in order to control VT and maintain
sufficient current drivability. The proposed asymmetric structure enables use of the
potential barrier at the gate corner for SCE suppression without reducing current
drivability, and, in addition, increases junction depth tolerance by a factor of three.
This structure is therefore a promising candidate for 32nm-node MOSFETs.
Wakabayashi et al (2006) has done research on sub-10-nm planar bulk
CMOS devices and were demonstrated by a lateral source/drain (S/D) junction
control, which consists of the notched gate electrode, shallow S/D extensions, and
steep halo in a reverse-order S/D formation.
Furthermore, the transport properties
were also evaluated by using those sub-10-nm planar bulk MOSFETs. The directtunneling currents between the S/D regions, with not only the gate length but also the
“drain-induced tunneling modulation (DITM)” effects, are clearly observed for the
sub-10-nm CMOS devices at low temperature. Moreover, a quantum mechanical
simulation reveals that the tunneling currents increase with the increase in the
temperatures and gate voltages, resulting in a certain amount of contribution to the
subthreshold current even at 300 K. Therefore, it is strongly required that the supply
11
voltage should be reduced to suppress the DITM effects for the sub-10-nm CMOS
devices even under the room-temperature operations.
Figure 2.4: Schematic images of the device-design concepts for the lateral S/Djunction control techniques. (a) Conventional. (b) Thick offset spacer. (c) Notch,
offset spacer and reverse S/D.
The 5-nm planar bulk CMOS devices were clearly demonstrated for the 45nm-node CMOS devices and rather beyond by the lateral junction control using the
precisely controlled gate electrode, shallow SDE, and steep halo.
Good cutoff
characteristics were observed for the 5-nm n and pMOSFETs at 0.4 V. Furthermore,
the transport properties of the sub-10-nm CMOS devices had been discussed in terms
of the QM effects, such as the source-to-drain direct-tunneling (DT) currents. In
order to improve the S/D DT currents in the planarbulk MOSFETs, it is newly
required to reduce the supply voltage even at 300 K from the measured data and
simulation results. Scaling the supply voltage simultaneously improves the energydelay products drastically. Any new compact model would be expected to enable to
describe such a phenomenon in some way, in order to push further the device
scaling.
Lei Sun et al (2006) has done research on an n-channel planar asymmetric
Schottky barrier source/drain MOSFET (ASB), in which the source-side Schottky
12
barrier is higher (0.9 eV, for PtSi) and the drain-side one is lower (0.2 eV, for ErSi),
has been investigated. A fabrication proposal for nano-scale ASB devices has been
put forward based on the spacer technique.
This method is compatible with
conventional CMOS processing. The characteristics of a 28 nm gate-length ASB
device have been simulated with a numerical simulator, and the data are compared
with the simulated results of corresponding conventional Schottky barrier
MOSFETs.
Comparison results have demonstrated that the ASB structure can
efficiently suppress the leakage current and the Ion/Ioff ratio can be much improved.
(a)
(b)
Figure 2.5: Schematic device cross section in the simulations: (a) the asymmetric
Schottky barrier MOSFET (ASB structure); (b) the conventional Schottky Barrier
MOSFET (CSB structure).
An optimized fabrication method has been proposed for the realization of the
ASB-MOSFET structures. This method based on spacer technology can be applied
to the nano-scale MOSFET structures. With the above method, the advantages of the
metal-gate and high-k dielectric also remain. The simulation results have shown that
the leakage current of the CSBMOSFET with the lower source/drain barrier height is
13
mainly determined by the electron component, and that of the CSBMOSFET with the
higher source/drain barrier is mainly due to the hole component. In the ASBMOSFET, the higher source barrier blocks the electron thermal emission, and the
lower drain barrier prevents the hole injection in the subthreshold region. Thus, the
leakage current of the ASB structure is reduced to a certain degree, and the Ion/Ioff
performance is optimized.
2.3
Vertical MOSFET
The possible benefits of making transistors on the sidewalls of trenches or
pillars have been recognized for more than three decades. An alternative method of
fabricating short channel MOS transistor is so-called Vertical MOSFET. In these
devices, the channel is perpendicular to the wafer surface instead of in the plane of
the surface.
Figure 2.6: Vertical MOSFET.
Vertical MOSFET’s have three main advantages, which first; the channel
length of the vertical MOS transistor is not defined by lithography. This means no
requirements for post-optical lithography techniques such as x-ray, extreme ultra-
14
violet, electron projection lithography, ion projection lithography or direct write ebeam which are possibly prohibitively expensive. Second, vertical MOS transistors
are easily made with both front gate and back gate. Using this technology doubles
the channel width per transistor area. Combined with easier design rules, this leads
to an increase of packing density of at least a factor of four as compared to horizontal
transistors.
One step further, is the use of very narrow pillars with the gate
surrounding the entire pillar. This way, fully depleted transistors can be produced
which have all the advantages of SOI transistors. Third advantage of the vertical
MOSFET is the possibility to prevent short channel effects from dominating the
transistor by adding processes that are not easily realised in horizontal transistors,
such as a polysilicon (or polySiGe) source to reduce parasitic bipolar effects or a
dielectric pocket to reduce drain induced barrier lowering (DIBL).
The normal planar MOSFET has a source and a drain area divided by the
channel area. Its contacts are symmetric. Turning the transistor through 90◦ in the
vertical direction, it is difficult to maintain that symmetry: The source and drain con
tact are now at the top of the substrate contact of the silicon mesa. The layout of the
leads and the contact areas, and hence the series resistances, are different. Therefore
there is a difference in device performance, depending on whether the source is at the
top contact (source on top: SOT) or drain (drain on top: DOT). This has to be taken
into account in developing the circuit layout.
One of the key issues is how to create the vertical interface with which the
channel is controlled, and the doping sequence to form the source, channel and drain
regions. In principle there are two different methods. The first one is to grow a layer
system, which is etched anisotropically. The sidewall of the mesas is used as the
active area. The other method is to use selective epitaxy to grow the required layer
sequence. The interface between the epitaxial layer and the mask for epitaxy is used
as the active area. It is doubtful whether the quality of the etched interface is
sufficient for proper device performance, because the etched surface is damaged by
the reactive ion etching. The second method is considered to produce better channel
characteristics, because the channel area is not exposed to the etching plasma and
15
hence should not be damaged. However, it is essential that the sidewall of the mask
for epitaxy should be smooth, because it is transferred to the sidewall, and hence to
the channel interface, of the epitaxial layer.
2.3.1
Vertical MOSFETs based on selective epitaxy
Several concepts have been developed in which the channel surface is defined
by selective epitaxial growth (SEG).
During SEG on a (100) substrate, a
crystallographic plane with different orientation occurs at the rim of the mask. These
facets have a different growth rate to the {100} facet and are energetically favorable.
The facets lead to a thinner epitaxial layer at the rim of the mask, resulting in a
shorter channel length.
Figure 2.7: Schematic cross section of VFET
The so-called VFET concept, an oxide layer of 700 nm thickness (Figure
2.3), serving as a mask for SEG, is deposited by plasma-enhanced chemical vapor
deposition (PECVD) on a buried layer, which enables substrate contact. Windows
with vertical sidewalls are etched into this oxide layer using reactive ion etching and
a three-layer resist. Epitaxial growth then follows. The epitaxial layer is doped in
situ, so that the source and drain and channel area are defined together.
The
16
epitaxially grown mesa is laid open by a wet chemical etching step, then the gate
oxide is grown by thermal oxidation. n-doped polysilicon is then used as the gate
electrode and an insulating SiO2 layer is deposited.
Figure 2.8: Schematic cross section of VOXFET
In the second concept, the so-called VOXFET concept (Figure 2.4), the mask
for SEG is not a single oxide layer deposited after implementation of the buried
layer, but rather a layer sequence of SiO2/n-polySi/SiO2 is deposited. The windows
with vertical sidewalls are etched into this layer sequence. The SiO2 gate oxide layer
and a Si3N4 sacrificial layer are deposited into those windows. After removing these
two layers on the horizontal areas by anisotropic reactive ion etching, the Si3N4
spacer at the sidewall is removed wet chemically by H3PO4. Thus only the thin
oxide layer at the side walls remains as a gate oxide. The epitaxial layer is grown
into the windows prepared in this way. The n-polysilicon within the mask stack
serves as the gate metal, and hence the formation sequence of the gate stack in this
transistor proceeds in the opposite sequence to that normally applied. The gate
electrode is deposited first, the gate oxide is deposited next and finally the channel
forming silicon is grown.
17
2.3.2
Vertical MOSFETs with etched sidewalls
One approach for creating etched sidewalls for vertical MOSFETs is to
achieve the doping profile by epitaxial growth. The active area of the transistor is
defined by the thickness of the corresponding layer. A similar approach was chosen
by Donaghy et al (2004), but here it is proposed to integrate a dielectric pocket into
the drain of the transistor. Therefore the channel region is implanted for PMOS and
NMOS, respectively. Afterwards a SiO2 layer is grown to form the dielectric pocket
layer. Polysilicon is deposited on top to form an extrinsic drain. Subsequently, the
layer stack is etched to form the mesa. The dielectric pocket layer is etched back to
enable SEG to form the contact between the silicon body and the polysilicon drain.
Figure 2.5 shows the cross-section view of the schematic transistor. The dielectric
pocket serves several purposes: First, it prevents the dopant from diffusing out and
attenuating bulk punch-through effects. Second, the electrostatics of the drain region
is influenced so that charge sharing is reduced, and, third, the parasitic bipolar
transistor associated with source/body and drain regions is suppressed.
Figure 2.9: Cross-section showing the concept of dielectric pocket in a vertical
MOSFET.
18
2.3.3
Works on vertical MOSFET
Gili et al (2006) has done a research on a simple process for the fabrication of
shallow drain junctions on pillar sidewalls in sub-100-nm vertical MOSFETs. The
key feature of this process is the creation of a polysilicon spacer around the perimeter
of the pillar to connect the channel to a polysilicon drain contact. The depth of the
junction on the pillar sidewall is primarily determined by the thickness of the
polysilicon spacer. This process is CMOS compatible and, hence, facilitates the
integration of a sub-100-nm vertical MOSFET in a planar CMOS technology using
mature lithography.
The fabricated transistors have a subthreshold slope of
95mV/decade (at VDS = 1 V) and a drain-induced barrier lowering of 0.12 V.
(a)
(b)
Figure 2.10: Schematic cross sections of vertical nMOSFETs (a) with deep drain
junction and (b) with shallow drain junction.
Vertical n-channel MOSFETs featuring shallow drain junctions on the pillar
sidewall were fabricated using a novel twostep pillar etch process. The key feature
of this process is the deposition of a polysilicon spacer to connect the channel to a
polysilicon drain contact around the perimeter of the pillar. This simple approach
involves only standard CMOS fabrication process steps and does not require
epitaxial growth. Moreover, it can be implemented without challenging lithography
and, thus, allows sub-100-nm vertical MOSFETs to be integrated in a mature CMOS
technology with relaxed lithography rules.
19
Jyi-Tsong Lin et al (2006) has done work on a vertical n-channel
enhancement type MOSFET with internal block layer (bVMOS) investigated
theoretically. In the proposed structure, the internal block layer comprises a buried
block layer and a sidewall block layer. They also test three blocking materials (ex.
doped Si, nitride and oxide) for performance comparisons. That is, the p-n junction
region between the substrate and drain is isolated by the buried block layer thereby
reducing the p-n junction leakage current and the parasitic capacitance. Similarly,
the electrical field between the body and drain is blocked or shielded by the sidewall
block layer; hence the intolerable ultra-short-channel effects, such as drain induced
barrier lowering (DIBL), hot-carrier effect, source/drain (S/D) punchthrough, and
charge-sharing effect, are ameliorated tellingly. Owing to the suppression of the
ultra-short-channel effects, excellent subthreshold swing is also successfully
achieved by the nano-scale regime. Moreover, the proposed vertical structure has a
path between the body and the substrate, the generated hole current by impact
ionization and generated heat in channel can be banished from this pass way. Thus,
both the floating-body effects and the self-heating effects are avoided synchronously.
Figure 2.11: Structure of bVMOS
This is the first to present a new vertical MOSFET with internal block layer
(bVMOS) for reduced p-n junction leakage current and suppressed ultra-shortchannel
effects. The internal block layer comprises a buried blocking layer that can eliminate
the most parts of the p-n junction between the body and the drain thus reducing the
junction leakage current and parasitic capacitances. In addition, the sidewall block
layer can isolate the electrical field between the body and drain. Therefore, it can
20
improve the undesirable ultra-short-channel phenomena in depth. Moreover, the
floating-body effects and the self-heating effects are also avoided in our proposed
structures due to the body is tied to the substrate. If thick enough buried block layer
and sidewall block layer are applied, bVMOS is believed to show excellent electrical
performances. Besides, high-k dielectric materials, advanced gate engineering and
re-crystallization techniques can be simultaneously introduced to bVMOS so that the
on-state drain current can thus be further improved. Thus, the advantages of bVMOS
provide stimulation to further experimental exploration.
Gili et al (2006) has done an investigation on the effect of the asymmetric
source and drain geometries of surround-gate vertical MOSFETs on the drain
leakage currents in the OFF-state region of operation.
Measurements of gate-
induced drain leakage (GIDL) and body leakage are carried out as a function of
temperature for transistors connected in the drain-on-top and drain-on-bottom
configurations. Asymmetric leakage currents are seen when the source and drain
terminals are interchanged, with the GIDL being higher in the drain-on-bottom
configuration and the body leakage being higher in the drain-on-top configuration.
Band-to-band tunneling is identified as the dominant leakage mechanism for both the
GIDL and body leakage from electrical measurements at temperatures ranging from
−50 to 200 ◦C. The asymmetric body leakage is explained by a difference in body
doping concentration at the top and bottom drain–body junctions due to the use of a
p-well ion implantation. The asymmetric GIDL is explained by the difference in gate
oxide thickness on the vertical <110> pillar sidewalls and the horizontal <100>
wafer surface.
21
Figure 2.12: Schematic cross section of a surround-gate vertical MOSFET fabricated
with the FILOX process
The asymmetry is observed in the transfer characteristics of the devices when
the source and the drain are interchanged, with GIDL being higher in the drain-onbottom configuration and body leakage being higher in the drain-ontop
configuration.
The temperature dependence of the leakage currents has been
analyzed, and the band-to-band tunneling of electrons from the valence band to the
conduction band has been identified as the dominant leakage mechanism.
The
asymmetric body leakage is process induced and arises from a slightly larger body
doping concentration at the top of the pillar than at the bottom due to the use of a
well implant for the body doping. On the other hand, the asymmetric GIDL is
explained by a thicker gate oxide on the vertical <110> pillar sidewall than on the
horizontal <100> wafer surface. The thinner gate oxide at the bottom of the pillar
increases the electric field and enhances the band-to-band tunneling, which is the
cause of the GIDL. The good agreement between the simulated and measured
leakage characteristics of the devices is a strong indication that the FILOX process
has a negligible impact on the asymmetric drain leakage currents.
22
2.4
Characteristics of an NMOS transistor
The transfer characteristic of an n-channel enhancement-mode MOSFET
(NMOS) is given in Figure 2.6 where VT its threshold voltage.
Figure 2.13: Transfer characteristic of an NMOS transistor
A typical family of drain current characteristics is given in Figure 2.7 for an
NMOS transistor. Note that the drain current is almost zero for VGS ≤ VT where VT is
about 1.4 V.
Figure 2.14: Drain current family of characteristic of an NMOS transistor
23
2.5
Short channel effects
The term of short-channel effects are referring to secondary effects such as
mobility degradation and velocity saturation, which these both are also occur in long
channel devices. The short-channel effects are recognized to two physical
phenomena:
i)
The limitation imposed on electron drift characteristics in the channel,
ii)
The modification if the threshold voltage due to the shortening
channel length.
In particular, four different short-channel effects can be distinguished:
2.6
i)
Drain-induced barrier lowering
ii)
Punch-through
iii)
Velocity saturation
iv)
Hot electrons
MOS device physics in short-channel regime
The continuing drive to shrink device geometries has resulted in devices so
small that various high-field effects become prominent at moderate voltages. The
primary high-field effect is that of velocity saturation.
Because of scattering by high-energy phonons, carrier velocities eventually
cease to increase with increasing electric field. In silicon, as the electric field
approaches about 106V/m, the electron drift velocity displays a progressively
weakening dependence on the field strength and eventually saturates at a value of
about 105m/s.
24
In deriving equations for long-channel devices, the saturation drain current is
assumed to correspond to the value of current at which the channel pinches off. In
short-channel devices, the current saturates when the carrier velocity does.
To accommodate velocity saturation, begin with the long-channel equation
for drain current in saturation:
I =
D
µ n⋅ C
ox
2
⋅
W
L
(
⋅ V
⋅ −V
GS
T
)2
(2.1)
which may be re-written as
I =
D
µ n⋅ C
ox
2
⋅
W
L
(
⋅ V
GS
)
⋅ −V ⋅ V
T
DSAT1
(2.2)
where the long-channel VDSAT is denoted VDSAT1 and is (VGS-VT).
As stated earlier, the drain current saturates when the velocity does, and the
velocity saturates at smaller voltages as the device gets shorter. Hence, we expect
VDSAT to diminish with channel length.
It may be shown that VDSAT may be expressed more generally by the
following approximation:
25
V
DSAT
=
(VGS − VT )⋅(LESAT)
(VGS − VT ) + (LESAT)
(2.3)
(VGS − VT)⋅ (LESAT)
(VGS − VT ) + (LESAT)
(2.4)
so that
I =
D
µ n⋅ C
ox W
2
⋅
L
⋅
where ESAT is the field strength at which the carrier velocity has dropped to one-half
the value extrapolated from low-field mobility.
It should be clear from the foregoing equations that the prominence of “short
channel” effects depends on the ratio of (VGS–VT)/L to ESAT. If this ratio is small,
then the device still behaves as a long device; the actual channel length is irrelevant.
All that happens as the device shortens is that less (VGS–VT) (also called the “gate
overdrive”) is needed for the onset of these effects.
With the definition for ESAT, the drain current may be re-written as:
(
I = WC ⋅ V
D
ox
GS
− V ⋅ υ sat ⋅ 
T
)


SAT 
1+

V −V 
GS
T 

1
LE
(2.5)
A typical value for ESAT is about 4x106V/m. While it is somewhat processdependent, we will treat it as constant in all that follows.
26
For values of (VGS- VT)/L large compared with ESAT, the drain current
approaches the following limit:
I =
D
µ n⋅ C
ox
2
(
⋅W⋅ V
GS
)
− V ⋅E
T
SAT
(2.6)
That is, the drain current eventually ceases to depend on the channel length.
Furthermore, the relationship between drain current and gate-source voltage becomes
incrementally linear, rather than square-law.
2.7
Threshold voltage
The threshold voltage of a MOSFET is usually defined as the gate voltage
where a depletion region forms in the substrate (body) of the transistor. In an NMOS
the substrate of the transistor is composed of p-type silicon which has more
positively charged electron holes compared to electrons. When a voltage is applied
on the gate, an electric field causes the electrons in the substrate to become
concentrated at the region of the substrate nearest the gate causing the concentration
of electrons to be equal to that of the electron holes, creating a depletion region.
If the gate voltage is below the threshold voltage, the transistor is turned off
and ideally there is no current from the drain to the source of the transistor. If the
gate voltage is larger than the threshold voltage, the transistor is turned on, due to
there being more electrons than holes in the substrate near the gate creating a channel
where current can flow from drain to source.
inversion.
This situation is called strong
27
Figure 2.15: Depletion region of an NMOS
For an enhancement mode, n-channel MOSFET the threshold voltage is
computed using the following equation.
(2.1)
Where γ is the body effect parameter, 2φF is the surface potential, and VTO is the zero
bias threshold voltage.
2.7.1
Threshold reduction
Higher drain voltages cause channel shortening, resulting in a nonzero output
conductance. When the channel length is small, the electric field associated with the
drain voltage may extend enough toward the source that the effective threshold
diminishes.
This drain-induced barrier lowering (DIBL) can cause dramatic
increases in subthreshold current. Additionally, it results in degradation in output
conductance beyond that associated with simple channel length modulation.
28
A plot of threshold voltage as a function of channel length shows a
monotonic decrease in threshold as length decreases. At the 0.5µm level, the
threshold reduction can be 100-200mV over the value in the long-channel limit,
corresponding to potential increases in subthreshold current by factors of 10 to 1000.
To reduce the peak channel field and thereby mitigate high-field effects, a
lightly-doped drain (LDD) structure is almost always used in modern devices. In
such a transistor, the doping in the drain region is arranged to have a spatial
variation, progressing from relatively heavy near the drain contact, to lighter
somewhere in the channel.
In some cases, the doping profile results in over-
compensation in the sense that higher drain voltages actually increase the threshold
over some range of drain voltages before ultimately decreasing the threshold. Not all
devices exhibit this reverse short-channel effect since its existence depends on the
detailed nature of the doping profile. Additionally, PMOS devices do not exhibit
high-field effects as readily as do NMOS transistors because the field strengths
necessary to cause hole velocity to saturate are considerably higher than those that
cause electron velocity saturation.
2.8
Leakage current
The problem with shrunken transistors to the point where the channel lengths
are so short, that a significant amount of current leaks through the source-drain
channel (sub-threshold leakage, IOFF), even when the transistor switch is in the off
position. As temperature is increased, the sub-threshold leakage increases
exponentially because of a drop in the threshold voltage.
29
Current also leaks from the base node through the oxide and channel and into
the underlying substrate (gate leakage, IGATE). As process geometries have shrunk
even further, another leakage effect is band-to-band tunneling (BTBT) where the
source/drain junctions reverse bias to allow electrons to tunnel their way into the
substrate or IJUNC.
All three sources of leakage have become a huge problem, and the process
technology is working to come up with new materials and transistor designs that
reduce the leakage.
Figure 2.16: Sources of current leakage in an n-channel MOSFET
To reduce these unwanted current, several things can be done. IOFF can be
reduced by increasing the threshold voltage. IJUNC can be reduced by low damage
junction engineering while IGATE can be reduced by increasing the gate oxide
thickness.
Each technique to reduced unwanted current can cause other short
channel effect, so the designer must scale appropriately to obtain an optimized
device.
30
2.9
Subthreshold characteristic
In simple MOSFET models, the device conducts no current until an inversion
layer forms. However, mobile carriers don’t abruptly disappear the moment the gate
voltage drops below VT . In fact, exercising a little imagination, one can discern a
structure reminiscent of an NPN bipolar transistor when the device is in the
subthreshold regime, with the source and drain regions functioning as emitter and
collector, respectively, and the (non-inverted) bulk behaving a bit like a base.
As VGS drops below threshold, the current decreases in an exponential
fashion, much like a bipolar transistor. Rather than dropping at the 60mV/decade
rate of a bipolar, however, the current in all real MOSFETs drops more slowly (e.g.,
100mV/decade) because of the capacitive voltage division between gate-source and
source-bulk.
Our first-order view of the MOSFET as a device in which the gate voltage
must reach VT before any drain current can flow provides a very useful picture for
many MOSFET applications. However, there are important applications in which
even every low current are important. Even a small current flowing through the
MOSFET allows the storage capacitor to discharge, destroying the stored
information. The assumption of an abrupt channel to turn-off when VG is reduced to
VT need to be reexamined for these cases.
The subthreshold current is due to weak inversion in the channel between
flat-band and threshold which leads to diffusion current from source drain. The drain
current in the subthreshold region is equal to
31
VD   ( VG− VT ) ⋅ q
 
   − q⋅   c ⋅ kT 
 q  ⋅ 1 − e kT ⋅ e r

I = µ( C + C )⋅
 
 
D
d
it
Z⋅ 
kT 
2
(2.2)
L
It can be seen that ID depends exponentially on gate bias, VG. However, VD
has a little influence once VD exceeds a few kT/q. If log ID plotted as a function of
VG, a linear behavior in subthreshold regime will be obtained, as shown in Figure 2.8
(b). the slope is known as subthreshold slope, S with unit of mV/decade. Typically,
S has a value of ~70mV/decace at room temperature for state-of-the art MOSFETs.
The S value means that a change of VG of 70mV will change the output ID by an
order of magnitude. Smaller value of S means a small change in the input bias can
modulate the output current.
S
(a)
(b)
Figure 2.17: (a) ID-VG curve and (b) inverse ID-VG that shows subthreshold slope, S
S is shown with the expression below.
S=
d
d log I
( ( D) )
V
G
= 2.3
kT 
1 +
q 
Cd + Cit 
Ci


(2.3)
For a small gate voltage, the subthreshold slope current is reduced to the
leakage current of the S/D junctions. From here, it determines the off-state leakage
32
current. From the subthreshold characteristics, it can be seen that if unavoidable
statistical variation of VT cause drastic variations of the subthreshold leakage current.
If VT is too high, it sacrifices the drive current which depends on the difference
between power supply voltage and VT.
Finally, many bipolar analog circuits are often translated into MOS form by
operating the devices in this regime. However, such circuits typically exhibit poor
frequency response because MOSFETs possess small transconductance in this region
of operation. As devices continue to shrink, the frequency response can nonetheless
be good enough for many applications, but careful verification is in order.
2.10
VT roll-off
In order that the threshold condition is reached in an MOS capacitor, we need
to deplete the channel charge by applying a positive bias (for nMOSFETs) until
strong inversion occurs. In a short-channel MOSFET, the depletion region has
complicated 2-D geometry and the channel region is influenced by the source/drain
(S/D) as much as by the gate. Before there is any positive bias on the gate, the
channel is already depleted by the built-in potential between the channel and S/D
regions. This influence becomes stronger when the p-n junctions between the S/D
and the channel are reverse-biased, giving rise to drain-induced barrier lowering
(DIBL). As a result of this undesirable coupling between the S/D region and the
channel, which becomes stronger as the gate length is reduced; VT is lower for a
transistor with shorter Lg. This VT roll-off is typically measured in mV/nm.
33
2.11
Summary
As a conclusion for this chapter, we have seen brief information on planar
and vertical MOSFET, and also a bit on short channel effect and other electrical
parameters that goes to affect as the transistor is scaled down. We will see more of it
in the results and analysis chapter.
CHAPTER 3
METHODOLOGY
This chapter discusses the methodology that is used in this project. The next
section will discuss the experiments and analysis of results in order to investigate the
device characters.
A comparison between planar and single channel vertical
NMOS’s performance is also addressed.
3.1
Process Simulation
Process simulation involves the modeling of physical processes with the aim
of studying their effects on the external environment and the objects applied to.
These processes usually involve the interaction between two or more systems.
Process simulation comprises the modeling of all process steps which are necessary
for the fabrication of semiconductor devices.
These process steps are layer
deposition, lithography, etching, implantation, oxidation and diffusion. Physically
and/or empirically based models are applied in the simulation.
35
The process simulation uses DevEdit as a simulator that provides general
capabilities for numerical, physically-based, two-dimensional simulation of
semiconductor processing. Figure 3.1 illustrates the overview of process simulation.
Silicon substrate doped with boron
Gate oxide grown
Polysilicon gate formation
Source and drain formation by adding
impurities
Metallization for source and drain
contact
Figure 3.1: Flow of process simulation
The planar and vertical NMOS is designed using basic structures. Uniform
doping is applied for both devices. To obtain 100nm down to 50nm of channel
length, the gate length for planar NMOS is adjusted. The impurities doping profile is
also adjusted to acquire desired length of channel. The complete details of the
NMOS design as the table follows.
Table 3.1: Summary of NMOS process flow
Process
Initial substrate doping, Na
Gate oxide thickness, tox
Source/drain implant
Junction depth, xj
NMOS
Boron, B = 1 x 1018 cm-3
10nm
Arsenic, As = 1 x 1020 cm-3
0.1µm
36
3.2
Process development
3.2.1 Work area
A work area is created for the device to be designed on it. Planar NMOS is
created with a depth of 0.6 micron and length of 0.4 micron as shown in Figure 3.2
(a). As for vertical NMOS, the depth of the work area is set to 0.55 micron with the
length of 0.2 micron as shown in Figure 3.2 (b). The length of the work area for
vertical NMOS is smaller because it is created in single channel first, and to obtain
the whole device, the design will be mirrored at the end of the simulation. Figure 3.3
is an example of the work area for planar NMOS.
(a)
(b)
Figure 3.2: Work area’s depth and length values for (a) planar NMOS and (b)
vertical NMOS
37
Figure 3.3: Workspace for planar NMOS
3.2.2 Adding silicon base region
We start with a silicon layer of 400nm in thickness as the body (Figure
3.4(a)) and uniformly doped with boron with concentration of 1018/cm3 for each
planar NMOS design. As for vertical NMOS, 300nm of silicon layer is the body
with a pillar height of 180nm which will act as the channel further in the process
(Figure 3.4(b)). It is also uniformly doped with boron concentration 1018/cm3, as in
Figure 3.5. The concentration, N [cm-3] refers to the total doping concentration.
38
substrate
(a)
substrate
(b)
Figure 3.4: Silicon region for (a) planar NMOS and (b) vertical NMOS
39
Figure 3.5: Base impurity, boron, added to the silicon
3.2.3 Creating gate oxide
A thin oxide layer of 10nm is grown to reduce the channeling effect and to
prevent contamination of the substrate. Channeling means that ions penetrate deeper
into the silicon along certain crystal directions building channel for the ions. For
planar, the oxide layer is created horizontally on the surface of substrate, and for
vertical, the silicon dioxide covers the side of the pillars and also the horizontal
surface of the substrate. Silicon dioxide (SiO2) layer for planar and vertical NMOS
is shown in Figure 3.6.
40
substrate
(a)
substrate
(b)
Figure 3.6: SiO2 layer for (a) planar NMOS and (b) vertical NMOS
41
3.2.4 Adding contacts for source/drain
Contact is added for source and drain regions. Aluminum is used as the metal
contact for drain and source. The aluminum region is marked as an electrode.
Finished added contact is as in Figure 3.7.
source
drain
substrate
(a)
42
drain
source
substrate
(b)
Figure 3.7: Contacts for (a) planar NMOS and (b) vertical NMOS
3.2.5 Adding substrate contact
The substrate is added with contact so that the current can flow thru the
substrate. This is done by selecting “Substrate Electrode Exists” in the DevEdit
“Regions” menu. Figure 3.8 shows the panel that adds the substrate contact.
43
Figure 3.8: Substrate electrode panel
3.2.6 Polysilicon gate formation
Another important development in the evolution of MOSFET is the
replacement of metal gate with polysilicon gate. Early MOSFET used aluminum as
a gate electrode, hence the name MOSFET. While a metal gate is ideal from a
purely transistor-architecture standpoint, it puts a great deal of constraint on process
integration. Use of heavily doped polysilicon as a gate material opened a whole new
horizon and allowed tremendous improvement in scalability of MOS transistors and
technology.
A heavily doped polysilicon, 100nm in thickness for planar NMOS and 20nm
of polysilicon for vertical NMOS, is as shown in Figure 3.9. Length of the gate of
the planar NMOS defines the length of the channel; hence, physically it must be
adjusted to obtain desired effective channel length of 100nm down to 50nm. As for
vertical NMOS, the length of the transistor gate did not affect the channel length.
44
gate
source
drain
substrate
(a)
drain
gate
source
substrate
(b)
Figure 3.9: Polysilicon gate region for (a) planar NMOS and (b) vertical NMOS
45
Impurities are added to the gate to create a highly doped region.
As
mentioned before, it is used to replace with a metal based material to be the gate.
Concentration of 1020cm-3 of arsenic is used as the impurity.
Figure 3.10: Adding impurities to gate to create highly doped region
3.2.7 Source/drain doping
A high dose of arsenic with concentration of 1020/cm3 is implanted to create
the source and drain region.
To create source for planar and vertical NMOS,
Gaussian distribution is used to create desired shape of source region, as in Figure
3.11. It goes the same for drain in planar NMOS (Figure 3.12(a)). As to create drain
in vertical NMOS, a linear distribution is used to create the drain on top (Figure
3.12(b)).
46
For planar NMOS, as in creating the source/drain region, the impurity
degree’s region is adjusted to achieve desired effective channel length, in
conjunction with adjusting the physical gate length. For vertical NMOS, the linear yplane roll-off of the implant is adjusted to achieve desired channel length.
(a)
(b)
Figure 3.11: Impurity added to create source for (a) planar NMOS and (b) vertical
NMOS
47
(a)
(b)
Figure 3.12: Impurity specification to create drain for (a) planar NMOS and (b)
vertical NMOS
Results of doping the source and drain region is as in Figure 3.13. In these
figures, it shows the net doping for each device.
48
gate
source
drain
substrate
(a)
drain
gate
source
substrate
(b)
Figure 3.13: Net doping for (a) planar NMOS and (b) vertical NMOS
49
3.2.8 Creating mesh
Finally, the mesh is applied to the device using automatic mesh creator. The
mesh parameters are adjusted to create desired mesh as in Figure 3.14 (a). Condition
of the mesh affects the electron flow inside the device. The minimum value of mesh
is defined in the refinement section (Figure 3.14(b)). The mesh is created according
to the net doping of the device. Finer mesh is applied at each junction for better flow
of electrons once the device is simulated in Atlas. Figure 3.15 shows the device with
applied mesh.
(a)
(b)
Figure 3.14: (a) Mesh parameters and (b) refinement on mesh for planar and vertical
NMOS
50
gate
source
drain
substrate
(a)
drain
gate
source
substrate
(b)
Figure 3.15: Mesh on (a) planar NMOS and (b) vertical NMOS
51
3.2.9 Final device
After going through all of the process, the device is now complete. The
single channel vertical NMOS is mirrored to the left to create the full vertical
NMOS. Figure 3.16 shows the final planar NMOS and Figure 3.17 shows the
vertical NMOS before and after mirrored. Figure 3.18 shows the planar and vertical
NMOS with effective channel length of 100nm.
gate
source
substrate
Figure 3.16: Completed planar NMOS
drain
52
drain
gate
source
substrate
(a)
drain
gate
gate
source
source
substrate
(b)
Figure 3.17: Completed (a) single channel vertical NMOS and (b) full vertical
NMOS
53
(a)
(b)
Figure 3.18: (a) Planar NMOS and (b) vertical NMOS with effective channel length
of 100nm
54
3.3
Device simulation
Device simulation is applied to calculate the electrical behaviour of the
semiconductor devices. The information about device geometry and the local doping
concentrations must be given by some kind of solid modeling or full process
simulation.
One important advantage of the simulation approach becomes clear. The
distribution of electrical parameters can be made visible easily, which is not very
difficult to achieve in a real transistor and very advantageous for the tuning of a
specific design. The transistor in the following simulation is the result of a TCAD
based optimization approach. The four contacts are called source and drain (S/D, ndoped regions), gate (G, contact above substrate region with oxide layer in between),
and bulk (B, contact of the substrate). The simulated device is called enhancement
mode which is normally off, meaning that there is no current flows between source
and drain when no voltage is applied to the gate contact.
For this project, two main simulations have been done on each device. First
is to obtain the output characteristic which is the ID-VDS graphs and second is
obtaining the transfer characteristic or also known ad ID-VGS graph. From these two
characteristic, we can obtain the threshold voltage, leakage current, maximum
drain/source current, drain saturation slope and also subthreshold slope. The results
of the simulation will be shown in Chapter 4.
55
3.3.1 Output characteristic
In short channel devices, the effective channel mobility decreases with
increasing transverse electric field perpendicular to the gate oxide. For short channel
lengths, the carriers travel at the saturation velocity over most of the channel. With
this, the drain current is given by the width times the channel charge per unit area
times the saturation velocity.
A few parameters can be extracted from this curve, such as threshold voltage,
maximum drain current, leakage current and also subthreshold slope. Using these
parameters, we can determine the characteristic of the design.
Threshold voltage is one of the important parameter in MOSFET device.
Threshold voltage determines the requirements for turning the MOSFET on or off,
thus it is very important to be able to adjust VT in designing the device. The
expression of the threshold voltage is shown in equation 2.1.
Leakage current is important to know so that it has the minimum value to
avoid short channel effect. Big leakage current can cause faulty of the device design
and it must be considered in engineering the device.
Subthreshold slope, S is the slope degree when ID-VGS graph is inversed.
This slope is available when VG<VT. Subthreshold slope is defined as the changes in
magnitude of the subthreshold current for every decade when gate voltage is applied.
Smaller subthreshold slope means the better subthreshold behavior, with lower
leakage current at VG=0 for given VT. Ideal value of S is 70mV/dec.
56
To bring out the ID-VDS curve and extract the parameters, a program as in
Appendix A is used.
3.3.2 Transfer characteristic
Transfer characteristic or ID-VGS curve can show us more on the performance
of the device. From this curve, we can extract drain saturation slope which can
determine the drain saturation current of the device. The program is as in Appendix
B.
3.4
Summary
In this chapter, the methodology to create the planar and vertical NMOS
transistors and also to simulate the device has been done. The results from the
simulation can bee seen in the next chapter of results and analysis.
CHAPTER 4
EXPERIMENTAL RESULTS AND ANALYSIS
This chapter discusses the experimental results of this project and its analysis.
Comparison between the devices is done for planar and single channel vertical
NMOS.
4.1
Results
4.1.1 Output characteristic
The output characteristic is obtained with applying gate voltage of 3.3V and
the drain voltage is ramped from 0V to 1.8V with a step of 0.1V. With higher gate
voltage, the characteristic of the device can be seen more clearly.
58
ID-VDS at VGS=3.3V
50nm NMOS
60nm NMOS
70nm NMOS
80nm NMOS
90nm NMOS
100nm NMOS
50nm VMOS
60nm VMOS
70nm VMOS
80nm VMOS
90nm VMOS
100nm VMOS
6.00E-04
50nm planar NMOS
Drain current, ID [A/um]
5.00E-04
4.00E-04
3.00E-04
2.00E-04
50nm vertical NMOS
1.00E-04
0.00E+00
0
0.2
0.4
0.6
0.8
1
1.2
-1.00E-04
Drain voltage, VDS [V]
Figure 4.1: ID-VDS curve for planar and single channel vertical NMOS
The graph show the result of the curve with the highest drain current with
50nm planar NMOS device, followed by larger effective channel length respectively.
Smaller channel length has higher drain current as shown in equation 4.1.
I
D
=
W ⋅ µ n⋅ C
ox
2L
⋅ 2 V

(
GS
)
− V ⋅V
T
DS
⋅ − V
(
DS
)2
(4.1)
From here we can see that shorter channel length have less space for the
electron to go through, thus it creates higher current because of the high doping
density means more electron in a smaller area. Planar NMOS shows faster response
than single channel vertical NMOS because of the planar channeling is easier for the
electron to flow.
59
4.1.2 Transfer characteristic
With applying a drain voltage of 0.1V, and ramp the gate with step voltage of
0.05V, with a gate bias from 0V to 1.8V, the graph below is obtained.
ID-VGS for Planar and Single Channel Vertical NMOS at
VDS=0.1V
100nm NMOS
90nm NMOS
80nm NMOS
70nm NMOS
60nm NMOS
50nm NMOS
100nm VMOS
90nm VMOS
80nm VMOS
70nm VMOS
60nm VMOS
50nm VMOS
Gate bias, VGS [V]
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
1.00E-04
1.00E-05
Drain current, ID [A/um]
1.00E-06
50nm planar NMOS
1.00E-07
1.00E-08
1.00E-09
1.00E-10
50nm vertical NMOS
1.00E-11
1.00E-12
1.00E-13
1.00E-14
1.00E-15
1.00E-16
Figure 4.2: ID-VGS curve for planar and single channel vertical NMOS
Once again, the planar NMOS have higher drain current, mostly due to the
design of the planar itself. From this semi log graph, we can also determine the on
and off current of the transistor. For 50nm NMOS, the IOFF for planar is nearly two
and a half decade higher than the IOFF for vertical NMOS. ION for planar NMOS is
also holds the same difference with vertical NMOS. From the graph we can say that
planar have lower voltage to turn it on, ~0.8V for 50nm planar NMOS compared
with 50nm single channel vertical NMOS that need ~1.1V to turn it on.
60
4.1.3 Threshold voltage
The threshold voltage of the device is obtained from the extraction of the
graph, which is used in Silvaco-Atlas. Figure 4.3 shows the threshold voltage versus
effective channel length for 100nm down to 50 nm.
Threshold voltage
Planar NMOS
Single Channel Vertical NMOS
Threshold voltage, VT [V]
1.3
1.2
1.1
1
0.9
0.8
0.7
40
50
60
70
80
90
100
110
Effective channel length, Lg [nm]
Figure 4.3: Threshold voltage for planar and single channel vertical NMOS
Vertical NMOS show better VT roll-off with not much changes of threshold
voltage changes from 100nm to 50nm. In the other hand, planar NMOS shows
lowest threshold voltage at 50nm. This is good for lower voltage usage as the market
needed right now, but planar NMOS a rough roll-off from 100nm to 50nm, which
shows bad gate control than vertical NMOS.
61
To reduce the threshold voltage, we can reduce the gate oxide thickness, tox.
A test has been done using gate oxide thickness of 2nm, 4nm, 6nm, and 8nm. This
will be reviewed more in the analysis segment.
4.1.4 Leakage current
Leakage current happened when there is current flow between drain and
source even when the transistor is off. IOFF, which is mainly due to diffusion current,
degrades (increases) with decreasing feature sizes.
Leakage current
Planar NMOS
Single Channel Vertical NMOS
1.00E-10
Leakage current, IOFF [A/um]
40
50
60
70
80
90
100
1.00E-11
1.00E-12
1.00E-13
1.00E-14
1.00E-15
1.00E-16
Effective channel length, Lg [nm]
Figure 4.4: Leakage current for planar and single channel vertical NMOS
110
62
Overall, vertical NMOS shows a promising value of leakage current. Even at
100nm, it shows lower leakage value than planar NMOS, which is 0.13fA/µm and
0.30fA/µm respectively. Planar NMOS at 50nm shows highest leakage current of
22.7pA/µm. Lower leakage control for vertical NMOS is caused by better gate
control on channeling the current.
At 50nm regime, using vertical NMOS, the
leakage current is reduced by 99.7%.
4.1.5 Subthreshold slope
The aim is to obtain subthreshold slope value at ~70mV/devade for optimum
performance.
Subthreshold slope
Planar NMOS
Single Channel Vertical NMOS
Subthreshold slope, S
[mV/decade]
140
130
120
110
100
90
80
40
50
60
70
80
90
100
110
Effective channel length, Lg [nm]
Figure 4.5: Subthreshold slope for planar and single channel vertical NMOS
63
Vertical NMOS shows almost similar values of S in range of 84 to
88mV/decade. The subthreshold swing of ~130mV/dec indicates high interface state
densities.
4.1.6 Drain saturation slope
Drain saturation slope is obtained from the transfer characteristic. It is the
slope that happens when the drain current is at the maximum, in the saturation
region.
Drain saturation slope at VGS=1.5V
Planar NMOS
Single channel vertical NMOS
50
70
9.00E-05
Saturation slope
8.00E-05
7.00E-05
6.00E-05
5.00E-05
4.00E-05
3.00E-05
2.00E-05
1.00E-05
0.00E+00
40
60
80
90
100
110
Effective channel length, Lg [nm]
Figure 4.6: Drain saturation slope for planar and single channel vertical NMOS
64
From Figure 4.6, it shows that vertical NMOS obtain lower drain saturation
slope, with a smooth curve from 100nm down to 50nm, means that the maximum
drain current is lower than planar NMOS.
With lower saturation current, the
transistor can be on at smaller voltage. 22.7% of drain saturation slope is reduced
from planar to vertical NMOS in 50nm regime.
4.2
Analysis
4.2.1 Varied gate oxide thickness
An experiment has been done using the same device with the same
parameters, but the gate oxide thickness is varied with 2nm, 4nm, 6nm and 8nm to
investigate is it true that with reducing gate oxide thickness, it can lower the
threshold voltage. From the same simulation, the behaviour of the subthreshold
slope and leakage current is also observed.
4.2.1.1 Threshold voltage
Using the same device simulation program, the threshold voltage as in Figure
4.7 is obtained. From here we can see that the thinner the gate oxide become, the
lower the threshold voltage appears. The lowest threshold voltage is using gate oxide
thickness of 2nm. It ranged from 0.71V to 1.23V for planar NMOS and 0.98V to
1.27V for vertical NMOS.
65
Threshold voltage with varied gate oxide thickness
2nm
4nm
6nm
8nm
10nm
1.4
Threshold voltage, VT [V]
1.2
1
0.8
0.6
0.4
0.2
0
S
S
OS
OS
OS
OS
OS
OS MO
OS
OS
OS
OS MO
VM
NM
NM
VM nmV
NM m NM
VM mVM
VM
NM nmN
m
m
m
m
m
m
m
m
n
n
n
n
n
n
n
n
0n
60
0n
90
50
50
80
70
60
90
70
80
10
10
Planar and vertical NMOS
Figure 4.7: Threshold voltage with varied gate oxide thickness for planar and vertical
NMOS
4.2.1.2 Subthreshold slope
Figure 4.8 is obtained by extract of the subthreshold slope. We target to
achieve smaller swing, as low as 70mV/decade, and it is possibly achieved using
2nm gate oxide thickness. Another gate oxide thickness value which is also relevant
with a range of swing in 80mV/decade is 4nm. It gives a slightly higher value of
subthreshold slope but it is still reasonable for the device.
66
Subthreshold slope with varied gate oxide thickness
2
4
6
8
10
Subthreshold slope, S [mV/decade]
140
130
120
110
100
90
80
70
60
1
S
S
S
S
S
S
S
S
S
S
S
O
O
S
O
O
O
O
O
O
O
O
O
O
M
M
NM
NM
VM
M
NM
VM
VM
NM
VM
V
NM m N
V
m
m
m
n
n
nm
nm
nm
nm
nm
nm
nm 90n
0n
nm
80
50
60
60
90
70
70
50
00
10
80
Planar and vertical NMOS
Figure 4.8: Subthreshold slope with varied gate oxide thickness for planar and
vertical NMOS
4.2.1.3 Leakage current
As we can see earlier, by using smaller gate oxide thickness, we can achieve
lower voltage threshold and smaller subthreshold swing. However, it got a tradeoff
in the leakage current department. We can see from the extracted graph in Figure 4.9
as thinner the gate oxide is, the higher the leakage current becomes. It shows the
lowest values of leakage current at 10nm of gate oxide thickness.
67
Leakage current with varied gate oxide thickness
2
4
6
8
10
1.00E-06
Leakage current, IOFF [A/um]
1.00E-07
1.00E-08
1.00E-09
1.00E-10
1.00E-11
1.00E-12
1.00E-13
1.00E-14
1.00E-15
1.00E-16
S OS
OS O S O S O S OS OS OS OS O S MO
OS
NM m N M N M m NM NM NM VM m VM m VM m V m VM VM
m
m
m
m
m
0n 9 0n 80n 70 n 60 n 5 0n 0 0n 90n 80 n 70 n 6 0n 5 0n m
10
1
Planar and vertical NMOS
Figure 4.9: Leakage current with varied gate oxide thickness for planar and vertical
NMOS
4.2.1.4 Conclusion
Using smaller value of gate oxide thickness, it creates lower threshold voltage
better subthreshold swing values.
But it has a tradeoff in the leakage current
department as the leakage current increases as the gate oxide thickness decreases.
From here, the designer should take note on the advantages and disadvantages as it
can affect the transistors as whole.
68
4.2.2 Varied body doping concentration
Another parameter that has been manipulated in this project is the body
doping concentration. In the next sub-topics, we will see the effect of varied body
doping concentration on threshold voltage, subthreshold slope and leakage current.
The body doping concentration varies from 1015cm-3 to 1019cm-3. Other parameters
that were designed earlier are the same.
4.2.2.1 Threshold voltage
By simulation, threshold voltage as in Figure 4.10 obtained. Low threshold
voltage values can be achieved by using lower body doping concentration, but
resulting VT in the negative region values.
transistor with a negative threshold voltage.
It is impossible having an NMOS
The best value of body doping
concentration is 1018cm-3, which has been used throughout the project for all NMOS
transistors.
69
Threshold voltage with varied body doping concentration
-3
[cm ]
10^15
10^16
10^17
10^18
10^19
Threshold voltage, V T [V]
1.4
1.2
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
S
S
S
S
S
S
S
S
S
S
S
OS
MO N MO N MO N MO N MO VMO VMO VMO VMO VMO VMO
NM
N
m
m
m
m
m
m
m
m
m
m
m
m
n
n
n
n
n
n
n
n
n
n
n
n
0
0
60
70
60
70
50
50
90
80
90
80
10
10
Planar and Vertical NMOS
Figure 4.10: Threshold voltage with varied body doping concentration for planar and
vertical NMOS
4.2.2.2 Subthreshold slope
From Figure 4.11, as low as the body doping concentration is, the higher the
subthreshold slope becomes. It results as high as 1.09V/decade for 50nm NMOS
transistor with body doping concentration of 1015cm-3. It shows the best swing at the
range of 85 to 135mV/decade with the body doping concentration of 1018cm-3. Other
than the value of 1018cm-3 shows an unpromising body doping concentration to be
used for the device in nanometer regime.
70
Subthreshold slope for varied body doping concentration
-3
[cm ]
Subthreshold slope, S [mV/decade]
10^15
10^16
10^17
10^18
10^19
1200
1000
800
600
400
200
0
1
S
S
OS M OS MOS
OS
S
O S M O NM
MO VM
OS MOS MOS
OS
N
N
V
M
N
M
MO VM
V
m
m
V
N
m
m
N
m
V
n
n
m
n
n
0n
70
90
60
50
nm 90nm 80n
nm 70nm 60nm 50nm
10
00
80
Planar and vertical NMOS
Figure 4.11: Subthreshold slope with varied body doping concentration for planar
and vertical NMOS
4.2.2.3 Leakage current
Figure 4.12 shows the comparison of using different body doping
concentration for each transistor used in this project.
19
With body doping
-3
concentration of 10 cm , it is the best for lowest leakage current, but as we have
seen earlier, it does not show good performance in the threshold voltage and
subthreshold slope section.
The next best lowest leakage current is using
concentration of 1018cm-3, as been used in this project as well. Lower body doping
concentration shows higher leakage current achieved.
71
Leakage current with varied body doping
-3
concentration [cm ]
10^15
10^16
10^17
10^18
10^19
Leakage current, I OFF [A/um]
1.00E-04
1.00E-06
1.00E-08
1.00E-10
1.00E-12
1.00E-14
1.00E-16
1.00E-18
1.00E-20
S
S
O S MO S MO MOS MOS MO MOS MOS MOS MO S MO S MOS
M
N
V
N
N
V
V
V
V
N
V
N
N
nm 0nm 80 nm 0nm 0nm 50n m 0n m 0n m 0n m 0nm 0 nm 50n m
0
9
6
9
8
7
6
7
10
10
Planar and vertical NMOS
Figure 4.12: Leakage current with varied body doping concentration for planar and
vertical NMOS
4.2.2.4 Conclusion
The best body doping concentration being used experimentally in the regime
tested is 1018cm-3. Using this body doping concentration, it shows the most relevant
threshold voltage, considerable subthreshold swing and also low leakage current.
72
4.3
Summary
In this chapter we have seen the results and analysis of each planar and
vertical transistor.
We can see that each device has its own advantages and
disadvantages. As the device is analyzed, it also has some tradeoffs by using certain
parameters of gate oxide thickness and body doping concentration. The conclusion
of the whole project and future works will be listed in the final chapter.
CHAPTER 5
CONCLUSION AND FUTURE WORKS
This chapter discusses the conclusion and also including the future works for
this project. The main objective of this project is to design and compare the device
characteristics when it is scaled down to 50nm.
5.1
Conclusion
At the end of the project, the planar and vertical n-channel MOSFET is
successfully developed and tested. Even though the device is not optimized; it still
shows good result to study on.
From the comparison in chapter 4, it is shown that planar and vertical NMOS
has its own advantages and tradeoffs. Vertical NMOS has better VT roll-off control,
lower leakage current, better subthreshold swing of ~85mV/decade, and lower drain
saturation slope. On the other hand, planar NMOS got lower threshold voltage,
which is good for low power supply.
74
By using thinner gate oxide, we can have lower threshold voltage and also
smaller subthreshold swing. It comes with a tradeoff in leakage current as it resulting
bigger leakage current as the gate oxide becomes thinner. Experimentally, the best
body doping concentration used is 1018cm-3 which comes with relevant threshold
voltage, considerable subthreshold swing and also low leakage current values.
5.2
Suggestion for future works
There are several suggestions and future works that can be done to further
improve this project. The suggestions are:
1. Applying advanced fabrication technique to the device to suppress the short
channel effect. This can show better device characteristic when analyzed.
2. Designing the device with proper scaling, according to the scaling rules for
optimum device performance.
3. Do tests on drain induced barrier lowering (DIBL), body effect test, calculate
the transconductance and produce the C-V characteristic for performance
comparison with other device available in the journals.
75
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No. 2/3
APPENDIX A
Family of ID-VDS curve program
(Silvaco Atlas)
79
go atlas
#
mesh infile=nmos_100.str
# define the Gate workfunction
contact name=gate n.poly
# Define the Gate Qss
interface qf=3e10
# Use the cvt mobility model for MOS
models cvt srh print numcarr=2
method climit=1e-4 maxtrap=10
# set
solve
solve
solve
solve
gate biases with Vds=0.0
init
vgate=1.1 outf=solve_tmp1
vgate=2.2 outf=solve_tmp2
vgate=3.3 outf=solve_tmp3
#load in temporary files and ramp Vds
load infile=solve_tmp1
log outf= nmos_100_1.log
solve name=drain vdrain=0 vfinal=1.5 vstep=0.1
load infile=solve_tmp2
log outf= nmos_100_2.log
solve name=drain vdrain=0 vfinal=1.5 vstep=0.1
load infile=solve_tmp3
log outf= nmos_100_3.log
solve name=drain vdrain=0 vfinal=1.5 vstep=0.1
# extract max current and saturation slope
extract name="nidsmax" max(i."drain")
extract name="sat_slope" slope(minslope(curve(v."drain",i."drain")))
tonyplot -overlay -st nmos_100_1.log
quit
nmos_100_2.log nmos_100_3.log
APPENDIX B
ID-VGS at VDS=0.1V program
(Silvaco Atlas)
81
go atlas
#input file
mesh infile=nmos_100.str
#model
models srh cvt boltzman print temperature=300
#mobility model
mobility bn.cvt=4.75e+07 bp.cvt=9.925e+06 cn.cvt=174000
cp.cvt=884200 \
taun.cvt=0.125 taup.cvt=0.0317 gamn.cvt=2.5 gamp.cvt=2.2 \
mu0n.cvt=52.2 mu0p.cvt=44.9 mu1n.cvt=43.4 mu1p.cvt=29
mumaxn.cvt=1417 \
mumaxp.cvt=470.5 crn.cvt=9.68e+16 crp.cvt=2.23e+17
csn.cvt=3.43e+20 \
csp.cvt=6.1e+20 alphn.cvt=0.68 alphp.cvt=0.71 betan.cvt=2
betap.cvt=2 \
pcn.cvt=0 pcp.cvt=2.3e+15 deln.cvt=5.82e+14
delp.cvt=2.0546e+14
#contact characteristic
contact name=gate n.poly
#specify interface properties
interface
s.n=0.0 s.p=0.0 qf=3e10
#numerical methods selection command group
method
newton gummel itlimit=25 trap atrap=0.5 maxtrap=4 autonr \
nrcriterion=0.1 tol.time=0.005 dt.min=1e-25 damped delta=0.5
\
damploop=10 dfactor=10 iccg lu1cri=0.003 lu2cri=0.03
maxinner=25
# obtain Id vs Vgs with Vds = 0.1V
solve init
solve vdrain=0.1
log outf=nmos_100.log
solve name=gate vgate=0 vfinal=1.5 vstep=0.05 vdrain=0.1
#extracting device parameters
extract name="vt"
(xintercept(maxslope(curve(abs(v."gate"),abs(i."drain")))) \
- abs(ave(v."drain"))/2.0)
extract name="idsmax" max(abs(i."drain"))
extract name="leak" min(abs(i."drain"))
extract name="subvt" \
1.0/slope(maxslope(curve(abs(v."gate"),log10(abs(i."drain")))))
tonyplot nmos_100.log
quit
APPENDIX C
Extract results from simulation
83
1) Threshold voltage
Effective
channel length,
Lg [nm]
50
60
70
80
90
100
Planar NMOS
[V]
0.7111
0.9005
1.0381
1.1086
1.1869
1.2343
Single Channel
Vertical NMOS
[V]
0.9810
1.0888
1.1620
1.2219
1.2592
1.2901
2) Leakage current
Effective
channel length,
Lg [nm]
50
60
70
80
90
100
Planar NMOS
[A/µm]
2.27E-11
2.80E-13
1.09E-14
2.92E-15
6.80E-16
3.02E-16
Single Channel
Vertical NMOS
[A/µm]
7.37E-14
6.53E-15
1.30E-15
4.00E-16
2.08E-16
1.27E-16
3) Subthreshold slope
Effective
channel length,
Lg [nm]
50
60
70
80
90
100
Planar NMOS
[mV/decade]
134.59
125.17
81.39
83.15
83.81
86.68
Single Channel
Vertical NMOS
[mV/decade]
87.68
85.19
84.64
84.61
85.41
85.33
84
4) Drain saturation slope
Effective
channel length,
Lg [nm]
50
60
70
80
90
100
Single Channel
Vertical NMOS
Planar NMOS
8.33E-05
5.61E-05
4.16E-05
3.30E-05
2.22E-05
1.42E-05
6.03E-05
4.37E-05
3.07E-05
1.93E-05
1.32E-05
8.81E-06
5) Threshold voltage with varied gate oxide thickness
(in V)
Gate oxide
thickness
2nm
4nm
6nm
8nm
10nm
100nm
NMOS
0.1221
0.3976
0.6769
0.9559
1.2292
90nm
NMOS
0.1128
0.3794
0.6488
0.9181
1.1869
80nm
NMOS
0.0958
0.3453
0.6004
0.8548
1.1086
70nm
NMOS
0.0963
0.3292
0.5665
0.8029
1.0381
60nm
NMOS
0.0674
0.2751
0.4846
0.6932
0.9005
50nm
NMOS
0.0318
0.2031
0.3731
0.5434
0.7111
Gate oxide
thickness
2nm
4nm
6nm
8nm
10nm
100nm
MOS
0.1680
0.4468
0.7323
1.0220
1.2718
90nm
MOS
0.1625
0.4359
0.7153
0.9988
1.2498
80nm
MOS
0.1554
0.4216
0.6938
0.9701
1.2191
70nm
MOS
0.1444
0.4002
0.6605
0.9246
1.1620
60nm
MOS
0.1331
0.3738
0.6193
0.8688
1.0888
50nm
MOS
0.1146
0.3343
0.5576
0.7843
0.9810
85
6) Subthreshold slope with varied gate oxide thickness
(in mV/decade)
Gate oxide
thickness
2nm
4nm
6nm
8nm
10nm
100nm
NMOS
71.02
81.16
92.83
76.21
86.68
Gate oxide
thickness
2nm
4nm
6nm
8nm
10nm
100nm
MOS
72.01
83.60
96.07
74.95
85.33
90nm
NMOS
71.54
81.36
93.14
74.24
83.81
90nm
MOS
72.17
83.81
96.49
75.18
85.41
80nm
NMOS
72.69
81.82
93.66
74.15
83.15
80nm
MOS
72.29
83.81
96.74
73.52
84.61
70nm
NMOS
73.69
83.03
94.95
107.63
81.40
60nm
NMOS
76.93
85.15
97.54
111.09
125.17
70nm
MOS
72.62
84.19
97.39
73.71
84.64
50nm
NMOS
85.14
90.03
103.63
118.65
134.59
60nm
MOS
73.00
84.72
98.43
112.68
85.19
50nm
MOS
73.81
85.25
99.27
114.14
87.68
7) Leakage current with varied gate oxide thickness
(in A/µm)
Gate oxide
thickness
2nm
4nm
6nm
8nm
10nm
100nm
NMOS
1.61E-08
1.44E-11
1.10E-13
3.60E-15
3.02E-16
90nm
NMOS
2.41E-08
2.77E-11
2.26E-13
7.81E-15
6.80E-16
80nm
NMOS
4.47E-08
8.07E-11
8.22E-13
3.14E-14
2.92E-15
70nm
NMOS
4.83E-08
1.55E-10
2.32E-12
1.06E-13
1.09E-14
60nm
NMOS
1.25E-07
8.94E-10
2.55E-11
1.91E-12
2.80E-13
50nm
NMOS
4.32E-07
9.25E-09
6.22E-10
9.14E-11
2.27E-11
Gate oxide
thickness
2nm
4nm
6nm
8nm
10nm
100nm
MOS
7.62E-09
7.19E-12
4.69E-14
1.45E-15
1.28E-16
90nm
MOS
9.42E-09
1.06E-11
7.72E-14
2.43E-15
2.09E-16
80nm
MOS
1.19E-08
1.67E-11
1.41E-13
4.58E-15
4.00E-16
70nm
MOS
1.70E-08
3.39E-11
3.78E-13
1.42E-14
1.30E-15
60nm
MOS
2.57E-08
7.81E-11
1.26E-12
6.16E-14
6.53E-15
50nm
MOS
4.83E-08
2.68E-10
7.07E-12
5.13E-13
7.37E-14
86
8) Threshold voltage with varied body doping concentration
(in V)
Body doping
concentration
[cm-3]
1015
16
10
1017
18
10
19
10
Body doping
concentration
-3
[cm ]
15
10
1016
17
10
1018
19
10
100nm
NMOS
-0.2984
-0.2259
0.0434
1.2292
0.7648
100nm
MOS
-0.2981
-0.2675
-0.0366
1.2718
0.9454
90nm
NMOS
80nm
NMOS
70nm
NMOS
60nm
NMOS
50nm
NMOS
-0.3196
-0.2469
0.0132
1.1869
0.5262
-0.3597
-0.2744
-0.0237
1.1086
0.7534
-0.3851
-0.3108
-0.0518
1.0381
0.4363
-0.4342
-0.3608
-0.1048
0.9005
-0.1511
-0.4980
-0.4296
-0.1716
0.7111
1.2395
90nm
MOS
80nm
MOS
70nm
MOS
60nm
MOS
50nm
MOS
-0.3081
-0.2791
-0.0520
1.2497
1.2164
-0.3218
-0.2913
-0.0654
1.2321
0.9360
-0.3375
-0.3092
-0.0873
1.1620
1.1833
-0.3529
-0.3304
-0.1143
1.0888
1.0862
-0.3769
-0.3591
-0.1522
0.9810
1.2772
60nm
NMOS
50nm
NMOS
9) Subthreshold slope with varied body doping concentration
(in mV/decade)
Body doping
concentration
-3
[cm ]
15
10
1016
17
10
1018
19
10
100nm
NMOS
627.81
460.15
125.50
86.68
334.65
90nm
NMOS
676.76
508.88
144.57
83.81
222.58
80nm
NMOS
769.22
572.31
175.58
83.15
157.98
70nm
NMOS
827.85
656.47
216.35
81.40
315.85
941.01
771.84
284.54
125.17
321.74
1088.16
930.36
390.76
134.59
157.04
87
Body doping
concentration
-3
[cm ]
15
10
1016
17
10
1018
19
10
100nm
MOS
626.97
556.43
168.21
85.33
35.10
90nm
MOS
650.20
583.27
188.37
85.40
51.89
80nm
MOS
681.78
611.30
213.94
84.59
44.56
70nm
MOS
718.02
652.59
251.48
84.64
68.45
60nm
MOS
753.74
701.73
299.04
85.19
68.01
50nm
MOS
808.87
767.82
370.76
87.68
99.07
10) Leakage current with varied body doping concentration
(in A/µm)
Body doping
concentration
-3
[cm ]
15
10
1016
17
10
1018
19
10
Body doping
concentration
[cm-3]
15
10
16
10
1017
18
10
1019
100nm
NMOS
90nm
NMOS
80nm
NMOS
70nm
NMOS
60nm
NMOS
50nm
NMOS
2.51E-05
1.81E-05
5.33E-07
3.02E-16
5.12E-18
2.79E-05
2.10E-05
1.07E-06
6.80E-16
4.47E-18
3.39E-05
2.47E-05
2.17E-06
2.92E-15
3.66E-18
3.48E-05
2.86E-05
3.49E-06
1.09E-14
5.59E-18
3.99E-05
3.47E-05
6.77E-06
2.80E-13
4.60E-18
4.61E-05
4.25E-05
1.25E-05
2.27E-11
3.44E-18
100nm
MOS
90nm
MOS
80nm
MOS
70nm
MOS
60nm
MOS
50nm
MOS
2.17E-05
2.01E-05
2.21E-06
1.28E-16
7.24E-20
2.30E-05
2.17E-05
2.95E-06
2.09E-16
3.29E-20
2.42E-05
2.34E-05
3.92E-06
3.96E-16
9.12E-20
2.59E-05
2.55E-05
5.45E-06
1.30E-15
2.56E-19
2.80E-05
2.82E-05
7.58E-06
6.53E-15
1.84E-19
3.03E-05
3.13E-05
1.09E-05
7.37E-14
4.31E-19