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Download NLHVQ011 - 1-Bit Gate Pulse Modulator
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NLHVQ011 1-Bit Gate Pulse Modulator The NLHVQ011 is a 1−bit gate pulse modulator designed to translate logic voltages for TFT LCD panels for automotive applications. This part translates a low voltage logic input signal to an output voltage of 15 V to 38 V. In addition, the NLHVQ011 provides a user selectable delay and fall time on the high−to−low edge of the output signal. The delay and fall times are controlled by the magnitudes of the external and capacitor resistor, respectively. www.onsemi.com MARKING DIAGRAM Features • • • • • • • • Gate Pulse Modulation (GPM) AEC−Q100 Grade 1 Qualified Adjustable TFT LCD Flicker Compensation Circuitry Reduction of Coupling Effect Between Gate Line and Pixel Provides Power Sequencing Circuit for Gate Driver IC Wide Power Supply Operation: 15 V to 38 V Output Delay and Fall Time are Independently Adjustable These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant 8 A3 MG G US8 US SUFFIX CASE 493 1 A3 M G = Device Code = Date Code* = Pb−Free Package (Note: Microdot may be in either location) *Date Code orientation may vary depending upon manufacturing location. Typical Applications • TFT LCDs Important Information ORDERING INFORMATION • ESD Protection for All Pins: See detailed ordering and shipping information on page 10 of this data sheet. Human Body Model (HBM) > 3000 V VGH VFLK 1 8 High Voltage Power Supply VGH_M GND High Voltage Output Signal 2 Low Voltage Input Signal VDPM RE 3 7 Falling Edge Control 6 Low Voltage Power Supply CE 4 VDD Propagation Delay Control 5 Figure 1. Block Diagram © Semiconductor Components Industries, LLC, 2015 November, 2015 − Rev. 0 1 Publication Order Number: NLHVQ011/D NLHVQ011 PIN DESCRIPTION Pin Pin Name Pin Function 1 VGH Power Supply Input Comment 2 VGH_M Output 3 RE RE pin used to set the falling edge time (tfall) 4 CE CE pin used to set the propagation delay time (tphl) 5 VDD Reference to input The reference input pin is used to reduce flicker. The reference input voltage is as follows: VDD ≤ VGH – 8.5 V, VDD = 0 to 25 V 6 VDPM Signal input 1 VDPM single input voltage is as follows: VDPM = 0 V to VGH. The VDPM pin is used to create a delay with the VGH to prevent system latch−up. VDPM also determines the time VGH is ON. 7 GND Ground 8 VFLK Signal input 2 VGH = 15 to 38 V This output directly drives the power supply of Gate Driver IC The Delay time is programmed by connecting resistor RE to VGH and capacitor CE to ground. VFLK single input voltage is as follows: VDPM = 0 V to VGH. The VFLK determines the ON/OFF time of the TFT LCD and is produced from LCD timing controller module. Figure 2. Block Diagram www.onsemi.com 2 NLHVQ011 ABSOLUTE MAXIMUM RATINGS Symbol Value Unit VGH DC Supply Voltage Parameter Condition −0.5 to +40 V VDD DC Supply Voltage −0.5 to +40 V VFLK Input Voltage VFLK −0.5 to +40 V VDPM Input Voltage VDPM −0.5 to +40 V IIK DC Input Diode Current ±50 mA IOK DC Output Diode Current ±50 mA IO DC Output Current 50 mA IGH DC Supply Current Per Supply Pin 50 mA PD Power Dissipation 200 mW TJ Junction Temperature 150 ºC TSTG Storage Temperature −65 to +150 ºC Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. RECOMMENDED OPERATING CONDITIONS Symbol Parameter Test Condition Min Typ Max Unit VGH DC Supply Voltage (Note 1) VGH – VDD ≥ 8.5 V 15 − 38 V VDD DC Supply Voltage VDD ≤ VGH – 8.5 V 0 − 25 V VFLK Input Voltage VFLK VGH_M = VGH – 1.2 V 1.5 − VGH V VDPM Input Voltage VDPM VGH_M = VDD + 1.5 V 0 − VGH V −40 − 125 V − ms / V TA Dt / DVGH Operating Temperature Range CE = 5 pF 0.2 CE = 10 pF 0.4 CE = 50 pF 0.6 CE = 150 pF Safe VGH Power−Up Slew Rate (Note 2) − 0.7 CE = 220 pF 0.8 CE = 500 pF 1.2 CE = 1000 pF 2.2 1. Maximum recommended VGH supply voltage guaranteed by design. 2. It is recommended that a ceramic or tantalum decoupling capacitor of 0.1 to 1 mF is used on the VGH power supply voltage. The capacitor should be placed adjacent to the NLHVQ011 and connected between VGH and Ground. www.onsemi.com 3 NLHVQ011 ELECTRICAL CHARACTERISTICS (VGH = 20 V, VDD = 10 V, VDPM = 2.2 V, VFLK = 2.2 V, VGH − VDD ≥ 8.5 V, Ta = 25 °C, unless otherwise noted.) Symbol Parameter Test Condition Min Typ Max Unit VFLK_H FLK High Voltage VGH_M = VGH − 1.6 1.5 − VGH V VFLK_L FLK Low Voltage VGH_M = VDD + 1.5 0 − 0.5 V VDPM_H DPM High Voltage VFLK = 0 V, VGH_M = VDD – 0.2 V 1.5 − VGH V VDPM_L DPM Low Voltage VFLK = 0 V, VGH_M ≤ 0.6 V 0 − 0.5 V IDPM DPM ON Current RC RC (Resistor of VDPM pin) VFLK = 3 V, VGH_M = VGH 0.2 0.4 2 mA VGH = 22 V, RC ≈ (VGH − 0.9) / IDPM (Application Circuits 2 and 3) 10 45 100 kW VGH – 1.6 VGH − 0.7 − V − − 0.6 V VDPM = 3 V, VFLK = 0 V, IO = −1 m A VDD − 0.2 VDD + 0.3 VDD + 0.8 V VGH = 35 V, VDD = 15 V, VFLK = VDPM = 3.3 V, IO = 0 − 3.5 − mA VGH = 35 V, VDD = 15 V, VFLK = 0 V, VDPM = 3.3 V, IO = 0 − 40 − mA VGH_M, H Output High Voltage IO = 10 mA VGH_M, R Output Reset Voltage VDPM = 0 V, VFLK = 3 V VDPM = 0 V, VFLK = 0 V VGH_M, L Output Low Voltage IGH Power Supply Input Current IDD Reference Input Current Figure 3. Input and Output Waveforms (Application Circuit #1) www.onsemi.com 4 NLHVQ011 Figure 4. Input and Output Waveforms (Application Circuit #2) www.onsemi.com 5 NLHVQ011 Figure 5. VGH_M Output Propagation Delay (tphl) is controlled by CE (Application Circuit #1, VGH = 18 V, VDD = 7 V, RE = 3.9 kW, RL = 15 kW, CL = 220 pF, Ta = 25 5C) Figure 6. VGH_M Output Transition Falling Edge (tfall) is controlled by RE (Application Circuit #1, VGH = 18 V, VDD = 7 V, CE = 47 pF, RL = 15 kW, CL = 220 pF, Ta = 25 5C) www.onsemi.com 6 NLHVQ011 Figure 7. Definition of Delay Time tD1 = Delay Time 1 (tD_50−50) = VFLK_50% to [VDD + ((VGH_M_H) – VDD) x 0.50)] tD2 = Delay Time 2 (tD_50−15) = VFLK_50% to [VDD + ((VGH_M_H) – VDD) x 0.15)] tfall = 90−to−10% Fall Time = [VDD + ((VGH_M_H) – VDD) x 0.90)] − [VDD + ((VGH_M_H) – VDD) x 0.10)] DELAY TIME CHARACTERISTICS (Application Circuit #1, VDPM = 3 V, VFLK = 3 V, RE = 15 kW, RL = 15 kW, CL = 220 pF, TA = 25°C) Parameter Delay Time 2 (tD_50−15) Test Condition Typ Unit VGH = 17 V, VDD = 6.7 V, CE = 100 pF 2.4 ms VGH = 17 V, VDD = 6.7 V, CE = 240 pF 2.8 ms VGH = 22.4 V, VDD = 10 V, CE = 91 pF 2.3 ms VGH = 22 V, VDD = 10 V, CE = 220 pF 2.8 ms VGH = 25.4 V, VDD = 15.4 V, CE = 56 pF 2.4 ms VGH = 25.4 V, VDD = 15.4 V, CE = 130 pF 2.5 ms www.onsemi.com 7 NLHVQ011 Figure 8. Application #1 Circuit Schematic Notes: 1. VDPM can rise only after VGH is valid. www.onsemi.com 8 NLHVQ011 Figure 9. Application #2 Circuit Schematic Notes: 1. VDPM is produced by a Low Pass Filter (LPF) on VGH pin with RC and CD. 2. RD is a VDPM pull−down resistor. APPLICATION 2: VGH_M SIGNAL DELAY TIME CHARACTERISTICS VGH (V) 22 VDD (V) 12 CD (mF) RD (kW) RC (kW) VGH_M ON Delay Time (when VGH ON) ton (ms) VDPM Pin Discharge Time (when VGH OFF) toff (ms) 1 15 50 17.9 3.4 1 1.5 20 5.5 1.4 1 0.620 10 1.7 0.74 APPLICATION 2: FUNCTION DESCRIPTION Name RC Comment Function RC and CD determines the time when the VDPM pin is charged. ton = Time when VGH_M is high toff = Time when VDPM pin is fully discharged CD RD RD determines the time when the VDPM pin is discharged. www.onsemi.com 9 NLHVQ011 Figure 10. Application #3 Circuit Schematic APPLICATION 3: FUNCTION DESCRIPTION Name RA Comment Function RA and RB set the VDD voltage. VDD = VGH x (RB / (RA + RB)) RB RC RC determines the voltage that VDPM pin becomes high. Notes: 1. VDPM produced by external RC and internal R and C. 2. VDD created from external resistors RA and RB. 3. VGH should be higher than 18 V to meet VDPM_H. 4. RA = 15 kW, RB = 10 kW, RC = 45 kW, RE = 15 kW, RL = 15 kW, CE = 220 pF, CL = 100 pF DEVICE ORDERING INFORMATION Device Order Number NLHVQ011USG Package Type Shipping† US8 (Pb−Free) 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 10 NLHVQ011 PACKAGE DIMENSIONS US8 CASE 493−02 ISSUE B −X− A 8 −Y− 5 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION “A” DOES NOT INCLUDE MOLD FLASH, PROTRUSION OR GATE BURR. MOLD FLASH. PROTRUSION AND GATE BURR SHALL NOT EXCEED 0.140 MM (0.0055”) PER SIDE. 4. DIMENSION “B” DOES NOT INCLUDE INTER− LEAD FLASH OR PROTRUSION. INTER−LEAD FLASH AND PROTRUSION SHALL NOT E3XCEED 0.140 (0.0055”) PER SIDE. 5. LEAD FINISH IS SOLDER PLATING WITH THICKNESS OF 0.0076−0.0203 MM. (300−800 “). 6. ALL TOLERANCE UNLESS OTHERWISE SPECIFIED ±0.0508 (0.0002 “). J DETAIL E B L 1 4 R S G P U C −T− SEATING PLANE K D H 0.10 (0.004) T N R 0.10 TYP 0.10 (0.004) M T X Y V M F DETAIL E MILLIMETERS MIN MAX 1.90 2.10 2.20 2.40 0.60 0.90 0.17 0.25 0.20 0.35 0.50 BSC 0.40 REF 0.10 0.18 0.00 0.10 3.00 3.20 0_ 6_ 5_ 10 _ 0.23 0.34 0.23 0.33 0.37 0.47 0.60 0.80 0.12 BSC DIM A B C D F G H J K L M N P R S U V INCHES MIN MAX 0.075 0.083 0.087 0.094 0.024 0.035 0.007 0.010 0.008 0.014 0.020 BSC 0.016 REF 0.004 0.007 0.000 0.004 0.118 0.126 0_ 6_ 5_ 10 _ 0.010 0.013 0.009 0.013 0.015 0.019 0.024 0.031 0.005 BSC SOLDERING FOOTPRINT* 3.8 0.15 0.50 0.0197 1.8 0.07 0.30 0.012 1.0 0.0394 SCALE 8:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 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