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Digital Integrated Circuits A Design Perspective Designing g g Combinational Logic Circuits Fuyuzhuo School of Microelectronics,SJTU Introduction Digital IC homework • Sketch a 4-input NAND gate with transistor widths chosen to achieve effective rise and fall resistance equal to a unit inverter. • Compute the rising and falling propagation delays(in terms of R and C) of the NAND gate driving h identical NAND gates using the ELMORE delay y model • Compute the rising and falling contamination delays(in terms of R and C) of the NAND gate driving h identical NAND gates using the ELMORE delay model • If C=2fF/um and R=2.5kohm.um in a 180nm, what is the delay of a fanout-of-3 NAND gate? Digital IC 2 • Select gate sizes x and y for least delay from A to B Digital IC 3 • Consider four designs of a 6-input AND gate shown in figure. Develop and expression for delay of each path if the path electrical effort is H. what design is fastest of H=1? For H=5? For H=20? Explain your conclusion intuitively Digital IC 4 • • Consider a process in which pMOS transistors have three times the effective ff ti resistance i t as nMOS MOS transistors. t i t A unitit inverter i t with ith equall rising and falling delays in this process is shown in figure. Calculate the logical efforts of a 2-input NAND gate and a 2-input NOR gate if they are designed with equal rising and falling delays Generalize the model if the pMOS transistors have u times the effective resistance of nMOS transistors. transistors Find a general expression for the logical efforts of a k-input NAND gate and a k-input NOR gate. As u increases, comment on the relative desirability of NANDs vs NORs vs. NORs. Digital IC 5 Example, Revisited • Ben Bitdiddle is the memory designer for the Motoroil 68W86, an embedded b dd d automotive t ti processor. H Help l B Ben d design i th the d decoder d ffor a register file. Decoder specifications: p • 16 word register file Register File • Each word is 64 bits wide • Each bit presents load of 3 unit-sized transistors • True and complementary address inputs A[3:0] • Each input may drive 10 unit unit-sized sized transistors Ben needs to decide: • How many y stages g to use? • How large should each gate be? • How fast can decoder operate? A[3:0] A[3:0] 32 bits • Digital IC 16 words 4:16 Decoder • 16 6 • Find the worst-case ELMORE parasitic delay of an ninput NOR gate Digital IC 7 • Design a 4-input footed dynamic NAND gate driving an electrical effort of 1. estimate the worst charge sharing noise as a fraction of Vdd assuming that diffusion capacitance on uncontacted nodes is about half of gate capacitance and on contacted nodes it equals gate capacitance. Digital IC 8 • Design a k-input AND gate with DeMorgan’s law using static CMOS inverters followed by a k-input pseudonMOS NOR,as shown in figure. Let each inverter be unit sized If the output load is an inverter of size H unit-sized. H, determine the best transistor sizes in the NOR gate and estimate the average delay of the path Digital IC 9