Download Metallurgical-grade silicon (MGS)

How to make VLSI Chip
Nida rehman
Lect EC Dept, ASCT Bhopal
ABASTACT Very-large-scale integration
(VLSI) is the process of creating
integrated circuits by combining
thousands of transistor-based circuits
into a single chip.VLSI is a process that can
be employed in several different ways. When it
comes to the production of semiconductor
chips, the process provides the ideal means of
including huge numbers of logic elements and
memory capacity on one single chip. This one
simple application helped to make desktop
computers more powerful than ever, as well as
setting the stage for the utilization of resources
that make online video and other high
resource applications possible.
INTRODUCTION
VLSI stands for "Very Large Scale
Integration". This is the field which
involves packing more and more logic
devices into smaller and smaller
areas.Thanks to VLSI, circuits that
would have taken boardfuls of space can
now be put into a small space few
millimeters across! This has opened up a
big opportunity to do things that were
not possible before. VLSI circuits are
everywhere ... your computer, your car,
your brand new state-of-the-art digital
camera, the cell-phones, and what have
you. All this involves a lot of expertise
on many fronts within the same field,
which we will look at in later sections.
VLSI began in the 1970s when complex
semiconductor and communication
technologies were being developed. The
microprocessor is a VLSI device. The
term is no longer as common as it once
was, as chips have increased in
complexity into billions of transistors.
Metallurgical-grade
silicon (MGS)
The typical source material for
commercial production of elemental
silicon is quartzite gravel; a relatively
pure form of sand (SiO2). The first step
in the synthesis of silicon is the melting
and reduction of the silica in a
submerged-electrode arc furnace. A
mixture of quartzite gravel and carbon
are heated to high temperatures (ca.
1800 °C) in the furnace. The carbon bed
consists of a mixture of coal, coke, and
wood chips. The latter providing the
necessary porosity such that the gases
created during the reaction (SiO and CO)
are able to flow through the bed.
The overall reduction reaction of
SiO2 is expressed in Equation 1,
however, the reaction sequence is more
complex than this overall reaction
implies, and involves the formation of
SiC and SiO intermediates. The initial
reaction between molten SiO2 and C
(Equation 2) takes place in the arc
between adjacent electrodes, where the
local temperature can exceed 2000 °C.
The SiO and CO thus generated flow to
cooler zones in the furnace where SiC is
formed (Equation 3), or higher in the bed
where they reform SiO2 and C (Equation
2). The SiC reacts with molten SiO2
(Equation 4) producing the desired
silicon along with SiO and CO. The
molten silicon formed is drawn-off from
the furnace and solidified.
(1)
(2)
(3)
(4)
The as-produced MGS is approximately
98-99% pure, with the major impurities
being aluminum and iron; however,
obtaining low levels of boron impurities
is of particular importance, because it is
difficult to remove and serves as a
dopant for silicon. The drawbacks of the
above process are that it is energy and
raw material intensive. It is estimated
that the production of one metric ton
(1,000 kg) of MGS requires 2500-2700
kg quartzite, 600 kg charcoal, 600-700
kg coal or coke, 300-500 kg wood chips,
and 500,000 kWh of electric power.
Currently, approximately 500,000 metric
tons of MGS are produced per year,
worldwide. Most of the production (ca.
70%) is used for metallurgical
applications (e.g., aluminum-silicon
alloys are commonly used for
automotive engine blocks) from whence
its name is derived. Applications in a
variety of chemical products such as
silicone resins account for about 30%,
and only 1% or less of the total
production of MGS is used in the
manufacturing of high-purity EGS for
the electronics industry. The current
worldwide consumption of EGS is
approximately 5 x 10 6 kg per year.
Electronic-grade
(EGS)
silicon
Electronic-grade silicon (EGS) is a
polycrystalline material of exceptionally
high purity and is the raw material for
the growth of single-crystal silicon. EGS
is one of the purest materials commonly
available. The formation of EGS from
MGS is accomplished through chemical
purification processes. The basic concept
of which involves the conversion of
MGS to volatile silicon compound,
which is purified by distillation, and
subsequently decomposed to re-form
elemental silicon of higher purity (i.e.,
EGS). Irrespective of the purification
route employed, the first step is physical
pulverization of MGS followed by its
conversion to the volatile silicon
compounds.
Crystallization
Silicon crystallizes in the diamond cubic
crystal structure
Silicon, like carbon and other group IV
elements form face-centered diamond
cubic crystal structure. Silicon, in
particular, forms a face-centered cubic
structure with a lattice spacing of
5.430710 Å (0.5430710 nm).
The majority of silicon crystals grown
for device production are produced by
the Czochralski process, (CZ-Si) since it
is the cheapest method available and it is
capable of producing large size crystals.
However, silicon single-crystals grown
by the Czochralski method contain
impurities since the crucible which
contains the melt dissolves. For certain
electronic devices, particularly those
required for high power applications,
silicon grown by the Czochralski method
is not pure enough. For these
applications, float-zone silicon (FZ-Si)
can be used instead. It is worth
mentioning though, in contrast with CZSi method in which the seed is dipped
into the silicon melt and the growing
crystal is pulled upward, the thin seed
crystal in the FZ-Si method sustains the
growing crystal as well as the
polysilicon rod from the bottom. As a
result, it is difficult to grow large size
crystals using the float-zone method.
Today, all the dislocation-free silicon
crystals used in semiconductor industry
with diameter 300 mm or larger are
grown by the Czochralski method with
purity level significantly improved.
Purification
The use of silicon in semiconductor
devices demands a much greater purity
than afforded by metallurgical grade
silicon. Historically, a number of
methods have been used to produce
high-purity silicon.
Physical methods
Early silicon purification techniques
were based on the fact that if silicon is
melted and re-solidified, the last parts of
the mass to solidify contain most of the
impurities. The earliest method of silicon
purification, first described in 1919 and
used on a limited basis to make radar
components during World War II,
involved crushing metallurgical grade
silicon and then partially dissolving the
silicon powder in an acid. When
crushed, the silicon cracked so that the
weaker impurity-rich regions were on
the outside of the resulting grains of
silicon. As a result, the impurity-rich
silicon was the first to be dissolved when
treated with acid, leaving behind a more
pure product.
In zone melting, also called zone
refining, the first silicon purification
method to be widely used industrially,
rods of metallurgical grade silicon are
heated to melt at one end. Then, the
heater is slowly moved down the length
of the rod, keeping a small length of the
rod molten as the silicon cools and resolidifies behind it. Since most
impurities tend to remain in the molten
region rather than re-solidify, when the
process is complete, most of the
impurities in the rod will have been
moved into the end that was the last to
be melted. This end is then cut off and
discarded, and the process repeated if a
still higher purity is desired.
Chemical methods
Today, silicon is purified by converting
it to a silicon compound that can be
more easily purified by distillation than
in its original state, and then converting
that silicon compound back into pure
silicon. Trichlorosilane is the silicon
compound most commonly used as the
intermediate,
although
silicon
tetrachloride and silane are also used.
When these gases are blown over silicon
at high temperature, they decompose to
high-purity silicon.
At one time, DuPont produced ultra-pure
silicon by reacting silicon tetrachloride
with high-purity zinc vapors at 950 °C,
producing silicon:
Oxygen
Silicon
SiCl4 + 2 Zn → Si + 2 ZnCl2
However, this technique was plagued
with practical problems (such as the zinc
chloride byproduct solidifying and
clogging lines) and was eventually
abandoned in favor of the Siemens
process.
In the Siemens process, high-purity
silicon rods are exposed to tri-chlorosilane at 1150 °C. The trichlorosilane
gas decomposes and deposits additional
silicon onto the rods, enlarging them:
2 HSiCl3 → Si + 2 HCl + SiCl4
Silicon produced from this and a similar
process is called polycrystalline silicon.
Polycrystalline silicon typically has
impurity levels of less than 10−9.
In 2006 REC announced construction of
a plant based on fluidized bed
technology using silane:
3 SiCl4 + Si + 2 H2 → 4 HSiCl3
4 HSiCl3 → 3 SiCl4 + SiH4
SiH4 → Si + 2 H2
Oxidation:
Thermal oxides are grown on Silicon at
temperature ranges between 750oC and
1100oC. When Silicon is exposed to
oxygen, a layer of amorphous silicon
dioxide grows.
Atomic Structure of Silicon Dioxide
SiO2 is a dielectric, or a non-conductor.
It has a melting point at 1732 oC. When
it is grown thermally, it adheres very
well to Silicon as well. Oxide layers
have many purposes, to act as surface
passivation, dielectric materiel in the
gate structure, device protection,
impurity mask during doping, and acting
as an insulating layer between metal
conducting paths.
In our process, a dry, wet,
dry thermal oxidation is used. There is
one hour of dry oxidation, three hours of
wet oxidation, and one hour of final dry
oxidation. The wet oxidation has a
solution of HCl:H2O in a 1:15 ratio, in a
250 mL bubbler. The temperature in the
furnace is set to 1100 oC.
The dry oxidation grows very pure SiO2
depending on the wafer surface quality,
and purity of the O2 supply.
Si (solid) + O2 (gas)  SiO2 (solid)
The wet reaction is:
Si (solid) + 2H2O (vapor)  SiO2
(Solid) + 2H2 (gas)
The water vapor has a faster rate of
diffusion and higher solubility that
causes an increase in the rate of oxide
growth. However, the materiel grown is
porous and contains impurities as a
result of hydrogen contamination. The
HCl is included in the solution in order
to pacify fixed oxide charges. Fixed
oxide charges result at the sharp
transition in the oxide-silicon interface.
Un-bonded Si atoms on the surface form
positive charges. The chlorine ions
diffuse towards the positive layer, and
form a neutral layer at the oxide-silicon
interface.
Silicon dioxide growth
results when silicon is consumed in the
chemical reaction. Oxide growth is
controlled by how well oxygen is
coming in contact with the silicon.
When oxygen has trouble diffusing
through the layer of previously grown
oxide, the growth rate of the oxide
slows. Diffusion rates are increased by
thermal energy, and large differences in
atom densities.
Photolithography:
Photolithography is a very important
process in the manufacturing of a
semiconductor device. Many factors can
be a factor here, such as feature size,
tolerances of alignment, number of
masking layers, and the cleanliness of
the wafer surface. There are eight main
steps involved in the photolithography
process. They are a vapor prime, spin
coat of photo-resist, the soft bake,
alignment of mask and exposure, postexposure bake, development, hard
baking, and inspection of the
development.
For
the
first
photolithography process, the sources
and drains needed to be defined by
opening up the field oxide, so that
dopants can be diffused into the source
and drain. The first step is to clean the
wafer with acetone and methanol; this
cleans the wafer to remove any
contaminants, something that is always
undesirable. Then the wafer is mounted
on a vacuum chuck. The wafer is then
primed
with
hexamethyldisilazane
(HMDS), which helps the photoresist to
adhere to the wafer surface. Photoresist
is poured on the surface of the wafer,
which is then spun at high rpm, so that
the resist is evenly spread over the
surface of the wafer. In our lab process,
the wafer is spun for 40 seconds and
5000 rpm for both the prime and spin
coat steps. The photoresist (PR) is then
put through a soft bake to drive out the
solvent from the PR. The uniformity of
the resist, as well as the quality of
adhesion is improved by the soft-bake.
This also allows better linewidth control
during photolithography. The bake is
done on a hot plate. This ensures that
the resist is heated from bottom to top,
and prevents bursting, as solvent under
hardened PR evaporates, and “bursts”
through the surface. The soft-bake is
done at 90oC for 90 seconds.
Etching/Diffusion:
Opening up windows in the PR now
allows underlying oxide to be selectively
etched away. A wet, isotropic, buffered
oxide etch (BOE), also known as a
buffered hydrofluoric acid etch (BHF), is
used to remove the oxide. A solution of
HF and ammonium fluoride (NH4F) is
used to remove the oxide, to define the
source and drains. The buffer keeps the
etch slow and controlled, and does not
attack the photoresist. Also, since SiO2
is an amorphous materiel, it etches
equally well in all dimensions, so that it
etches laterally beneath the mask
materiel. This lateral undercutting limits
the amount of lines and spaces you can
have in a given area. Then a standard
RCA clean is done to remove the
remaining PR.
Isotropic Wet Etch
In order to create a pn junction, an Ntype “well” must be created in the p +
substrate. This is done by diffusing ntype dopant into the substrate through
the oxide windows that were opened up
in the lithography step. Phosphorous
was used as the dopant, in a gas form in
a high temperature furnace. Dopant gas
is put into the furnace, and comes in
contact with the surface of the substrate,
and begins to diffuse into the wafer.
After 5 minutes of bubbling N2 through
POCl3, there are two drive-in steps,
using N2 for 20 minutes, and O2 for 20
minutes. The dopant atoms diffuse into
the wafer creating our pn junctions.
The gate oxide is grown
thermally with dry oxidation. It is very
important that the gate oxide remains as
pure as possible. Any particles or
defects in the gate oxide can lead to
trapped charges, which can lead to gate
oxide integrity breakdown, as well as
letting small amounts of current through
the device. A dry oxidation for two
hours at 950oC is used to grow the oxide.
However, due to equipment problems, a
furnace used for other purposes was
used, that could have possibly
contaminated the gate oxide with carbon
particles.
Ohmic contact masks
metallization masks:
and
Now that the device structure is in
place, the last step is to prepare for
laying down metal contacts so that the
device can be tested. The process
involves two more lithography steps, a
BOE. For the metallization, the PR from
the second lithography acts as the mask.
The first lithography step is the ohmic
contact mask. This creates two vias that
open up to the source and drain, so that
they can be contacted with a metal pad.
The photoresist is removed, and then
there is a standard RCA clean. The next
step is a second lithography step.
However, for the metallization mask, a
negative photoresist is used. Negative
photoresist works in the opposite manner
of positive photoresist. With positive
PR, when UV light interacts with the
PR, it breaks the bonds in the resist. In
negative resist, the resist is soluble in
developer until it has been exposed to
light.
For the metallization mask, holes
are opened up in the photoresist above
the drain, source and gate.
The
photoresist alone acts as a mask for the
metallization process. With negative
photoresist, the development time is
critical. NR7-1500PY PR resist is used,
spin coated, soft baked, exposed,
subjected to a post exposure 60 second
bake at 130oC, and developed in DR6 for
ten seconds.
After
the
development,
metallization is done to provide ohmic
contacts for the drain, gate, and source.
The wafer is placed inside the
metallization chamber, which is an
evaporation system. The chamber is
pumped down to 2x10-6 torr, and then
200 nm of aluminum is deposited on the
wafer. With evaporation metallization,
the Al is placed in a crucible beneath the
wafer. The metal is heated until it
evaporates, and the metal vapor travels
upward, contacting the wafer, and
condenses to form a film.
Liftoff is the final fabrication
step. It involves removing the remaining
photoresist on the wafer surface. As the
solvent removed the PR, the metal layer
on top of it also comes off, leaving metal
only on the areas defined by the
metallization mask.
The liftoff is
composed of a 15 minutes acetone rinse
with agitation, followed by a 20 second
methanol rinse, a DI rinse, and a N2
blow dry. The device is now complete
and ready for testing.
Testing and Analysis:
Our device was tested by randomly
contacting a three point probe on the
drain, source, and gate. Several gate
voltages are applied to the gate, as the
drain-source voltage is swept over a
range, and the drain-source current is
measured. This testing results in the IVcharacteristic curves of the transistors.
Analysis and Conclusion:
The critical factor in the failure of the
device would be the lack of proper
diffusion and gate oxidation equipment.
Due to equipment restrictions within the
laboratory, the device was doped with a
spin on glass (SOG) method. A SOG
with dopant is spun onto the wafer much
like photoresist. The dopant is then
“driven in” with a heating process, and
the device is doped. This method had
not been performed by the TA of the lab
before, and was quite possibly not done
correctly. Secondly, the gate oxide was
grown in a furnace that is contaminated
with carbon.
Carbon contamination
within the gate oxide is also a likely
failure mechanism within the devices.
Overall, the process steps which could
be completed properly were executed
well, and with precision. If anything,
this lab shows the vulnerability of an IC
fabrication to the smallest contamination
or process difficulty, and the importance
of strict laboratory practices and
cleanliness.
Reference:
1. VLSI Technology by Sujata Pandey
and Manoj Pandey
2. www.ieee.org
3. www.epfl.ch
4. Principles of CMOS VLSI Design
Neil H.E.Weste Kamran Eshraghian