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CA1524, CA2524
CA3524
TE
LE
BSO
524
CA2
NO
IS A
T
DUC
PRO
Regulating Pulse Width Modulator
October 2000
Features
Description
• Complete PWM Power Control Circuitry
The CA1524 and CA3524 are silicon monolithic integrated
circuits designed to provide all the control circuitry for use in
a broad range of switching regulator circuits.
• Separate Outputs for Single-Ended or Push-Pull
Operation
The CA1524 and CA3524 have all the features of the industry types SG1524, SG2524, and SG3524, respectively. A
block diagram of the CA1524 series is shown in Figure 1.
The circuit includes a zener voltage reference, transconductance error amplifier, precision R-C oscillator, pulse-width
modulator, pulse-steering flip-flop, dual alternating output
switches, and current-limiting and shutdown circuitry. This
device can be used for switching regulators of either polarity,
transformer-coupled dc-dc converter, transformerless voltage doublers, dc-ac power inverters, highly efficient variable
power supplies, and polarity converter, as well as other
power-control applications.
• Line and Load Regulation . . . . . . . . . . . . . . . 0.2% (Typ)
• Internal Reference Supply with 1% (Max) Oscillator
and Reference Voltage Variation Over Full
Temperature Range
• Standby Current of Less Than 10mA
• Frequency of Operation Beyond 100kHz
• Variable-Output Dead Time of 0.5µs to 5µs
• Low VCE(sat) Over the Temperature Range
Applications
Ordering Information
• Positive and Negative Regulated Supplies
PART
NUMBER
• Dual-Output Regulators
• Flyback Converters
• DC-DC Transformer-Coupled Regulating Converters
• Single-Ended DC-DC Converters
• Variable Power Supplies
TEMPERATURE
RANGE
CA1524E
-55oC
CA1524F
-55oC
CA2524E
0oC
CA2524F
0oC
CA3524E
0oC
CA3524F
0oC
PACKAGE
to
+125oC
16 Lead Plastic DIP
to
+125oC
16 Lead CerDIP
to
+70oC
16 Lead Plastic DIP
to
+70oC
16 Lead CerDIP
to
+70oC
16 Lead Plastic DIP
to
+70oC
16 Lead CerDIP
Pinout
CA1524, CA3524
(PDIP, CERDIP)
TOP VIEW
INV. INPUT
1
16
VREF
NONINV. INPUT
2
15
V+
OSC OUT
3
14
EMITTER B
4
13
COLLECTOR B
5
12
COLLECTOR A
RT
6
11
EMITTER A
CT
7
10
SHUTDOWN
GND
8
9
(+) C.L.
SENSE
(-) C.L.
SENSE
COMPENSATION
AND COMPARATOR
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 2000
1
File Number
1239.4
CA1524, CA2524, CA3524
Functional Block Diagram
15
V+
REFERENCE
REGULATOR
5V
+5V TO ALL
INTERNAL CIRCUITS
CA
+5V
12
16
VREF
FLIP
FLOP
SA
11
3
OSC OUT
EA
+5V
CB
13
OSCILLATOR
6
RT
SB
+5V
7
CT
+5V
14
COMPARATOR
-
1
INV. INPUT
+
C.L.
-
ERROR
AMP
+
2
EB
+5V
+ SENSE
4
5
- SENSE
NON-INV.
INPUT
1kΩ
10
9
SHUTDOWN
COMPENSATION AND COMPARATOR
10kΩ
8
GND
Test Circuit
8 - 40V
2kΩ
1W
ls
V+
2kΩ
1W
12
OUT A
13
OUT B
15
CA1524
3
11
16
14
8
6
7
2
1
9
2kΩ
0.1µF
RT
CT
10
2kΩ
4
10
kΩ
10kΩ
1kΩ
2kΩ
2
5
Specifications CA1524, CA2524, CA3524
Absolute Maximum Ratings
Thermal Information
Input Voltage (Between VIN and GND Terminals). . . . . . . . . . . . 40V
Operating Voltage Range (VIN to GND) . . . . . . . . . . . . . . . . 8 to 40V
Output Current Each Output:
(Terminal 11, 12 or 13, 14) . . . . . . . . . . . . . . . . . . . . . . . . . 100mA
Output Current (Reference Regulator) . . . . . . . . . . . . . . . . . . . 50mA
Oscillator Charging Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
Thermal Resistance
θJA
Plastic DIP Package . . . . . . . . . . . . . . . . . . . . . . . . 100oC/W
Device Dissipation
Up to TA = +25oC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.25W
Above TA = +25oC . . . . . . . . . . . . . . .Derate Linearly at 10mW/oC
Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC
Storage Temperature Range . . . . . . . . . . . . . . . . . . -65oC to +150oC
Lead Temperature (During Soldering)
At distance 1/16 ± in. (1.59mm ±0.79mm)
from case for 10s Max . . . . . . . . . . . . . . . . . . . . . . . . . . . . +265oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications
TA = -550C to +125oC for CA1524, 0oC to +70oC for the CA2524 and CA3524; V+ = 20V and
f = 20kHz, Unless Otherwise Stated.
CA1524, CA2524
PARAMETER
TEST CONDITIONS
CA3524
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
4.8
5
5.2
4.6
5
5.4
V
-
10
20
-
10
30
mV
-
20
50
-
20
50
mV
-
66
-
-
66
-
db
-
100
-
-
100
-
mA
REFERENCE SECTION
Output Voltage
Line Regulation
V+ = 8 to 40V
Load Regulation
IL = 0 to 20mA
Ripple Rejection
f = 120Hz, TA =
25oC
25oC
Short Circuit Current Limit
VREF = 0, TA =
Temperature Stability
Over Operating Temperature
Range
-
0.3
1
-
0.3
1
%
Long Term Stability
TA = 25oC
-
20
-
-
20
-
mV/khr
Maximum Frequency
CT = 0.001µF, RT = 2KΩ
-
300
-
-
300
-
kHz
Initial Accuracy
RT and CT Constant
-
5
-
-
5
-
%
-
-
1
-
-
1
%
OSCILLATOR SECTION
25oC
Voltage Stability
V+ = 8 to 40V, TA =
Temperature Stability
Over Operating Temperature
Range
-
-
2
-
-
2
%
Output Amplitude
Terminal 3, TA = 25oC
-
3.5
-
-
3.5
-
V
-
0.5
-
-
0.5
-
µs
25oC
Output Pulse Width (Pin 3)
CT = 0.01µF, TA =
Ramp Voltage Low (Note 1)
Pin 7
-
0.6
-
-
0.6
-
V
Ramp Voltage High (Note 1)
Pin 7
-
3.5
-
-
3.5
-
V
Capacitor Charging Current Range
Pin 7 (5-2 VBE)/RT
0.03
-
2
0.03
-
2
mA
Timing Resistance Range
Pin 6
1.8
-
120
1.8
-
120
kΩ
Charging Capacitor Range
Pin 7
0.001
-
0.1
0.001
-
0.1
µF
Dead Time Expansion Capacitor on
Pin 3 (when a small osc. cap is used)
Pin 3
100
-
1000
100
-
1000
pF
ERROR AMPLIFIER SECTION
Input Offset Voltage
VCM = 2.5V
-
0.5
5
-
2
10
mV
Input Bias Current
VCM = 2.5V
-
1
10
-
1
10
µA
72
80
-
60
80
-
dB
1.8
-
3.4
1.8
-
3.4
V
-
70
-
-
70
-
dB
-
3
-
-
3
-
MHz
Open Loop Voltage Gain
Common Mode Voltage
Common Mode Rejection Ratio
Small Signal Bandwidth
TA =
25oC
TA =
25oC
AV = 0dB, TA =
25oC
3
Specifications CA1524, CA2524, CA3524
Electrical Specifications
TA = -550C to +125oC for CA1524, 0oC to +70oC for the CA2524 and CA3524; V+ = 20V and
f = 20kHz, Unless Otherwise Stated. (Continued)
CA1524, CA2524
PARAMETER
CA3524
TEST CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
25oC
0.5
-
3.8
0.5
-
3.8
V
-
250
-
-
250
-
Hz
External Sink
-
200
-
-
200
-
µA
Duty Cycle
% Each Output On
0
-
45
0
-
45
%
Input Threshold
Zero Duty Cycle
-
1
-
-
1
-
V
Input Threshold
Max. Duty Cycle
-
3.5
-
-
3.5
-
V
-
1
-
-
1
-
µA
190
200
210
180
200
220
mV
Sense Voltage T.C.
-
0.2
-
-
0.2
-
mV/oC
Common Mode Voltage
-1
-
+1
-1
-
+1
V
Rolloff Pole of R51 C3 + Q64
-
300
-
-
300
-
Hz
40
-
-
40
-
-
V
Output Voltage
TA =
Amplifier Pole
Pin 9 Shutdown Current
COMPARATOR SECTION
Input Bias Current
CURRENT LIMITING SECTION
Sense Voltage for 25% Output Duty
Cycle
Terminal 9 = 2V with Error
Amplifier Set for Max Out,
TA = 25oC
OUTPUT SECTION (EACH OUTUT)
Collector-Emitter Voltage
Collector Leakage Current
VCE = 40V
-
0.1
50
-
0.1
50
µA
Saturation Voltage
V+ = 40V, IC = 50mA
-
0.8
2
-
0.8
2
V
Emitter Output Voltage
V+ = 20V
17
18
-
17
18
-
V
RC = 2KΩ, TA =
25oC
-
0.2
-
-
0.2
-
µs
Fall Time
RC = 2KΩ, TA =
25oC
-
0.1
-
-
0.1
-
µs
Total Standby Current: (Note 2) IS
V+ = 40V
-
4
10
-
4
10
mA
Rise Time
NOTES:
1. Ramp voltage at Pin 7
High
where t = OSC period in microseconds
t ≅ RTCT with CT in microfarads and RT in ohms.
t
Output frequency at each output transistor is half OSC frequency when each output is used separately and is equal to the OSC frequency
when each output is connected in parallel.
Low
2. Excluding oscillator charging current, error and current limit dividers, and with outputs open.
4
CA1524, CA2524, CA3524
Schematic Diagram
15 VIN
A
R1
500
R5
1K
R7
1K
B
Q1
Q2
Q13
Q7
Q17
Q6
Q18
R12
10K
Q3 Q4
Q9
C1
20pF
Q16
R11
500
R2
2.7K
R13
6Ω
RD
R16
16.2K
Q10
RC
10K
R3
6.3K
16
10K
1.9K
Q11
VREF
+5V
R14
450
R17 R18
18.7 18.7
K
K
C4
D2
D1
Q19
PULSE
STEERING
FLIP-FLOP
RA
5.3K
Q21
Q23
R8
8.4K
C
QA
RB
4.8K
R19 R18
18.7 18.7
K
K
Q5
Q12
Q14
Q15
N+
R4
500
D
E
C2
20pF
R6
500
R9
500
Q20
P
Q24
Q22
R15
25K
R10
1K
F
G
H
I
8
GND
OSC SECTION
ERROR
AMP
Q42
Q43
Q47
Q48
Q59
R43
7.4K
6
Q44
RT
Q60
Q61
Q55 INV.
IN
Q49
Q50
1
Q56 Q57
2
NON-INV.
INPUT
J
R44
1.8K
7
Q51
CT
Q58
R41
24K
Q45
R39
1K
R40
560
Q62
OSC.
OUT
Q46
Q52
R42
19.8K
3
R47
1K
R45
25K
Q53
R46
3.3K
5
R48
2K
Q54
K
L
CA1524, CA2524, CA3524
Schematic Diagram (Continued)
A
OUTPUT B
OUTPUT A
B
COLL. A
Q33
12
R33
200
Q40
Q35
R36
200
R32
1K
CA
1pF
CB
1pF
R34
500
R31
4.7Ω
D3
R35
500
D4
RE
500
RF
500
EMIT A 11
Q37
Q38
C
NOR
R21
43.3K
NOR
D
E
R23
8.7K
R25
5K
R24
5K
R30
43.3K
R26
5K
R28
8.7K
Q29
Q26
Q30
R27
5K
Q27
Q31
F
G
H
I
R52
1.96K
COMP
Q65
COMPARATOR
R54
1.96K
Q67
9
Q68
C3
45pF
R49
1K
Q68
Q70
Q71
R53
1.8K
Q64
R51
10K
Q63
Q66
Q72
CURRENT
LIMIT
SECTION
R50
10K
14
EMIT B
R37
1K
Q39
Q36
J
COLL. B
Q41
Q34
10
13
K
L
5
4
(-) C.L.
SENSE
(+) C.L.
SENSE
6
Q73
R38
4.7Ω
CA1524, CA2524, CA3524
Circuit Description
Osclllator Section
Voltage Reference Section
Transistors Q42, Q43 and Q44, in conjunction with an
external resistor RT, establishes a constant charging current
into an external capacitor CT to provide a linear ramp voltage
at terminal 7. The ramp voltage has a value that ranges from
0.6V to 3.5V and is used as the reference for the comparator
in the device. The charging current is equal to (5-2VBE)/RT or
approximately 3.6/RT and should be kept within the range of
30pA to 2mA by varying RT. The discharge time of CT determines the pulse width of the oscillator output pulse at terminal 3. This pulse has a practical range of 0.5µs to 5µs for a
capacitor range of 0.001 to 0.1µF. The pulse has two internal
uses: as a dead-time control of blanking pulse to the output
stages to assure that both outputs cannot be on simultaneously and as a trigger pulse to the internal flip-flop which
controls the switching of the output between the two output
channels. The output dead-time relationship is shown in Figure 4. Pulse widths less than 0.5µs may allow false triggering of one output by removing the blanking pulse prior to a
stable state in the flip-flop.
The CAl524 series contains an internal series voltage regulator employing a zener reference to provide a nominal 5-volt
output, which is used to bias all internal timing and control
circuitry. The output of this regulator is available at terminal
l6 and is capable of supplying up to 50mA output current.
Figure 1 shows the temperature variation of the reference
voltage with supply voltages of 8V to 40V and load currents
up to 20mA. Load regulation and line regulation curves are
shown in Figures 2 and 3, respectively.
V+ = 40V, IL = 0mA
V+ = 20V, IL = 0mA
V+ = 40V, IL = 20mA
5.00
V+ = 8V, IL = 0mA
V+ = 20V, IL = 20mA
V+ = 8V, IL = 20mA
4.98
100
4.96
TA = +25oC
-60 -40 -20
0
20
40
60
OUTPUT DEAD TIME (µs)
REFERENCE VOLTAGE (V)
5.02
80 100 120 140
AMBIENT TEMPERATURE
(oC)
FIGURE 1. TYPICAL REFERENCE VOLTAGE AS A FUNCTION
OF AMBIENT TEMPERATURE
5.1
V+ = 40V
REFERENCE VOLTAGE (V)
4.9
V+ = 8V - 40V
10
1.0
4.7
0.1
0.0001
4.5
V+ = 20V
4.3
0.001
0.01
0.1
1.0
TIMING CAPACITOR, CT (µF)
TA = +25oC
V+ = 20V
4.1
FIGURE 4. TYPICAL OUTPUT STAGE DEAD TIME AS A
FUNCTION OF TIMING CAPACITOR VALUE
3.9
V+ = 8V
3.7
If a small value of CT must be used, the pulse width can be
further expanded by the addition of a shunt capacitor in the
order of 100pF but no greater than 1000pF, from terminal 3
to ground. When the oscillator output pulse is used as a sync
input to an oscilloscope, the cable and input capacitances
may increase the pulse width slightly. A 2-KΩ resistor at
terminal 3 will usually provide sufficient decoupling of the
cable. The upper limit of the pulse width is determined by the
maximum duty cycle acceptable.
3.5
0
8
16
24
32
40
48
56
64
72
80
REFERENCE OUTPUT CURRENT (mA)
FIGURE 2. TYPICAL REFERENCE VOLTAGE AS A FUNCTION
OF REFERENCE OUTPUT CURRENT
REFERENCE VOLTAGE (V)
8
TA = +25oC
7
The oscillator period is determined by RT and CT, with an
approximate value of t = RTCT, where RT is in ohms, CT is in
µF, and t is in µs. Excess lead lengths, which produce stray
capacitances, should be avoided in connecting RT and CT to
their respective terminals. Figure 5 provides curves for
selecting these values for a wide range of oscillator periods.
For series regulator applications, the two outputs can be
connected in parallel for an effective 0-90% duty cycle with
the output stage frequency the same as the oscillator
frequency. Since the outputs are separate, push-pull and
flyback applications are possible. The flip-flop divides the
frequency such that the duty cycle of each output is 0-45%
and the overall frequency is half that of the oscillator. Curves
6
5
4
3
2
1
0
0
10
20
30
40
SUPPLY VOLTAGE, V+ (V)
FIGURE 3. TYPICAL REFERENCE VOLTAGE AS A FUNCTION
OF SUPPLY VOLTAGE
7
CA1524, CA2524, CA3524
TIMING RESISTANCE, RT (Ω)
of the output duty cycle as a function of the voltage at
terminal 9 are shown in Figure 7. To synchronize two or
more CAl524’s, one must be designated as master, with RT
CT set for the correct period. Each of the remaining units
(slaves) must have a CT of 1/2 the value used in the master
and approximately a 1010 longer RTCT period than the master. Connecting terminal 3 together on all units assures that
the master output pulse, which occurs first and has a wider
pulse width, will reset the slave units.
The output amplifier terminal is also used to compensate the
system for ac stability. The frequency response and phase
shift curves are shown in Figure 7. The uncompensated
amplifier has a single pole at approximately 250Hz and a
unity gain cross-over at 3MHz.
Since most output filter designs introduce one or more
additional poles at a lower frequency, the best network to
stabilize the system is a series RC combination at terminal9
to ground. This network should be designed to introduce a
zero to cancel out one of the output filter poles. A good starting point to determine the external poles is a 1000-pF
capacitor and a variable series 50-KΩ potentiometer from
terminal 9 to ground. The compensation point is also a
convenient place to insert any programming signal to
override the error amplifier. internal shutdown and current
limiting are also connected at terminal 9. Any external circuit
that can sink 200µA can pull this point to ground and shut off
both output drivers.
TA = +25oC
V+ = 8V - 40V
105
CT = 0.001µF
CT = 0.002µF
CT = 0.005µF
104
CT = 0.02µF
CT = 0.05µF
While feedback is normally applied around the entire regulator, the error amplifier can be used with conventional
operational amplifier feedback and will be stable in either the
inverting or non-inverting mode. Input common-mode limits
must be observed; if not, output signal inversion may result.
The internal 5V reference can be used for conventional regulator applications if divided as shown in Figure 8. If the error
amplifier is connected as a unity gain amplifier, a fixed duty
cycle application results.
CT = 0.1µF
CT = 0.01µF
103
1
102
10
104
103
OSCILLATOR PERIOD, t (µs)
FIGURE 5. TYPICAL OSCILLATOR PERIOD AS A FUNCTION
OF RT AND CT
Error AmplIfIer Section
The error amplifier consists of a differential pair (Q56,Q57)
with an active load (Q61 and Q62) forming a differential
transconductance amplifier. Since Q61 is driven by a
constant current source, Q62, the output impedance ROUT,
terminal 9, is very high (≅ 5MΩ).
OUTPUT DUTY CYCLE (%)
TA = +25oC
V+ = 20V
The gain is:
AV = gmR = 8 lC R/2KT = 104,
ROUT RL
where R =
ROUT +
RL
, RL = ∞, AV ∝ 104
24
CT =1000pF
RT = 5k
fOSC = 20kHz
16
8
0
0.4 0.8 1.2 1.6
2
2.4 2.8 3.2 3.6
4
COMPARATOR VOLTAGE (V)
FIGURE 7. TYPICAL DUTY CYCLE AS A FUNCTION OF
COMPARATOR VOLTAGE (AT TERMINAL 9).
RL = 1MΩ
50
RL = 300kΩ
PHASE ANGLE (DEGREES)
60
OUTPUT SATURATION VOLTAGE (V)
OPEN LOOP GAIN
RL = 3MΩ
VOLTAGE GAIN (dB)
32
RL = ∞
70
40
0o
CT = 2700pF
RT = 6.19k
fOSC = 60kHz
40
0
Since ROUT is extremely high, the gain can be easily
reduced from a nominal 104 (80dB) by the addition of an
external shunt resistor from terminal 9 to ground as shown in
Figure 6.
80
48
RL =100kΩ
90o
OPEN LOOP PHASE
50
10
102
103
104
1.1
1.0
0.9
0.8
0.7
-75 -50 -25
105
0
25
50
75 100 125 150 175
AMBIENT TEMPERATURE (oC)
FREQUENCY (Hz)
FIGURE 8. TYPICAL OUTPUT SATURATION VOLTAGE AS A
FUNCTION OF AMBIENT TEMPERATURE.
FIGURE 6. OPEN-LOOP ERROR AMPLIFIER RESPONSE
CHARACTERISTICS.
8
CA1524, CA2524, CA3524
Output Section
The internal 5V reference can be used for conventional regulator applications if divided as shown in Figure 11. If the error
amplifier is connected as a unity gain amplifier, a fixed duty
cycle application results.
The CA1524 series outputs are two identical n-p-n
transistors with both collectors and emitters uncommitted.
Each output transistor has antisaturation circuitry that
enables a fast transient response for the wide range of
oscillator frequencies. Current limiting of the output section
is set at 100mA for each output and 100mA total if both
outputs are paralleled. Having both emitters and collectors
available provides the versatility to drive either n-p-n or p-n-p
external transistors. Curves of the output saturation voltage
as a function of temperature and output current are shown in
Figures 8 and 9, respectively. There are a number of output
configurations possible in the application of the CA1524 to
voltage regulator circuits which fall into three basic
classifications:
VREF
R2
POSITIVE
OUTPUT
VOLTAGES
5K
2
+
-
1
5K
R1
VO
GND
VREF
1. Capacitor-diode coupled voltage multipliers
2. Inductor-capacitor single-ended circuits
3. Transformer-coupled circuits
2.5V (R1 + R2)
R1
R1R2
= 2.5KW
R1 + R2
R1
5K
2
+
-
OUTPUT SATURATION VOLTAGE (V)
1
2.0
TA = +25oC
V+ = 8V to 40V
5K
GND
1.5
NEGATIVE
OUTPUT
VOLTAGES
R2
FIGURE 11. ERROR AMPLIFIER BIASING CIRCUITS
1.0
0.5
16
0
0
20
40
60
80
VT
100
15
OUTPUT CURRENT, IL (mA)
FIGURE 9. TYPICAL OUTPUT SATURATION VOLTAGE AS A
FUNCTION OF OUTPUT CURRENT
VREF
CA1524
REFERENCE
SECTION
8
V+ CANNOT
EXCEED 6V
Device Application Suggestions
For higher currents, the circuit of Figure 10 may be used with
an external p-n-p transistor and bias resistor. The internal
regulator may be bypassed for operation from a fixed 5V
supply by connecting both terminals 15 and 16 to the input
voltage, which must not exceed 6V.
NOTE: V+ Should Be in the 5V Range
And Must Not Exceed 6V
FIGURE 12. CIRCUIT TO ALLOW EXTERNAL BYPASS OF THE
REFERENCE REGULATION
To provide an expansion of the dead time without loading the
oscillator, the circuit of Figure 13 may be used.
Q1
100Ω
V+
15
CA1524
REFERENCE
SECTION
IL TO IA
DEPENDING
ON CHOICE
FOR Q1
16
16
VREF
5KΩ
9
+
10µF
8
8
GND
FIGURE 13. CIRCUIT FOR EXPANSION OF DEAD TIME, WITHOUT USING A CAPACITOR ON PIN 3 OR WHEN A
LOW VALUE OSCILLATOR CAPACITOR IS USED
FIGURE 10. CIRCUIT FOR EXPANDING THE REFERENCE
CURRENT CAPABILITY
9
CA1524, CA2524, CA3524
TABLE 1. INPUT vs. OUTPUT VOLTAGE, AND FEEDBACK
RESISTOR VALUES FOR IL = 40mA (FOR CAPACITOR-DIODE OUTPUT CIRCUIT IN FIGURE 18)
VO = 5V
SA//SB
R1
(
IMAX = I
RS
R2
RS
5
SENSE
+
4
ISC =
VO (V)
)
VOR2
VTH +
R1 + R2
VTH
6
8
-2.5
10
9
-3
11
10
-4
13
11
-5
15
12
-6
17
13
-7
19
14
-8
21
15
VTH = 200mV
FIGURE 14. FOLDBACK CURRENT-LIMITING CIRCUIT USED
TO REDUCE POWER DISSIPATION UNDER
SHORTED OUTPUT CONDITIONS
D1
V+
+VO
SA
SB
V+ > VO
D1
+VO
V+
SA
SB
V+ < VO
D1
V+
V+ (Min.) (V)
-0.5
WHERE
RS
R2 (KΩ)
-9
23
16
-10
25
17
-11
27
18
-12
29
19
-13
31
20
-14
33
21
-15
35
22
-16
37
23
-17
39
24
-18
41
25
-19
43
26
-20
45
27
-VO
V+
SA
SB
| V+ | > | VO |
VO
SA-B
NOTE: Diode D1 Is Necessary To Prevent Reverse
Emitter-Base Breakdown of Transistor Switch SA.
FLYBACK
FIGURE 15. CAPACITOR-DIODE COUPLED VOLTAGE
MULTIPLIER OUTPUT STAGES
SA
VO
V+
SA/SB
V+
SB
+VO
PUSH-PULL
V+ > VO
SA
CAN BE SA OR
SA CAN DRIVEQ1
Q1
SB
CAN BE SB OR
SB CAN DRIVEQ2
Q2
+
VO
V+
+VO
V+
SA/SB
V+ < VO
V+
SA/SB
V+
+
-
-VO
VO
| V+ | < | VO |
FULL BRIDGE
FIGURE 16. SINGLE-ENDED INDUCTOR CIRCUITS WHERE THE
TWO OUTPUTS OF THE 1524 ARE CONNECTED IN
PARALLEL
FIGURE 17. TRANSFORMER-COUPLED OUTPUTS
10
CA1524, CA2524, CA3524
Applications (Note 1)
Single-Ended Switching Regulator
The CA1524 in the circuit of Figure 19 has both output
stages connected in parallel to produce an effective 0% 90% duty cycle. Transistor Q1 is pulsed on and off by these
output stages. Regulation is achieved from the feedback
provided by R1 and R2 to the error amplifier which adjusts
the on-time of the output transistors according to the load
current being drawn. Various output voltages can be
obtained by adjusting R1 and R2. The use of an output
inductor requires an R-C phase compensation network to
stabilize the system. Current limiting is set at 1.9 amperes by
the sense resistor R3.
A capacitor-diode output filter is used in Figure 19 to convert
+15VDC to -5VDC at output currents up to 50mA. Since the
output transistors have built-in current limiting, no additional
current limiting is needed. Table 1 gives the required
minimum input voltage and feedback resistor values, R2, for
an output voltage.
Capacitor-Diode Output Circuit
A capacitor-diode output filter is used in Figure18 to convert
+15VDC to -5VDC at output currents up to 50mA. Since the
output transistors have built-in current limiting, no additional
current limiting is needed. Table 1 gives the required
minimum input voltage and feedback resistor values, R2, for
an output voltage range of -0.5V to -20V with an output
current of 40mA.
NOTE:
1. For additional information on the application of this device and a
further explanation of the circuits below, see Intersil Application
Note AN6915 “Application of the CA1524 series PWM lC”.
V+
+15V
R2
15KΩ
61
5KΩ
1
12
1
21
R1
5KΩ
16
1
11
1
IN4001
5KΩ
0.1µF
2KΩ
0.01µF
CA3524
61
14
1
71
41
31
15
10
1
9
1
18
20µF
IN4001
-5V
20mA
13
1
IN4001
50µF
R1 = 5KΩ
0.01µF
R2 =
R1 ( | VO | + 2.5)
(VREF - 2.5)
FIGURE 18. CAPACITOR-DIODE OUTPUT CIRCUIT
V+
+5V IA
+28V
5KΩ
0.1µF
0.9mH
R1
5KΩ
R2
5KΩ
5KΩ
15
1
1
12
1
21
11
1
Q1
500µF
2KΩ
16
1
3KΩ
0.02µF
2N6388
CA3524
13
1
61
14
1
71
41
31
15
10
1
9
1
RURD410
0.001µF
18
50KΩ
0.1Ω
V-
FIGURE 19. SINGLE-ENDED LC SWITCHING REGULATOR CIRCUIT
11
CA1524, CA2524, CA3524
Flyback Converter
Low-Frequency Pulse Generator
Figure 20 shows a flyback converter circuit for generating a
dual 15V output at 20mA from a 5V regulated line.
Reference voltage is provided by the input and the internal
reference generator is unused. Current limiting in this circuit
is accomplished by sensing current in the primary line and
resetting the soft-start circuit.
Figure 22 shows the CA1524 being used as a low-frequency
pulse generator. Since all components (error amplifier,
oscillator, oscillator reference regulator, output transistor
drivers) are on the lC, a regulated 5-V (or 2.5-V) pulse of 0%
- 45% (or 0% - 90%) on time is possible over a frequency
range of 150 to 500Hz. Switch S1 is used to go from a 5-V
output pulse (S1 closed) to a 2.5-V output pulse (S1 open)
with a duty cycle range of 0% to 45%. The output frequency
will be roughly half of the oscillator frequency when the
output transistors are not connected in parallel (75Hz to
250Hz, respectively). Switch S2 will allow both output stages
to be paralleled for an effective duty cycle of 0%-90% with
the output frequency range from 150 to 500Hz. The
frequency is adjusted by R1; R2 controls duty cycle.
Push-Pull Converter
The output stages of the CA1524 provide the drive for
transistors Q1 and Q2 in the push-pull application of Figure
21. Since the internal flip-flop divides the oscillator frequency
by two, the oscillator must be set at twice the output
frequency. Current limiting for this circuit is done in the
primary of transformer T1 so that the pulse width will be
reduced if transformer saturation should occur.
V+
RURD620
+15V
+5V
+
100µF
25K
Ω
15
1
5K
Ω
300Ω
200Ω
1MΩ
50T
50µF
20T
1
12
1
21
11
1
50T
0.1µF
5KΩ
50µF
5KΩ
16
1
2KΩ
CA3524
61
14
1
71
41
0.02µF
-15V
13
1
31
15
10
1
9
1
RURD620
2N6290
CORE: FEROX CUBE
2213P - A250 - 387
OR EQUIVALENT
620Ω
IN914
510Ω
+
18
0.001µF
4.7µF
2N2102
1Ω
FIGURE 20. FLYBACK CONVERTER CIRCUIT
V+
+28V
15
1
5K
Ω
5KΩ
5KΩ
0.1µF
5KΩ
1KΩ
1W
1
12
1
21
11
1
16
1
13
1
61
14
1
71
41
31
15
2KΩ
1KΩ
1W
RURD620 1mH
2N6292
20T
1KΩ
1KΩ
20T
5T
5T
0.01µF
2N6292
10
1
9
1
0.001µF
18
RURD620
+
0.1µF
100µF
20KΩ
FIGURE 21. PUSH-PULL TRANSFORMER-COUPLED CONVERTER
12
+
1500µF
5V
5A
CA1524, CA2524, CA3524
+5
VREFERENCE
DUTY CYCLE
ADJUSTMENT
R2
10K
2
15
3
14
4
13
CA3524
5
12
6
11
R1
50K
7
10
0.1µF
8
9
V+
1.1K
1/ S2
2
TO PIN 12 TO PIN 13
OUTPUT 1 OUTPUT 2
16
1
2K
FREQUENCY
ADJUSTMENT
1.1K
TO PIN 9
2K
= 9V
OUTPUT 1A
1/
1.5K
2S1
1/
2S2
OUTPUT 2A
1/
1.5K
2S1
20K
TO PIN 1
SILVER
MICA
SWITCH
OUTPUT
PULSES
DUTY
CYCLE
S1
0V - 5V
0% - 45%
S2
-
0% - 90%
FIGURE 22. LOW-FREQUENCY PULSE GENERATOR
The Variable Switcher
varied, the feedback voltage will track that level and cause
the output voltage to change according to the change in
reference voltage.
The circuit diagram of the CA1524, used as a variable output
voltage power supply is shown in Figure 23. By connecting
the two output transistors in parallel, the duty cycle is
doubled, i.e., 0% - 90%. As the reference voltage level is
D1
D3
36
AC
IN
D2
VDC
2N6385
(PNP DARLINGTON)
Q1
D4
L1
20mH
R2
1.5
10W
R1
1K
1W
5100µF
100V
7V - 30V
0A - 3A
0.01µF
D1-D4 - A15A
C5
25µF
D5
RURD410
C3
10000µF
100V
C4
0.1µF
VOUT
NON-POLAR
L2
50mH
RETURN
BIFILAR
WINDING
C6
25µF
NON-POLAR
C7
0.1µF
R3
10K
R4
5K
16
15
14
13
12
11
10
9
R10
16K
CA1524
R6
2K
1
2
3
4
5
6
7
8
R7
10K
R9
15K
1%
R5
2K
R8
2K
VOLTAGE
CONTROL
C8
0.1µF
C9
3300
pF
1%
C11
0.01µF
C10
1100pF
SILVER
MICA
fOSC = 20KHz
FIGURE 23. THE CA1524 USED AS A 0-5A, 7-30 V LABORATORY SUPPLY
13
CA1524, CA2524, CA3524
Digital Readout Scale
The CA1524 can be used as the driving source for an
electronic scale application. The circuit shown in Figures 24
and 25 uses half (Q2) of the CA1524 output in a low-voltage
switching regulator (2.2V) application to drive the LED’s
displaying the weight. The remaining output stage (Q1) is
used as a driver for the sampling plates PL1 and PL2. Since
the CA1524 contains a 5V internal regulator and a wide
operating range of 8V to 40V, a single 9V battery can power
the total system. The two plates, PL1 and PL2, are driven
with opposite phase signals (frequency held constant but
duty cycle may change) from the pulse-width modulator lC
(CA1524). The sensor, S, is located between the two plates.
Plates PL1, S and PL2 form an effective capacitance bridgetype divider network. As plate S is moved according to the
object’s weight, a change in capacitance is noted between
PL1, S and PL2. This change is reflected as a voltage to the
ac amplifier (CA3160). At the null position the signals from
PL1 and PL2 as detected by S are equal in amplitude, but
opposite in phase. As S is driven by the scale mechanism
down toward PL2, the signal at S becomes greater. The
CA3160 ac amplifier provides a buffer for the small signal
change noted at S. The output of the CA3160 is converted to
a dc voltage by a peak-to-peak detector. A peak-to-peak
detector is needed, since the duty cycle of the sampled
waveform is subject to change. The detector output is filtered
further and displayed via the CA3161E and CA3162E digital
readout system, indicating the weight on the scale.
PL1
OSCILLATOR ≈ 20KHz
(PART OF CA1524)
PEAK TO PEAK
DETECTOR
AC
AMP
S
PL2
LOW PASS
FILTER
DC
VOLTAGE
CA3130
COUPLED TO
MECHANICAL
SCALE MECHANISM
DISPLAY DRIVE
(PART OF CA1524)
FULL SCALE
NO WEIGHT
DIGITAL METER
AND DISPLAY
FIGURE 24. BASIC DIGITAL READOUT SCALE
2.5V
+5V
ZERO
ADJUSTMENT
0.27
µF
50K
8
0.1
µF
9 12 14
POWER 2N2907
OR EQUIVALENT
16
MSD
NSD
LSD
A
B
C
COMMONANODE LED
DISPLAYS
(NOTE 1)
5
3
4
13
CA3162E
11
HIGH
INPUTS:
LOW
10
13
GAIN
ADJUSTMENT
7
CA3161E
12
DIGIT
DRIVERS
11
16
6
10
15
2
9
1
1
15
2
7
14
BCD
OUTPUTS
8
3
NOTE:
1. FAIRCHILD FND507 OR EQUIVALENT
10KΩ
FIGURE 25. SCHEMATIC DIAGRAM OF DIGITAL READOUT SCALE (CONT’D)
14
CA1524, CA2524, CA3524
9V
10K
200pF
100µF
PL1
TO SCALE
MECHANISM
1
9V
8
3
S
100
MΩ
PL2
39K
22MΩ
2
7
+
CA3160
-
68K
4
430K
22MΩ
30K
0.1µF
910K
910K
6
6.2K
0.47
µF
2µF
2µF
10K 10µF
300K
2N4037
9V
2.5V
125µH
A
B
C
470µF
200Ω
4.7K
5V
16 15 14 13 12 11 10 9
CA1524
4.7K
1
2
3
4.7K
4.7K
4
5
6
7
0.01µF
8
24K
6.2K
4700pF
FIGURE 26. SCHEMATIC DIAGRAM OF DIGITAL READOUT SCALE
DIMENSIONS AND PAD LAYOUT FOR CA3524RH CHIP
NOTE: Dimensions in parentheses are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations
are in mils (10-3 inch). The layout represents a chip when it is part of
the wafer. When the wafer is cut into chips, the cleavage angles are
57o instead of 90o with respect to the face of the chip. Therefore, the
isolated chip is actually 7 mils (0.17mm) larger in both dimensions.
15
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice.
Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may
result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
File Number
16