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High Speed MOSFET Circuits Using Advanced Lithography D. L. Critchlow IBM Introduction During the last decade we have seen a dramatic increase in the complexity of silicon integrated circuit chips, particularly in memory. The n-channel FET technology is dominant in main memory and in lower performance logic and arrays (i.e., read-only memory and buffers) because of its higher circuit density and simpler processing, whereas bipolar transistor technology dominates for high-performance logic and arrays. As applications develop for microprocessors and minicomputers there is an increasing demand for logic, array, and memory technologies in the cost/ performance range of 5 to 25 nanosecond delay/ logical decision and 100 to 200 nanosecond memory system access time but at costs approaching that achieved by current FET technology. These needs have led to a renewed interest in bipolar LSI, particularly in merged transistor logic (MTL) or integrated injection logic (12L), and in higher speed FET technologies. Potential advances with conventional FET structures evolve from advances in lithography-e.g., electron beam exposure of patterns directly on the wafer, which allow further miniaturization. The,purpose of the paper is to quantify the advantages of FET circuits of smaller dimensions, February 1976 to survey the trends in lithography, and to describe some experimental results. As illustrated in Figure 1, the advances in memory density have been dramatic. Over two orders of magnitude reduction in normalized memory cell area were achieved at the conceptual stage due to device and circuit innovation in a seven year period from 1963 to 1970. (Large scale production followed about 5 to 7 years later.) This plot is normalized to the area per cell of a hypothetical array of metal lines (e.g., x-direction) crossing an array of diffusions (e.g., y-direction) with a cbntact hole between each intersection of the two arrays. The plot shows that we are within a factor of five or so of this "ultimate" normalized density of this hypothetical array and hence can expect only small improvements in the future due to memory, cell innovation. During the time period shown, only modest reductions in line widths were achieved. Rather, effort went into learning how to reduce photolithographic defect levels to allow large levels of integration to be achieved. During the last few years we have seen line widths decrease gradually from the 5 to 10 pm range to 3 to 5 pm. However, optical resolution limits make further advances more and more difficult. Hence the interest in alternate exposure techniques such as electron beam and x-ray to achieve even higher packing density. 31 i Bipolar * MOSFET t 100 Multiemmitter 0L * 0 a 0 0) 6 Device l0[ N N Slope of-l/2 per year N 4 Device . \ N I Device 3Device N I Device N (Improved Sense) IN INI Metal-Diffusion Crossing (Contact Hole) 63 64 65 N. N CCD 66 67 68 69 Year of "Product Conception" 70 - 71 72 Figure 1. Memory cell improvements due to device and circuit innovation over last decade plotted for fixed litho graphic layout rules SCALE: L, W, tox, Na, VD & VG BY k THEN: DELAY ak POWER/CIRCUIT a, k2 AREA/CIRCUIT ak2 POWER/UNITAREA = CONSTANT Figure 2. Scaling of FET devices and interconnections to obtain improved delay power and density Scaling of FET's If all dimensions of the devices (Figure 2) and interconnections are multiplied by a scaling factor k (less than unity), the circuit density obviously increases as 1/k2. In addition, miniaturization can also improve circuit speed and reduce power dissipation.' The approach is to scale all horizontal and vertical dimensions and the operating voltages by the factor k. (If one reduces dimensions without reducing voltages, the field strength in the structure will increase, raising problems with device reliability. Also, velocity saturation effects limit the device transconductance and hence the gain in speed.) In order to scale depletion layer widths, the doping level of the substrate is increased by 1/k. 32 The transconductance (Gm) of expressed as follows: Gm where = VG-VT an FET can be -effx W DSLx IDS = drain to source current VG = gate voltage VT = threshold voltage VDS = drain to source voltage COMPUTER W/L = width to length ratio of device 1eff = large signal mobility of device e = effective dielectric constant of gate insulator tox = gate insulator thickness 4 -E tox iooo A L w a5 I = wz H z 0 Hence Gm remains constant as the design is scaled. The total node capacitance (C) driven by the circuit scales directly with k since all dimensions including dielectric thickness are made smaller. The delay (Td) of the circuit can be approximated as DRAIN VOLTAGE [V] t *200A Td = C/Gm a k, hence the circuit becomes faster. The circuit power is: P = VX IaV2X Gmak2; therefore, the power reduces dramatically. Note that since the area per circuit is also decreasing as k2, the power per unit area remains the same and the cooling requirement has not changed. The power-delay product (P X Td), a useful measure of circuit quality, scales as k3, which is indeed a dramatic improvement. Lithography improvements from the present day 5 ,um to 1 ,m in the future should therefore result in circuits which are 25 times more dense, 5 times faster, and dissipate 1/25 as much power with a power delay improvement of 125. Note that a key reason for the dramatic improvement in the power-delay product due to scaling is the lowering of the operating voltages. In the case of bipolar transistors the operating voltages tend to be low already. Therefore, bipolars may not gain as much by using smaller dimensions unless lower voltage circuit/device techniques (e.g., MTL/I2L) are used as well. Experinental results of scaling (from Ref. 1) are given in Figure 3. The experimental grounded source characteristics (Figure 3A) demonstrate that the scaling works quite well at large currents. However, as shown in Figure 3B the subthreshold current of the device does not scale, resulting in a "softer turnon." Figure 3C shows the threshold voltage as a function of source-drain spacing for each device design. Note that the onset of the "short channel effect" (due to the merging of the depletion layer around the drain with that around the source) has scaled down because of the higher substrate doping level, the shallower junction, and the lower operating voltages; hence it is not a limitation. Scaling down does result in some problems: 1) The thinner dielectric-e.g., 200 A-is more difficult to manufacture and may suffer reliability problems.* 2) As mentioned above, the subthreshold region of z w L' =WUI1 z 4 cc A. Grounded source characteristic 3.5 3.0 2.5 Vads 2.0 [PA] 1/2 1.5 1.0 0.5 1.2 1.6 2.0 GATE VOLTAGE [V] 4 2.8 2.4 B. Subthreshold characteristic > 2.5 Li CONVENTIONAL FET DEVICE tox = 1000I VDD = 12 VOLTS XXj =2.5MICRONS 5 2.0 F_ A- 0 -o 1.5 I I.CIF tox =200 VDD=2.5VOLTS, Xj =0.5 MICRONS LI 0 5 0O ..~0-0 - 1 -0 0- 6 7 4 5 3 2 SOURCE DRAIN SPACING (MICRONS) 8 C. Effect of source-drain spacing on device threshold *This problem can be relieved by the use of ion implantation to make improved device designs with thicker gate oxides, e.g. 350 R rather than 200 A, Ref. 1. Feburary 1976 Figure 3. Experimental results comparing 5 gm device and scaled 1 gm device 33 Table 1. Alternative Lithographic Techniques TECHNIQUE ADVANTAGES PRESENT LIMITATIONS PRESENT CAPABILITY Contact Printing Conventional simplicity, throughput flexible mask resolution, throughput defects, resolution, wear, flatness registration, mask stabilitv Near-Contact Printing ultraviolet X-ray Optical Projection full wafer step & repeat Reflective Optics full wafer Electron Beam raster scan (spot) vector scan (spot) projection 4-8 pm for LSI manufacture non-contact, throughput resolution, flatness resolution, non-contact suitable resist, exposure <1 um over 1 cm x cm as time, alignment, thermal lab experiment stability non-contact, throughput standing waves in resist, magnification, depth of focus, thermal stability non-contact, resolution/ .standing waves, throughput, depth of focus field-size tradeoff 3-5 m over 6 cm diameter as lab tool and early manufacturing 1 to 2 pm over 5mm x 5mm as lab tool & limited manufacturing non-contact, through-put resolution, flatness, thermal stability 2to4pm over7.5cm throughput, cost resolution, depth of focus, low hysteresis & eddy currents, flexibility throughput, hysteresis hi.gher throughput & eddy currents, cost 1 Am lines over 2mm x 2mm field as lab throughput, resolution the device transfer characteristic does not scale, resulting in a "softer" turn-on characteristic for the smaller structures. This impacts circuit performance and appears to limit practical designs to about 1 pm minimum dimensions at room temperature.** 3) The current density in the power supply lines increases by 1/k, possibly impacting reliability due to aluminum migration. 4) The resistive voltage drops in power lines become more significant by 1/k when compared to the power supply voltage. 5) The RC time constants of the signal lines on the chip remain constant while the circuit speeds are increasing. The latter two problems become especially severe when **Operation at lower temperatures can sharpen the turn-on, allowing circuit design with submicron devices.2 34 4-8 mm for LSI manufacture <1 ,um as lab experiment mask problem, cost diameter, early manufacturing usage experiment 1 gm lines over 2mm x 2mm field as lab experi- ment 1 pm lines over 5 mm field in limited lab experiments diffused and polysilicon lines are used for signal and power distribution. This points to the desirability for a two-level metal interconnection technology for very small dimensions. Lithography Trends Integration levels on semiconductor chips have to a very large degree been paced by the lithographic capabilities, particularly in defect levels, resolution, and field size. Consequently many alternative tech- niques have been explored (see Table 1). Contact printing is the mainstay of the industry due to its inherent simplicities in process and tooling and high throughput. Contact printing has potential for submicron dimensions, but problems of defects, damage COMPUTER during use, and dimensional problems due to mask and wafer flatness and thermal considerations have limited its use for LSI to dimensions of 4 to 8 plm. In addition, standing wave patterns in the resist, reflections, and the complex topology of a partially completed wafer add to the problems. Flexible masks,3 which follow the contour of the wafer, overcome some of the flatness/resolution problems but tend to aggravate the dimensional tolerance problems. Nearcontact (or proximity) printing which alleviates the damage problem during exposure at some sacrifice in resolution due to diffraction effects4 also has broad usage. A relatively new but promising approach is to uAse near-contact printing with soft x-ray sources (10 A wavelengths) to essentially remove the diffraction limitation.5 Submicron -dimensions have been demonstrated. Key problem areas at present are the fabrication of masks with sufficient contrast/resolution, alignment techniques, exposure time, and finding the correct resist. Dimensional matching between mask and wafer will be a critical factor in achieving the ultimate resolution while meeting registration requirements. Thermal expansion and changes in wafer dimension during processing are key questions. Optical projection, where optics (in the range of lx to lox reduction) are placed between the mask and the wafer, has the advantages of non-contact printing and the direct use of the optics to expose the wafer without introducing intermediate masking steps and their attendant problems of increased defects, loss of resolution, and increased distortion. Full wafer systems (6 cm diameter) are limited to 3 to 5 pum minimum lines, while with a step-and-repeat system, 1 or 2 pm resolution on a 5mm X 5mm field may be possible. The penalty for this increased resolution is a more complicated step-and-repeat mechanism with a reduced throughput rate and possible alignment errors. Magnification and depth of focus are critical factors in both systems. A severe problem results from the use of monochromatic light: complex standing wave patterns in the photoresist, which are a function of film thicknesses and affect both exposure levels (and hence line widths)6 and the ability to see alignment marks. Another projection approach is the reflective optics system,7 which uses two concentric spherical reflecting surfaces (rather than lenses) to focus a narrow illuminated zone or slit across the mask onto the wafer. By moving the wafer and mask laterally in unison, one may scan the slit across the field to expose the whole wafer. The system uses polychromatic light, which helps alleviate the problems due to standing waves mentioned above. The system is reported to have resolution capabilities of 2 pm over 7.5 cm diameter wafers.7 All of these projection systems have several factors in common: they are limited by fundamental relations between depth of focus and resolution, and they have similar requirements on illumination control and positional and geometrical tolerances which can only be understood after considerable engineering and experience. Electron beam exposure offers higher resolution and large depth of focus. In a scanned single spot February 1976 system an electron beam is deflected over the field under computer control. This allows a high degree of flexibility including the potential of modifying the positions of patterns exposed to match those previously written on the silicon wafer. A raster scan single spot system' minimizes hysteresis and eddy current effects since each scan has the same history, whereas a vector (or point to point) system8 scans only the geometries being exposed and has a higher speed potential. As with optical projection there is a relationship between field size and resolution which for a high quality single spot system results in a field about 2000 times the minimum geometry being exposed. (This assumes 4 or 5 spot diameters per minimum line width exposed to achieve good line edge and corner resolution.) A key concern is throughput since the system is serial. Broers and Dennard9 calculate that such systems would require 35 to 120 minutes to expose a 6-cm diameter wafer with 1 Am lines with about 400 individual 2mm X 2mm fields. This may be satisfactory for small volume production where flexibility and resolution are paramount. However, for large volume production, such as memory, projection electron beam systems in which a mask is imaged onto the wafer through an electron lens system are much more interesting. Field sizes 10,000 times the minimum line width may be possible, and exposure timnes can be very short (<1 second) since a large area is being exposed at once. In this case Broers and Dennard estimate a potential exposure time of 70 seconds per wafer (including table stepping and registration time) using 5mm X 5mm fields. A key remaining problem in projection systems is the fabrication of a stable accurate mask which is transparent to electrons. One possible solution is to use a photocathode in place of the mask. 10 Experimental High Density Memory Chip Figures 4A and B show an experimental, fullydecoded 8192-bit memory chip1' that was made using electron beam exposure with line widths in the order of 1.5 pum. The one-device memory cell is used. The FET's are n-channel silicon gate with a gate oxide of 350 A, an ion-implanted channel region for threshold tailoring, and ion-implanted arsenic source and drain regions. Boron ions are implanted in the isolation region surrounding the storage nodes and active devices to control leakage. The poly-methyl methacrylate resist was exposed using a vector-scan system under computer control. Aluminum liftoff and plasma etching techniques were used to improve the resolution of the line delineation pr'ocesses. Electrical testing of the chips demonstrated access times in the order of 90 ns; this corresponds well with the projected speed. No attempt was made to determine chip yield. These results indicate that considerable progress has been made in lithography in terms of demonstration that resolution and alignment capability needed for these small dimensions can indeed be achieved. 35 Figure 4. Experimental n-channel silicon gate 8K-bit memory chip fabricated using electron beam system and 1.5£ m lines A. Full chip B. Detail of structure 36 COMPUTER Conclusions Miniaturization of FET's holds promise of improvement by perhaps a factor of 5 in speed and dramatic power reductions over present products in the industry. Depending upon design tradeoffs and the sophistication of the technologies used, this could result in average logic circuit delays (including fanout and interconnection capacitance) in the range of 5 to 25 nanoseconds. Coupled with the very higher packing densities and the inherent simplicity of the FET, this may lead to significant changes in how one builds computers in the cost/performance region. The complexities of the advanced lithography tools and the processes are great. This, in conjunction with a number of choices of lithographic tools and device technologies, indicates that the move to smaller dimensions will probably occur over a 8. "Instrumentation for Electron Beam Lithography," T. H. P. Chang, IEEE Transactions or Magnetics, September 1974. 9. "Impact of Electron Beam Technology on Silicon Device Fabrication," A. N. Broers and R. H. Dennard, Semiconductor Silicon 1973, H. R. Huff and R. R. Burgess, Eds., The Electrochemical Society Pubs., 1973, pp. 830-841. 10. "Computer Controlled Electron-Beam Projection Mask Aligner," W. R. Livesay, Solid State Technology, July 1974, pp. 21-26. "Fabrication of a Miniature 8K-bit Memory Chip Using Electron Beam Exposure," H. N. Yu et al, J. Vac. Sci. Technology, Vol. 12, No. 6, November/December, 1975. 11. Dale L. Critchlow is Heights, New York. Currently he is manager of the Solid State Engineering Department which, as one of its missions, exploring the practical lim.its of the FET BSEE logic and memory. He received hisand the is from The concepts and data given here are the result of the work of many people over several years. In particular, the author wishes to acknowledge the contribution of R. H. Dennard, H. N. Yu, A. Broers, and people in their respective groups. research staff member in Yorktown number of years. Acknowledgements a in the T. J. Watson Research Center of IBM Grove City College in 1953 MS and PhD degrees in electrical engineering from Carnegie Institute of Technology in 1954 and 1956, respectively. After serving as assistant professor at CIT for two years, he joined IBM Research in 1958. During the 1960's he worked on the n-channel MOSFET logic and memory circuits currently used in IBM products. Dr. Critchlow is a member of the IEEE and Sigma Xi. EDP References 1. "Design of Ion-Implanted MOSFETs with Very Small Physical Dimensions," R. H. Dennard, F. H. Gaensslen, H. N. Yu, V. L. Rideout, E. Bassous, and A. LeBlanc, IEEE J. Solid State Circuits, October 1974. 2. "Design and Characterization of Very Small MOSFETs for Low Temperature Operation," F. A. Gaensslen, et al, International Electron Devices Meeting, Washington, D.C. December 3-5,1975. 3. 4. "A High-Yield Photolithographic Technique for Surface Wave Devices," H. I. Smith, F. J. Bachner, and N. Efremow, Electrochemical Soc. 118,821 (1971). "Computer Simulation Study of Images in Contact and Near-Contact Printing," B. J. Lin, Polymer Engineering and Science, July 1974, Vol. 14, No.7, pp.498-508. PERFORMANCE REVIEW The How-to Monthly on Computer Performance Improvement * * * * Tutorial Reports User Experiences Products & Services Current Literature Conferences, 5. "X-Ray Lithography: A Complementary Technique to Electron Beam Lithography," H. I. Smith, D. L. Spears, and S. E. Bernacki, J. Vac. Sci. Technology, Vol. 10, No. 6, November/December 1973, pp 913-917. * 6. "Special Issue on Pattern Generation and Microlithography," L. K. Anderson, Ed., IEEE Transactions on Electron Devices, July 1975, Vol. ED-22, No. 7. sample issue and index. 7. "All-Reflective 1:1 Projection Printing System," Peter Moller, Proceedings of Regional Technical Conference, Mid-Hudson Section, Society of Plastics Engineers, Inc., October 24-26,1973, pp. 56-62. February 1976 EUPPRFOEWA"EEW ftr i2 o Seminars Subscription: $48.00/year. Write now for I___AG______ a free W" nce tO10 - .=._ O t"0es ==_ Applied Computer Research P.O. Box 9280, Phoenix, AZ 85068 (602) 944-1589 Reader Service Number 223 37