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Target Tester: All GR228X testers except the GR2288 Generated by: xpse:PTS.r.320 [pse:Arena:sv386] Sat Feb 3 00:20:39 EDT 1996 Template Ver: 3.2.1 Generated on: Tue Jul 9 09:43:38 1996 Supply voltages should be wired to power buses in the fixture. NOTE GenRad software requires that all power nodes begin with VCC and all reference nodes begin with GND. For example: VCC5 would be +5V VCCN5_2 would be -5.2v; GND would be digital ground and be analog ground. ----------------------------------------------------------Target Testers with Alliance supplies require: PS(1) 5.00 Volts 2.00 Amps Target Testers with Non-Alliance supplies require: SVS(1) 5.00 Volts 2.00 Amps ----------------------------------------------------------Power Supply Wiring Information for PS(1) / SVS(1): 5.00 Volt Power Node=VCC 5.00 Volt Reference Node=GND Connect 03-A17 to 5.00 Volt Reference Bus (LO) Connect 03-A18 to 5.00 Volt Reference Bus (LO) Connect 03-A19 to 5.00 Volt Reference Bus (LO) Connect 03-A20 to 5.00 Volt Reference Bus (LO Sense) Connect 03-A21 to 5.00 Volt Power Bus (HI Sense) Connect 03-A22 to 5.00 Volt Power Bus (HI) Connect 03-A23 to 5.00 Volt Power Bus (HI) Connect 03-A24 to 5.00 Volt Power Bus (HI) *** SVS1 Programming Resistor Wiring: Connect 01-B32 to 01-B33 Connect 01-B28, 01-A28, 01-A29, 01-A30, and 01-A31 together Connect 19955 Ohm resistor between 01-B30 and 01-A30 Used to define variables, which customize the generated output files to specific target testers and power supply hardware configurations. To get detailed information on the power supply options variables, read the file pseopt.tpl in the GenRad templates directory or use on-line help for PSE. 1 /** Power Supply Programming Statements generated automatically by GenRad software on Mon Oct 21 15:39:25 1996. Executable: pse.exe:PTS..40 [pse:Arena:nt386] Fri Aug 23 22:33:55 1996 Template: 3.2.1 **/ /** Subroutines needed for Power Programming **/ DECLARE SYSTEM CNTRL_C(CSTRING CONTROL(8)); DECLARE DISCHARGE_POWER(); /* Power Discharge Subroutine */ DECLARE PWRUP(); /* Power-up Subroutine */ DECLARE PWRDN(); /* Power-down Subroutine */ /** LOAD Subroutine and LOAD Variables for Power Programming **/ DECLARE LOAD PROGRAM_INITIALIZATION(); /** Executed at RTS Init **/ DECLARE LOAD CSTRING GR_TARGET(8); /** Contains Target Tester **/ DECLARE LOAD POWER_TYPE; /** Alliance or Non-Alliance **/ /*** Global String variables for Power Programming ***/ DECLARE GLOBAL CSTRING CONTROL(8); /** For CNTRL_C Sys Sub **/ DECLARE GLOBAL CSTRING SUPPLY_SETTING(15); /** Voltage Setting **/ DECLARE GLOBAL CSTRING SUPPLY_NAME(15); /** Power Supply Name **/ 2 DECLARE GLOBAL CSTRING UUT_POWER_STATUS(3) = 'OFF'; /*** Declarations needed for BasicSCAN Diagnostics ***/ DECLARE BASSCAN_FAILBIT; /** BASICSCAN fail bit **/ DECLARE BASSCAN_FAILCNT; /** BASICSCAN fail count **/ DECLARE CSTRING PINNAME(5); /** Alpha-numeric pin name **/ /** Translates PINORDER number to Alphanumeric pin name **/ DECLARE SYSTEM GET_PINNAME(FLOAT PINORDER, CSTRING PINSTRING(5)); DECLARE BSTRING FAIL(1100); ENDDEC: ON ABORT CALL PWRDN(); /****************************************************/ /** Call UUT Power-Up Subroutine **/ /*********************************************************/ CALL PWRUP(); IF FAIL(6) THEN BRANCH DDONE; /* if power up fails skip digital tests */ /** Default ASSIGN LOGIC Statement - Modify as needed **/ ASSIGN LGC VCDH=3.5 VCDL=.2 VCST=1.5 VTT=1.5 VIHA=3.5 VILA=0.1 VOHA=2.4 VOLA=0.8 LVLA(1-3840); END_DIGINIT: DDONE: CALL PWRDN(); END; SUBROUTINE PROGRAM_INITIALIZATION(); /** This Load Subroutine is executed once during program initialization. It is used to determine and store system hardware configuration information in system variables that can then be accessed during UUT Power-up and Power-down sections... **/ /********************* NOTE*****************************/ /** The PROGRAM_INITIALIZATION(), PWRUP(), PWRDN(), and**/ /** DISCHARGE_POWER() Subroutines contain Test Language**/ /** Statements that will allow them to control both **/ /** Alliance and Non-Alliance GR228X power supplies. **/ /** The PROGRAM_INITIALIZATION() Subroutine determines **/ /** the target tester capabilities at Run-Time **/ /** initialization and executes the appropriate **/ /** Programming statements based on the target tester **/ /** configuration. **/ /*********************************************************/ /********************* WARNING!!*************************/ /** "Alliance" PS Power supplies on UNIX based testers **/ /** do not program negative. Negative voltages are **/ /** obtained by reversing the polarity of the leads in **/ /** the test fixture. The only exception to this is **/ 3 /** PS(13), which is wired in some 228X testers to **/ /** provide a negative voltage to match the -15V or 12V**/ /** FIXED Power Supply. Therefore, to obtain a positive**/ /** voltage on PS13, the polarity of the leads must be **/ /** reversed. **/ /********************** NOTE *****************************/ /** If you require negative supply voltages and the UUT **/ /** fixture is to be used on testers equipped with both **/ /** Alliance and Non-Alliance power supplies, then PVS **/ /** Supplies should be programmed to a positive voltage **/ /** and the HIGH side of the Supply should be wired to **/ /** the reference bus (usually GND) and the LOW side of **/ /** the supply should be wired to the negative supply **/ /** bus. This approach will allow the fixture to be **/ /** used with PS or PVS type supplies. **/ /** **/ /** Common PS / UPS fixture wiring is not possible when **/ /** supplying negative voltages. The wiring must be **/ /** swapped in the fixture when moving between testers **/ /** with different supplies! **/ /*********************************************************/ /************************NOTE****************************** This program uses the following 1 GenRad power supplies to power up the Unit-Under-Test: GR Supply Type: PS(1)/SVS1 UUT Power: 5.00 volts, 2.00 amps Power Nodes: VCC, GND Power Nails: 383, 249 ***********************************************************/ /** First, Declare local variables and System Subroutines **/ DECLARE SYSTEM SYSTYPE(CSTRING TEMP_STRG(8)); DECLARE SYSTEM CONFIG(CSTRING ARG1(8), ARG2, ARG3); /** Now, Make sure operator cannot ABORT this Subroutine **/ CALL CNTRL_C(CONTROL='OFF'); /* disable control C processing */ /** Get Target Tester Type **/ GET_TARGET_TYPE: CALL SYSTYPE(TEMP_STRG=GR_TARGET); WRITE ID=MESFILE'GenRad Target is %S%%NL%'GR_TARGET; /** Now find out if the tester has Alliance Supplies.**/ /** The variable POWER_TYPE will be set to 0 if the **/ /** target tester has Alliance Supplies, otherwise **/ /** it will be set to the ID of the PS Controller. **/ CALL CONFIG(ARG1='PSC', ARG2=1, ARG3=POWER_TYPE); /** If the target tester has Alliance supplies, then load Power Supply Sequence statements...**/ 4 IF POWER_TYPE = 0 THEN [ LOAD_PS_SEQUENCES: /** This section will "load" sequences into the ** Alliance Power Supply controller. Programming ** the Alliance Supplies using Sequences will ** produce the fastest UUT test throughput ** because the test programming statements are loaded ** into the Alliance controller only once, at Run-time ** initialization. ** The purpose of each sequence is: ** SET PS SEQUENCE = 1; Power up the UUT ** SET PS SEQUENCE = 2; Power down the UUT ** SET PS SEQUENCE = 3; Disconnect PS Relays **/ SEQUENCE1: /** Sequence #1 will TURN ON the power supplies. Supplies are turned on in the order they appear within the sequence. Remember, PS supplies cannot be programmed to negative voltages. Negative voltages are obtained by wiring the HIGH output to the negative supply bus and the LOW output to the reference bus. **/ SET PS START SEQUENCE = 1; SET PS(1) V=5 I=2.00 ; SET PS END SEQUENCE = 1; SEQUENCE2: /** Sequence #2 TURNS OFF the power supplies. Supplies are powered down in the opposite order in which they were powered up. **/ SET PS START SEQUENCE = 2; SET PS(1) V=0.0 I=2.00; SET PS END SEQUENCE = 2; SEQUENCE3: /** Sequence #3 DISCONNECTS the power supply relays. It must be preceded by a call to sequence 2 and a call to DISCHARGE_POWER to ensure that the power nodes are completely discharged prior to disconnecting the relays. **/ SET PS START SEQUENCE = 3; SET PS(1) DISCONNECT; SET PS END SEQUENCE = 3; ]; /* End of IF POWER_TYPE = 0 conditional */ /** Finished Initialization, enable control-C processing **/ CALL CNTRL_C(CONTROL='ON'); END SUBROUTINE PROGRAM_INITIALIZATION; SUBROUTINE PWRUP(); /** This Subroutine is called to Power-up the UUT **/ 5 DECLARE VVAL1; TEST_FOR_POWER: /* Do not execute this Subroutine if UUT is already powered up! */ IF UUT_POWER_STATUS = 'ON' THEN RETURN; PWRON: CALL CNTRL_C(CONTROL='OFF'); /* disable control C processing */ WRITE 'POWER UP FOR DIGITAL TESTING%NL%'; NOLOG; /* disable logging during power up */ SET PIO(0) HRLY(CLOSE 3); /* GROUND THE PCB */ CHECK_ID: /* Branch to Alliance or Non-Alliance power-up statements based on tester power configuration. */ IF POWER_TYPE > 0 THEN BRANCH NA_PWRUP; ELSE BRANCH A_PWRUP; NA_PWRUP: /* This section contains power up statements for testers with Non-Alliance power supplies. */ SVS_CONNECT_RELAY: /* CONNECT SVS TO UUT, Required on 2282 Only */ IF GR_TARGET = '2282' THEN SET PIO(0) HRLY(CLOSE 7); SVS1_ON: SET SVS(1) VB DLY=50M [ WRITE 'SVS(1) OVERLOAD. CURRENT LIMIT FAILURE.%NL%'; BITSET(FAIL,6); RETURN; ]; GO_TO_TEST: /* Now that the Non-Alliance Supplies have been programmed, branch to measure the supply voltages. Skip the Alliance power-up section. */ BRANCH TEST_POWER; A_PWRUP: /* This section calls the Alliance Power Supply Sequence that will turn on the PS Supplies. To understand what power supply commands are executed by each Sequence, refer to the Sequence definitions in the PROGRAM INITIALIZATION Load Subroutine. */ /*** POWER UP SEQUENCE ***/ PS_ON: /* Turn on UUT Power Supplies...*/ /* Turn on the Alliance power supplies...*/ 6 SET PS SEQUENCE = 1; TEST_POWER: /** MEASURE OUTPUT VOLTAGE OF ALL POWER SUPPLIES AT THE UUT **/ POWER1: SET SCAN AT(383:249); SET MUX AT(CHA=DCMVHI:CHB=DCMVLO); /* Connects Voltage Meter */ MEAS DCV INTO VVAL1 MAX=5.00 VAL=5.00 TOL=5 RDLY=2M FAIL(6)[ IF POWER_TYPE > 0 THEN SUPPLY_NAME='SVS(1)'; ELSE SUPPLY_NAME='PS(1)'; LET SUPPLY_SETTING='5.00 VOLT'; BRANCH PWR_FAIL; ]; CLEAR MUX; CLEAR SCAN; PWRUP_DONE: /* If program gets here, then power up is OK. */ BRANCH PWROK; /****************************************************/ /** IF any power supply voltage measurement FAILs, **/ /** generate diagnostic message and ABORT testing. **/ /** If power is OK, Branch to PWROK. **/ /****************************************************/ PWR_FAIL: WRITE ID=MESFILE'%NL% %NL%'; WRITE ID=MESFILE '%037%%S%%NL%%036%UUT %S% SUPPLY FAILED.%NL%' SUPPLY_NAME,SUPPLY_SETTING; WRITE ID=MESFILE'VOLTAGE WAS %F%V. %NL%'VVAL1; WRITE ID=MESFILE'TESTING ABORTED. %NL% %035%%NL%'; PWROK: CLEAR MUX; CLEAR SCAN; LET UUT_POWER_STATUS = 'ON'; LOG; /* re-enable logging */ CALL CNTRL_C(CONTROL='ON'); /* enable control C processing */ END SUBROUTINE PWRUP; SUBROUTINE PWRDN(); /* POWER DOWN ROUTINE */ /** This Subroutine is used to turn UUT Power off. **/ /** If power is already off, then don't execute this subroutine! **/ IF UUT_POWER_STATUS = 'OFF' THEN RETURN; PWRD: CALL CNTRL_C(CONTROL='OFF'); /* disable control C processing */ /* Determine whether to execute Alliance or Non-Alliance power-down statements. */ 7 IF POWER_TYPE > 0 THEN BRANCH NA_ZERO; ELSE BRANCH A_ZERO; NA_ZERO: /*** PROGRAM NON-ALLIANCE POWER SUPPLIES TO ZERO VOLTS ***/ SVS1_OFF: SET SVS(1) OFF; /** Now that Power is turned off - Discharge any capacitive voltage on the power nodes... **/ CALL DISCHARGE_POWER(); BRANCH OPEN_NA_RELAYS; A_ZERO: /*** PROGRAM ALLIANCE POWER SUPPLIES TO ZERO VOLTS ***/ PS_OFF: SET PS SEQUENCE = 2; /** Now that Power is turned off - Discharge any capacitive voltages on the power nodes... **/ CALL DISCHARGE_POWER(); /* Branch to open the Non_Alliance power supply relays...*/ BRANCH OPEN_A_RELAYS; OPEN_NA_RELAYS: /**********************************************************/ /* CAUTION: */ /* */ /* The next several test statements open "connect relays" */ /* for testers with Non-Alliance power supplies. */ /* */ /* Please make sure the board is DISCHARGED before these */ /* relays are opened. */ /* */ /**********************************************************/ SVS1_OPEN: CLEAR SVS(1); /* ISOLATION RELAY SVS IN SLOTS 1-3 */ IF GR_TARGET = '2282' THEN SET PIO(0) HRLY(OPEN 7); BRANCH PWRDN_MSG; OPEN_A_RELAYS: /* Disconnect the Alliance power supply relays. Please make sure UUT voltages are discharged before executing the following test programming statements. UUT power voltages can be discharged by calling the DISCHARGE_POWER subroutine. */ PS_OPEN: /** Disconnect Alliance Supplies...**/ SET PS SEQUENCE = 3; PWRDN_MSG: WRITE'POWER REMOVED FROM PC BOARD.%NL%%NL%'; SET PIO(0) HRLY(OPEN 3); /* GND RLY */ 8 LET UUT_POWER_STATUS = 'OFF'; CALL CNTRL_C(CONTROL='ON'); /* enable control C processing */ END SUBROUTINE PWRDN; SUBROUTINE DISCHARGE_POWER(); /**********************************************************/ /** This discharge routine will remove any existing **/ /** capacitive voltage from the UUT prior to test **/ /** completion and opening of the power supply relays. **/ /** **/ /** NOTE: In some instances, the UUT should have **/ /** its capacitive voltage discharged at the **/ /** start of the test program. **/ /**********************************************************/ /** Declare variables local to this Subroutine **/ DECLARE CNT; DECLARE VVAL3; NOLOG; /* Turn off Logging during this Subroutine */ DISCHARGE1: SET SCAN AT(383:249); /* Connect Scanner to Power nodes */ SET MUX AT(CHA=DCMVHI:CHB=DCMVLO); /* Connect Voltage Meter */ MEAS DCV DCM INTO VVAL3 MAX=60; /* Measure Voltage */ IF ABS(VVAL3) < 10 THEN [ /* Absolute Voltage <10V. Use 10 ohm Resistor to Discharge */ IF GR_TARGET = '2282' THEN SET STM RLY(27,47,48); ELSE SET STM RLY(1,2,21,23); ]; IF ABS(VVAL3) >= 10 THEN [ IF ABS(VVAL3) <= 60 THEN [ /* Absolute Voltage >10V and <60V. Use 82 ohm STM Resistor */ IF GR_TARGET = '2282' THEN SET STM RLY(23,47,48); ELSE SET STM RLY(1,2,18,20); ]; ELSE [ WRITE ID=MESFILE 'WARNING: MEASURED VOLTAGE ACROSS 383:249 > 60V!%NL%'; WRITE ID=MESFILE 'DISCHARGE VOLTAGE USING FIXTURE RESISTOR!%NL%%NL%'; ]; ];LET CNT=0; /* Set Counter to 0 */ 9 DSCHG_M1: MEAS DCV DCM INTO VVAL3 HI=+.05 LO=-.05 DLY=50M MAX=50 FAIL() [ LET CNT=CNT+1; IF CNT<100 THEN BRANCH DSCHG_M1; IF POWER_TYPE > 0 THEN LET SUPPLY_NAME='SVS(1)'; ELSE LET SUPPLY_NAME='PS(1)'; WRITE ID=MESFILE 'FAILED TO DISCHARGE %S%%NL%' SUPPLY_NAME; WRITE ID=MESFILE 'POWER NODE=VCC, REFERENCE NODE=GND%NL%'; WRITE ID=MESFILE 'MEASURED %F%%035%%NL%%NL%' VVAL3; ]; DSCHG_CLR1: CLEAR MUX; CLEAR STM; CLEAR SCAN; LOG; /* Turn on Logging again */ END SUBROUTINE DISCHARGE_POWER; Practice using the Power Editor, generate the test program and fixture data, and then release the fixture reports. 1. Select Power Supply Editor from the toolbar. 2. Load System Configuration as 2286sys. 3. Load Circuit Data (IDD). 4. Enter required information: +5 Volts, 2 Amps, PS1. 5. Generate a Power Test Program and FWI file. 6. Review program and report. Generating a Test Program After completing this module, you should be able to: Generate a test program (TPG). Describe the purpose of each of the files used as input by ATG and each file generated by ATG. Describe how the ATP, DTP, HTP, and BTP files are generated. Use ATO to modify the ATG processing. Merge ATP, DTP, PTP, HTP and BTP files to create the TPG. 10 ATG Input Filename AtoWithTemporaryNails Contains Test program statements, routines and instructions for ATG to customize the test program. 11 AtgInternalWork IddWithTemporaryNails PowerTestProgram Circuit Description file that has been compiled into a machine usable format. Component pin data, temporary node lists and Driver/Sensor Data. Power test data which can be translated and run on the system to check power node wiring and voltages being applied to the UUT. ATG Output Filename AnalogTestProgram DigitalTestProgram HybridTestProgram BscanTestProgram TpgWithTemporaryNails AnalogAtgResults DigitalAtgResults HybridAtgResults BScanAtgResults MergeResults Contains Analog Test Program created by ATG to test analog components. Digital Test Program created by ATG to test Digital components. Hybrid Test Program created by ATG to test Hybrid components. Boundary Scan Test Program created by ATG to test Boundary Scan components. Source test program that combines the results of all test program files. Result data for all analog components tested, showing libraries used and problems generating test. Result data for all digital components tested, showing libraries used and problems generating test. Result data for all hybrid components tested, showing libraries used and problems generating test. Result data for all boundary scan components tested, showing libraries used and problems generating test. Combined results of all message files. Practice using the ATG Monitor Page, generate the test program files, and review files. 1. Set up and run ATG Step 2. 2. Review the importance of all generated files. In-circuit Test Fixtures After completing this module, you should be able to: Describe different types of fixtures. Determine which type of test fixture should be built based on manufacturing needs and cost factors. Choose a fixture vendor from GenRad’s current vendor list. Understand the process used for building a test fixture. Understand how to attach a test fixture to the receiver and 12 attach the UUT to the test fixture. Describe the tools and the process used to verify that the fixture functions properly. Each different printed circuit board requires its own test fixture. You have 2 options in developing your fixture: Buying an assembled test fixture from a fixture manufacturer. Assembling a fixture from a kit purchased from a fixture manufacturer. GenRad does not recommend building your own fixture unless you have a precision drill machine. Most users purchase an assembled fixture from a fixture manufacturer. Nails are assigned to UUT test points without regard to physical nail and testpoint locations Advantages: does not require UUT testpoint X-Y data. Uses the minimum number of D/S boards. Disadvantages: debug and ECOs are may take more time. UUT test points are assigned to nails which are as close as possible. Advantages: greater measurement accuracy and easier digital debug and ECOs. Fewer wires must be added during debug. Disadvantages: more D/S boards are required. Nails are in direct contact with the interface board. Advantages: high signal integrity, low maintenance, minimal debug, physically smaller. Higher degree of uniformity between fixtures. Disadvantages: ECOs are not easy to implement and fixtures are somewhat more expensive, except when you are having multiple identical fixtures built. Two types of Opens Xpress fixture hardware OFM board is located on the fixture overclamp and is connected to the interface board with a ribbon cable. Opens probes are placed directly over the device under test and connected to the OFM board by a wire. The Buffer/MUX type fixture has the Buffer board mounted on the overclamp connected to the Mux board with a ribbon cable. The Mux board is mounted on the interface board. Opens probes are placed directly over the device under test and connected to the Buffer board by a wire. Composed of two separately controlled sides. Allows placement of two boards on the fixture. Made to work in conjunction with the specific type of handler you have. Used in automated production lines 13 Two different length nails used. One set of nails makes contact in only one position, the other set of nails makes contact in both positions. Use to disconnect nails from sensitive circuits on the UUT. Made to test many boards built in a panel, all at one time. Generating Fixture Data After completing this module, you should be able to: Describe how the Nail Assignment Monitor Page works. Use the Nail Assignment Monitor Page to assign permanent nails and generate the fixture reports. Describe the purpose of and interpret the sections of each fixture report. Use the Translate Monitor Page to generate an object code, which verifies that no MUX conflicts exist. Generates all of the reports necessary to produce the UUT fixture. Assigns target nails to the test program files if necessary. Generates a FixtureTestProgram file for verifying the fixture. Generates reports. Translate generates an object code and symbol table. 14 The Power Test Program and Fixture Test Program can also be translated and run as stand-alone tests. Allows you to specify how to assign permanent nails to your test program. Performs the most compact and efficient assignment of nail resources. Performs a geographic nail assignment for use with short-wire fixtures. Report Contains FixtureAtgResults Fixture section of the AnalogTestReport file. FixtureTestProgram Program generated to check that each nail in the fixture makes proper contact. NailAssignmentListing Lists errors and warnings found during Nail Assignment. NailAssignmentReport All Nail Assignment information sorted by assigned nail. NailContactList A one line description of each nail 15 NailFixtureReport NailWireLength NailDatabase and its connection information. Nail information in a fixture wiring format. Output report generated for short wire nail assignment. Temporary nail mapping to actual nails, sorted by temporary nail number. /* Target system: 2286 Adaptor: 2286 */ /* atg.exe__40 t1 8-NOV-96 10:31 PAGE 1.1 */ /* FIXTURE VERIFICATION TEST PROGRAM */ DECLARE BSTRING FAIL(1); DECLARE CSTRING YN(1); ORG: WRITE '%033%H%033%J'; WRITE 'DO YOU HAVE A FIXTURE SHORTING PLATE ( Y OR N ) ? '; READ '%S%' YN; IF YN='Y' THEN BRANCH TSTOPEN; IF YN='N' THEN BRANCH TSTSHRTN; WRITE '%033%H%033%JPLEASE ANSWER "Y" OR "N"'; DELAY 1.5; BRANCH ORG; TSTOPEN:WRITE '%033%H%033%J'; WRITE 'PRESS START/CONTINUE WHEN THE SHORTING PLATE IS PROPERLY'; WRITE ' MOUNTED.%NL%'; READ '%S%' YN; TEST OPENS DISJ AT(1-124,129-132,137-140,145-148,153-156,161,162, 169,170,177,178,185,186,193) [WRITE '%NL%%NL%TSTOPEN '; WRITE 'FIXTURE FAILURE ........ SEEK ASSISTANCE'; BRANCH DONE;]; WRITE 'PRESS START/CONTINUE WHEN THE SHORTING PLATE IS'; WRITE ' REMOVED.%NL%'; READ '%S%' YN; BRANCH TSTSHRT; TSTSHRTN:WRITE '%033%H%033%J%NL%'; WRITE 'REMOVE UUT OR SHORTING PLATE FROM FIXTURE IF'; WRITE ' PRESENT.%NL%%NL%'; WRITE 'PRESS START/CONTINUE TO RUN FIXTURE SHORTS TEST. '; READ '%S%' YN; TSTSHRT:TEST SHORTS AT(1-124,129-132,137-140,145-148,153156,161,162,169,170,177,178,185,186,193) [WRITE '%NL%%NL%TSTSHRT '; WRITE 'FIXTURE FAILURE ........ SEEK ASSISTANCE';]; DONE: WRITE '%NL%%033%Y%067%%040%*** TEST COMPLETED *** '; WRITE 'PRESS START/CONTINUE TO REPEAT THIS PROGRAM'; 16 END; GENRAD 2286 TEST LANGUAGE TRANSLATOR USER OPTIONS: CONFIGURATION FILE: C:\GenRad\228X\config\2286sys GENERAL WARNINGS ARE NOT DISABLED TARGET ANALOG SUBSYSTEM IS NON_ICA IDENTIFY ICA ONLY TESTS WITH ERRORS programs\FixtureTestProgram THU 07-NOV-96 13:27:41 BEGINNING SYNTAX PASS FOR programs\FixtureTestProgram BEGINNING OBJECT CODE GENERATION PASS GENRAD 2286 TEST LANGUAGE TRANSLATOR tlc.exe__40 ***TESTS THAT WILL ONLY EXECUTE ON ICA TESTERS: 0 TRANSLATION ERRORS: 0 TRANSLATION WARNINGS: 0 2286 NAIL ASSIGNMENT IN PROGRESS Target Machine: 2286 Software ID: nas.exe__40 Mode: NEW Board Name: board1 Date: 07-NOV-96 13:27:06 Process: Copying Input TPG File Process completed: 0 errors detected 0 warnings detected Process: Creating Nail Record File (.VPN) Process completed: 0 errors detected 0 warnings detected Process: Creating Nail Assignment File (.VPR) Process completed: 0 errors detected 0 warnings detected Process: Mapping old nails to new Process completed: 0 errors detected 0 warnings detected Process: Creating Nail Database File (.NDB) Process completed: 0 errors detected 0 warnings detected Process: Updating TPG File Process completed: 0 errors detected 0 warnings detected Process: Copying Input CKT File Process completed: 0 errors detected 17 0 warnings detected Process: Updating CKT File Process completed: 0 errors detected 0 warnings detected Process: Copying Output CKT File Process completed: 0 errors detected 0 warnings detected Process: Creating Nail Fixture Report File (.NFR) Process completed: 0 errors detected 0 warnings detected Process: Creating Nail Assignment Report File (.NAR) Process completed: 0 errors detected 0 warnings detected Process: Creating Nail Connection Report File (.NCL) Process completed: 0 errors detected 0 warnings detected Process: Updating IDD File Process completed: 0 errors detected 0 warnings detected Process: Copying Output TPG File Process completed: 0 errors detected 0 warnings detected NAIL ASSIGNMENT COMPLETED Cumulative errors: 0 Cumulative warnings: 0 The NailDatabase file can be used to control (customize) how Nail Assign assigns nails. The NailDatabase file contains the following sections. Section Purpose %NAILMAP Specifies actual nails to be used in the test program and to force nails to specific nodes. Can also be used to run Nail Assign on a board that already has a wired fixture. %NAILLOC Forces nail assignment to locate a probe under a particular device pin. %NAILNOT Notifies nail assignment not to use particular nails. %NONAIL Specifies nodes from the CircuitDescription which are not going to be nailed. %HIPRIO Specifies high priority nodes for short wires. %LOPRIO Specifies low priority nodes for short wires. /* 2286 NAIL DATABASE REPORT Page 1 Generated by nas_r_310 18 Nail Assignment Mode NEW .TPG Filename sy:demo.tpx Report Date 16-OCT-95 16:47:27 Report Name sy:demo.ndb Number of Nails Required by TPG Clock Drive 2 Clock Sync 1 Fast 188 Nail Range Assigned Requested Clock Drive 9 - 10 1 - 16 Clock Sync 1 - 1 1 - 8 Fast 1 - 608 1 - 640 -----------------------------------------------------------*/ %NAILNOT; /* leave free for OX */ F3-F16; F18-F32; F609-F640; %NAILLOC; /* Force Nail Assign to place probes on test points */ TP32.1 ; TP35.1 ; TP36.1 ; TP38.1 ; TP40.1 ; TP41.1 ; TP42.1 ; TP43.1 ; TP45.1 ; TP46.1 ; TP47.1 ; TP48.1 ; TP49.1 ; TP50.1 ; TP54.1 ; TP55.1 ; TP56.1 ; TP57.1 ; TP58.1 ; TP59.1 ; TP60.1 ; TP61.1 ; TP62.1 ; TP63.1 ; TP64.1 ; TP65.1 ; TP66.1 ; TP67.1 ; TP68.1 ; TP69.1 ; TP71.1 ; TP73.1 ; TP75.1 ; TP76.1 ; TP77.1 ; TP78.1 ; TP79.1 ; TP80.1 ; TP81.1 ; TP82.1 ; TP84.1 ; TP85.1 ; TP86.1 ; TP87.1 ; TP89.1 ; TP90.1 ; TP92.1 ; TP94.1 ; TP95.1 ; TP96.1 ; TP97.1 ; TP98.1 ; TP99.1 ; TP100.1 ; /*Section of code deleted for this sample file. */ TP270.1 ; TP271.1 ; TP272.1 ; TP273.1 ; TP274.1 ; TP275.1 ; TP276.1 ; TP278.1 ; TP279.1 ; TP280.1 ; TP281.1 ; TP284.1 ; TP285.1 ; TP286.1 ; TP288.1 ; TP289.1 ; TP290.1 ; TP291.1 ; TP292.1 ; TP293.1 ; TP294.1 ; TP296.1 ; TP297.1 ; TP298.1 ; TP300.1 ; TP1.1 ; TP2.1 ; TP3.1 ; TP4.1 ; TP5.1 ; TP6.1 ; TP7.1 ; TP8.1 ; TP9.1 ; TP10.1 ; TP11.1 ; TP12.1 ; TP13.1 ; TP14.1 ; TP15.1 ; TP16.1 ; TP17.1 ; TP18.1 ; TP19.1 ; TP20.1 ; TP21.1 ; TP22.1 ; TP173.1 ; TP169.1 ; TP151.1 ; TP153.1 ; TP155.1 ; TP156.1 ; TP157.1 ; TP158.1 ; TP159.1 ; TP160.1 ; TP161.1 ; TP162.1 ; TP163.1 ; TP165.1 ; TP167.1 ; %NAILLOC; /* Shows temporary to target nail maping */ +TP115.1 <- CD9; +TP122.1 <- CD10; +TP129.1 <- CS1; +TP87.1 <- F249; +TP77.1 <- F383; +TP122.1 <- F104; +TP141.1 <- F119; +TP233.1 <- F298; +TP234.1 <- F329; 19 +TP236.1 <- F345; +TP225.1 <- F410; +TP114.1 <- F71; +TP118.1 <- F55; +TP112.1 <- F79; +TP239.1 <- F130; +TP270.1 <- F49; +TP269.1 <- F42; +TP296.1 <- F241; /*Section of code deleted for this sample file. */ +TP264.1 <- F353; +TP237.1 <- F258; +TP261.1 <- F290; +TP2.1 <- F52; +TP18.1 <- F511; +TP151.1 <- F17; +TP17.1 <- F400; +TP163.1 <- F505; +TP257.1 <- F337; +TP10.1 <- F463; +TP159.1 <- F489; +TP43.1 <- F544; +TP158.1 <- F473; +TP16.1 <- F447; +TP13.1 <- F416; +TP155.1 <- F426; +TP161.1 <- F442; +TP11.1 <- F432; +TP98.1 <- F479; +TP156.1 <- F457; +TP103.1 <- F456; +TP223.1 <- F402; +TP253.1 <- F306; /* TEMP NAIL NUMBER -> ASSIGNED NAIL NUMBER Page: 8 ----------------------------------------------------*/ %NAILMAP 2286 NEW; CD1-> CD9 ; CD2-> CD10 ; CS1-> CS1 ; F1-> F249 ; F2-> F383 ; F3-> F104 ; F4-> F119 ; F5-> F298 ; F6-> F329 ; F7-> F345 ; F10-> F410 ; /*Section of code deleted for this sample file. */ F38-> F495 ; F39-> F577 ; F40-> F536 ; F41-> F520 ; F42-> F545 ; F43-> F567 ; /* TEMP NAIL NUMBER -> ASSIGNED NAIL NUMBER Page: 9 ----------------------------------------------------*/ F44-> F375 ; F45-> F183 ; F46-> F65 ; F47-> F170 ; F48-> F177 ; F49-> F138 ; 20 F50-> F279 ; /*Section of code deleted for this sample file. */ F93-> F145 ; F94-> F210 ; F95-> F233 ; F96-> F328 ; /*TEMP NAIL NUMBER -> ASSIGNED NAIL NUMBER Page: 10 ------------------------------------------------------*/ F97-> F185 ; F99-> F169 ; F100-> F218 ; F104-> F186 ; F105-> F305 ; F106-> F97 ; F107-> F225 ; /*Several pages of code deleted for this sample file. */ /* TEMP NAIL NUMBER -> ASSIGNED NAIL NUMBER Page: 12 ------------------------------------------------------*/ F273-> F442 ; F274-> F432 ; F276-> F479 ; F278-> F457 ; F279-> F456 ; F280-> F402 ; F281-> F306 ; 21 No .OBC file is produced when errors are detected. Translator reports errors in test statements that contain ICA-specific parameters. Select the ERRORS option if the program is to be run on both ICA and Non-ICA systems. .OBC file is produced. Translator reports warnings in test statements that contain ICA-specific parameters. Select the WARNINGS option when you want to know if a test program will run on Non-ICA systems. Translator does not report errors or warnings related to ICAspecific parameters. Select the NEITHER option when you want the test program to run only on the ICA testers. Translation takes place after nail assignment. Converts a readable source language test program into machine readable binary files. Generates listing files applicable to the MergedTestProgram. Reports Contains ObjectCode Binary version of the MergedTestProgram. FixtureObjectCode Binary file the tester uses to test the fixture. SymbolTable Binary file with pointers to labels and variables used for modifying or debugging the test set. FixtureSymbolTable Binary file containing pointers to labels and variables used for modifying or debugging the fixture. TranslatorListing Error and warning messages concerning Language statements, syntax and nail assignment conflicts. GENRAD 2286 TEST LANGUAGE TRANSLATOR USER OPTIONS: CONFIGURATION FILE: C:\GenRad\228X\config\2286sys GENERAL WARNINGS ARE NOT DISABLED TARGET ANALOG SUBSYSTEM IS NON_ICA IDENTIFY ICA ONLY TESTS WITH ERRORS programs\MergedTestProgram THU 07-NOV-96 13:29:53 BEGINNING SYNTAX PASS FOR programs\MergedTestProgram BEGINNING OBJECT CODE GENERATION PASS 22 GENRAD 2286 TEST LANGUAGE TRANSLATOR tlc.exe__40 ***TESTS THAT WILL ONLY EXECUTE ON ICA TESTERS: 0 TRANSLATION ERRORS: 0 TRANSLATION WARNINGS: 0 This step allows you to select the files required by the manufacturer to build the test fixture. Also NailWireLength for Short Wire Fixtures Only. Also CAD drill files, if available. When receiving a fixture from a contract manufacturer, use this checklist to verify that it functions properly. Step Action 1. Look for visible damage. 2. Mount the fixture and check for vacuum leaks. 3. Run a shorts test. 4. Run a contact test. 5. Verify that all specified requirements are met. Practice using the Nail Assignment and Translate Monitor Pages, generate the fixture data and reports, and then select the fixture reports for release. 1. Set up and run Nail Assignment. 2. Review reports. 23 3. Run Translate. 4. Select reports for release to a fixture vendor. Debugging a Test Program After completing this module, you should be able to: Describe how component failures and messages are coded. Use the debugging process to assist you when debugging a test program. Describe the purpose of each debug tool. Use the ALLFAULT command to generate a detailed fault coverage report. Debug analog component tests using the analog debug commands. Debug digital component tests using the digital debug commands. Insert debug changes into the test program using the update utility. A failure occurs when the measured value of a component does not meet its given specification or when a test statement cannot be performed as specified. When a test statement fails, the fail vector is first set, unless you explicitly inhibit it. Then failure reporting options are performed (message assignments and subroutine execution). Finally, the error-command is executed if one is specified. Analog component tests can fail for any of the following reasons. A tested value is outside the set limits. The requested measurement is not made because of unanticipated UUT behavior. This can include problems such as a current source operating in voltage compliance or current limiting of a voltage source. The requested measurement is not made because the test system malfunctioned. Digital tests can fail for reasons similar to analog test failures. Digital test(s) commonly fail because a component output pin did not reach the expected logic state. Analog Test Failure and/or Digital Test Failure reasons The FAIL vector must be DECLAREd as a bit string variable at the start of the test program. At that time, all cells (bits) in the vector are reset to zero. Do not use the FAIL vector in a LET statement, it may change the FAIL settings, resulting in erroneous operations. The FAIL( ) parameter in an instrumentation statement prevents that statement from having any effect on the FAIL vector. If FAIL(n) is omitted from an instrumentation statement, 24 FAIL(1) is assumed. Failures occurring during the test program typically set bits within the FAIL BSTRING. The program fails if any bits in the FAIL BSTRING remain set at the end of the test. When a test statement fails, the specified FAIL vector bit is set to 1, unless you explicitly inhibit it. At the end of the program, if any FAIL vector bit remains set, the FAIL message is displayed. Otherwise, the PASS message is displayed. Setting/clearing fail bits have no effect on failure processing. FAIL bits 1 - 100 are reserved for GenRad tests. User generated tests should use FAIL bit > 100. FAIL bits can be interrogated and custom diagnostics printed based on which FAIL bits are set. DECLARE BSTRING FAIL(m); | TEST/MEAS ----- FAIL(n)-----; Argument TEST/MEAS FAIL (m) (n) Description Command keywords for instrumentation statements. Keyword for FAIL vector bit string. Maximum number of cells (bits) in the FAIL vector. Must be DECLAREd at the start of the program. Number of the FAIL cell that is set if the instrumentation statement fails. If FAIL(n) is : - Omitted from the statement, FAIL(1) is assumed. - Specified, execution of the statement has no effect on the FAIL vector. TEST DCI DCS FAIL(7); FAIL bit 7 is set if the current source cannot supply enough voltage to force the current for which the DCI is programmed, that is, voltage compliance error. Because a fail bit is set, the FAIL indicator is turned on at the end of the program. TEST DCI DCS [BRANCH CURRENTERR;]; The default FAIL bit 1 is set if the current source is not in voltage compliance. If this occurs, the FAIL indicator is turned on at the end of the program. In addition, a branch to the label CURRENTERR is taken. TEST DCI DCS FAIL( ); No FAIL bit is set even if the current source is not in voltage compliance. A FAIL(null) can be included in an instrumentation 25 statement as shown here to inhibit a test failure from causing the program to fail. The test failure is masked, and the FAIL indicator remains off. TEST DCI DCS FAIL(7); IF FAIL(7) THEN BRANCH N30; If the current source is not in compliance, set FAIL bit 7. Test the status of FAIL bit 7 by means of the IF-THEN-ELSE statement. If FAIL(7) is set, indicating a failure, branch to N30. IL(27) OS(156) OL(156) FAIL(156); FAIL bit 156 is set if nail 156 is not low at the above digital test statement. Failure-reporting options are user-defined routines and messages. Specify which failure-reporting options are used when an instrumentation statement fails. Can be specified as parameters within individual instrumentation statements or can be predefined with a USE statement. System test devices supported include: DCS, DCM, ACZ, RM, ARITH, CONTACT, SHORTS, OPENS, and BURST. The routines have access to special diagnostic variables defined by the system when an instrumentation statement fails. System failure variables do not need to be declared. Variables cannot be read into by an I/O instruction or by the TEST/MEAS statement INTO parameter, and they cannot be assigned a LET statement value. These variables can be tested as part of the IF condition in an IF-THEN-ELSE statement. At the start of test program execution, the values of all failure options and variables are reset; that is, character-string variables are set to nulls and floating-point variables are reset to zeros. These options and variables may then be assigned values for individual instrumentation statements by including the options as parameters in each statement. The USE statement defines the default options for all subsequent FAILed statements; that is, instrumentation statements without explicit failure parameters revert back to the failure options specified by the most recent USE statement. When explicit failure parameters are used in a statement, the options specified by those parameters apply only to that statement. MEAS R INTO RVAL . . . . . FSUB=FAILSUB DMSG=‘NOMINAL’; USE FSUB=FAILSUB DMSG=‘NOMINAL’; NOFSUB FSUB=name-of-routine 26 PMSG=‘user-part-message’ DMSG=‘user-diagnostic-message’ CMSG=‘user-component-message’ Inhibits the calling of subroutine FSUB in the event of a failure in an instrumentation statement. Used to replace a [CALL subroutine] error-command in an instrumentation statement. If the statement fails, the FAIL bit, if specified, is set; then the failure routine is invoked. If an [error-command] is specified, it is executed after completion of the failure routine. Failure routines must be DECLAREd, the same as any other subroutines, but they cannot have an argument list. Instead, they obtain information about the failure from special system failure variables. These user-defined messages are available to the failure routines. Each text string message can be up to 80 characters and, may be specified in a USE statement or as a parameter in an instrumentation statement. Test strings do not adhere to the formatting rules for other WRITE statements. For a single percent character (%) to appear as text, use %045% (octal 045). Do not use %% to represent a single % character, in user-defined messages, as both percent symbols appear in the message. Argument FTYPE Description Two-character string indicating the component type tested/measured in the last FAILed statement. R V I RP RS Resistance Voltage Current Parallel Resistance Series Resistance CP Parallel Capacitance CS Series Capacitance LP Parallel Inductance LS XP XS Series Inductance Parallel Reactance Series Reactance ZM Impedance Magnitude QQ Quality = XS/RS = RP/XP DD Dissipation = RS/XS = XP/RP VS Voltage Source (TEST DCS DCV) 27 IS Current Source (TEST DCS DCI) AR Arith (TEST ARITH) DG Digital FSTAT Indicates the status of the test results for the last FAILed instrumentation statement *LOW Measured value was low *HIGH Measured value was high *FAIL Measurement failure #ERR Testing error occurred FLABEL Label associated with last FAILed instrumentation statement, that is, the last label or subroutine used before the failure. FDMSG DMSG associated with the last FAILed instrumentation statement. FPMSG PMSG associated with last FAILed instrumentation statement. FCMSG CMSG associated with the last FAILed instrumentation statement. FMEAS Measured value from the last FAILed instrumentation statement. FHI HI limit value (if available) from the last FAILed instrumentation statement, or some value greater than 1.0E30 (to indicate that no HI limit is available). FLO LO limit value (if available) from the last FAILed instrumentation statement, or some value less than -1.0E30 (to indicate that no LO limit is available). Failure messages and current values of the failure variables can be written to the system message file (MESFILE). WRITE ‘data’ ; WRITE ID=MESFILE ‘data’ ; Specifies the I/O channel for the system message file, which is defined by the MESsage option on the DIAGNOSE monitor page. This MESFILE channel should not be explicitly OPENed or CLOSEd. The MESFILE device, STRIP_PRINTER, CRT, or FILE, is determined by the DIAGNOSE page Messages to field. DECLARE FAILSUB( ); SET MUX AT (6:6:8:8:REF=5,6,8,11); USE FSUB=FAILSUB; /*TEST NAIL 89*/ SET SCAN AT (117:117:89:89); MEAS R INTO RVAL V=.1 HI=10 MAX=1 CMSG=‘NAIL 89’ DMSG=‘OPEN FROM 117 TO 89’; /*TEST NAIL 57*/ SET SCAN AT (117:117:57:57); 28 MEAS R INTO RVAL V=.1 HI=10 MAX=1 CMSG=‘NAIL 57’ DMSG=‘OPEN FROM 117 TO 57’; /*START RESISTANCE TEST*/ SET MUX AT (6:8:9:10:REF=5,6,11); USE DMSG=‘NOMINAL’; /*TEST R6*/ SET SCAN AT (135:134); MEAS R INTO RVAL V=200M HI=4.9K LO=4.4K CMSG=‘R6’; SUBROUTINE FAILSUB( ); WRITE ID=MESFILE ‘%S% FAILED %S%%S%%NL%’ FCMSG,FTYPE,FSTAT; WRITE ID=MESFILE ‘%S% MEASURED:%5G%%NL%’ FDMSG,FMEAS; Use the [error-command] construct, also referred to as a fail bracket, in an instrumentation statement to specify one or more commands for execution when the statement cannot be performed or when a test fails. The error-command may be a simple statement, a single command, a compound statement, or multiple commands. For example: TEST Z LO=550 FAIL(5) [CALL ZFAIL( );]; If the measured impedance is less than 550 W, set FAIL bit 5, then execute subroutine ZFAIL. The [error-command] construct is useful for reporting powersupply power-up errors. Power-up errors occur when a UUT power supply fails to reach a desired value within an allotted time, or values settle outside of specified limits. Check for these errors, since test statements associated with the failed UUT power supply do not execute. Unless specific error statements are included within a test program, there is no way to inform the Operator that testing has been halted. If the Operator is not notified that testing has not been executed, he may assume the UUT passed all tests and label it good. Check UUT power-supply power-up errors with errorcommand brackets included with the command keywords SET, TEST, and MEAS. Specific requirements are discussed under each UUT power-supply description in the GR228X Test Language Reference Manual. The following command within the error command brackets is done automatically by the power supply editor. WRITE ID=MESFILE‘POWER SUPPLY FAILURE, TESTING HALTED%NL%’; By including this message in the system message file, there is no chance of its being overlooked. UUTs that have not been thoroughly tested will not be falsely labeled as “good”. If 29 desired, modify the above message to include other information such as the values that caused the failure. A digital test step fails when a sensor detects a logic state different from the expected state specified by OH or OL. In addition, the burst is considered to have failed. Because the digital testing software includes automatic error reporting, additional error-handling subroutines are usually not required for digital test bursts. If necessary, the END BURST statement can include a jump to an error-handling subroutine, with whatever parameter-passing statements are required. 30 Refer to Appendix A for the Monitor Page filenames. 31 The GR228X system has easy to use debugging tools that can decrease the time you spend debugging your test programs. Measuring Fault Coverage (ALLFAULT) Manual Debug using the Diagnose Page - Debug Mode 32 Program Xplorer Autodebug Digital Waveform Display Array Plot Tool For details, refer to the GR228X Test Program Debug Manual. ALLFAULT is a Run–Time Debug command that analyzes your test program and generates a report indicating how effective the test is at detecting potential faults. The ALLFAULT generated report can provide A test summary for each component tested using analog instruments. Data is derived from running the analog component tests many times, then reporting the min, max, and standard deviation of the collected measurements. The flags for this test can indicate when a test failed, is measuring too close to a measurement limit, or is unstable from test to test. Digital Fault Insertion results for all digital components that are tested within a burst. It also flags device pins that can not detect open and stuck pin faults. Results for all test program BUSTEST and FORCE sections. It flags BUSTESTS that fail and identifies DISABLE and FORCE sections that have incorrect current measurements. UUT Fault Coverage Summary section that identifies: Analog tests that contain problems which should be debugged Nodes that are missing from the shorts and contact tests UUT components that are not tested using any technique Board summary of digital fault insertion results Digital Bursts that failed and had no fault inserted Digital Bursts that had faults inserted, but failed during reruns UUT components tested using the Opens Xpress technique Bustest statistics information Use the report to identify tests that may need more debugging, or identify components that are missing tests, and can be used to document the test program for other departments. 33 SURROUND Prints the names of all components connected to the specified nail and lists the nails connected to the other pins of the component. COMPONENT Prints to the MES file all interconnect data for the specified component from the .idd file. GUARD Adds the specified nail lists to channels C and GND (in 4 wire mode only). NAIL or NODE Provides connection information about the specified NAIL or NODE according to the .idd file. LOCPIN Provides the NAIL, NODE, and connection information about the location being probed (must be run from “reset” or “waiting to test” state). PRINT Prints current screen display to the strip printer. AVE Typing AVE enables Run Time System (RTS) to make an average measurement. ACCEPT The RTS stores all debug changes by component label until those changes are either ACCEPTED or REMOVED. ACCEPTED changes will be permanently written to the .obc and .dbt files. ACCEPT ALL Is a valid command. DISPLAY NODE/DISPLAY NAIL Enables you to view either node names or nail numbers while debugging the test program. ORDER/PORDER Displays the digital IC timing display by (PINLIST) NAIL or PIN as listed in the command. RERUN or <CR> Causes the current test to be executed again. 34 RERUN = n, Reruns the test “n” times, then gives the highest, lowest, and average readings. RUN Executes the test program or continues executing the next test in the test program. REMOVE ALL Restores the test program to what it was prior to the current set of changes that have been made to the test. REMOVE Removes only changes made to the current test program label. LBLSEL Specifies a BEGIN= label and runs a test. DEPOSIT Changes the value of the variable to the value specified. EXAMINE Displays current value of the specified variable. MULTI Toggles digital waveform display window. PLOT Plots a floating point array. SOH (Single Output High) senses a nail high in a digital burst for only the specified test statement. STEP Steps through analog test. Program Xplorer is a graphical debugging tool for analog tests within the GR228X test program. The Program Xplorer display provides a window environment 35 that enables you to: Modify GR228X instrument statements Determine which nodes surround the Device Under Test (DUT) Plot measurement readings View graphical views of mux connections The Program Xplorer relies on information stored in the .idd and the .wor files. Both files are created during the Verify Circuit test step. Apply/remove guarding with mouse clicks. Autodebug is a debugging tool that uses the Run–Time System (RTS) to debug your test program without programmer interaction. Autodebug performs the actions that you would interactively perform using RTS’s Debug mode. Autodebug assumes that the test program, not the UUT or fixture, is the cause for a test that does not pass. You can edit the Autodebug command file (.ADC) to control which debug changes are performed. When you debug a test program using Autodebug, it recognizes the type of test and applies a sequence of debug commands that attempt to pass the test. The tasks Autodebug can perform on analog tests include: Changing the values of analog test parameters Swapping source and measure Adding a small delay to adjust the guard set Modifying instrument parameters For digital tests that fail or have unknown output states, Autodebug can: Initiate the learning of output states 36 Insert faults using the Digital Fault Insertion (DFI) feature Most of the debug actions that Autodebug initiates require data contained in the in–circuit diagnostic data file (.idd). Although an Autodebug session can be performed without an .idd, useful results generally occur only when an .idd file is supplied. When you test a digital component using the DIAGNOSE monitor page set to Debug mode, a waveform display of the driven and sensed logic states displays. You can view digital debug information by using Test statement Digital waveform The test system also offers unique debugging features for bursts that contain CRC collection and indirect addressing statements. Interpreting data in an array often depends on the ability to display a waveform or part of a waveform and to quickly find what you are looking for. These are the system’s array plotting capabilities. Capability Multiple windows X-Y Coordinates Description Enables you to display up to 20 plot windows at a time. Each window has a unique title. Uses crosshairs to read X-Y coordinates. 37 Multiple waveforms in a single window: Enables you to add waveforms to an existing window, delete waveforms, lock waveforms, and hide waveforms. Window size Enables you to change the Plot window size. Waveform attributes Enables you to select a waveform, change its color, point size and shape, and the type of lines it uses to connect points. Selecting the amount of data to plot: Enables you to plot an entire array or a portion of an array (subarray). Saving, loading, and printing: Enables you to save data from a plot window for a future display. You can load previously saved plot data or print a plot. Magnification Enables you to focus (zoom) on a particular portion of the window. Log10 mode Enables you to convert the display of the X or Y axis on a logarithmic scale. Scrolling Enables you to scroll (shift) the waveform display left, right, up, and down. Help Provides on-line help for the plot window. Practice using the Debug tools to debug a test program. 1 Debug the test program in manual debug. 2 Run the Update Monitor Page 3 Retranslate the test program. Releasing the Test Set to Manufacturing After completing this module, you should be able to: Describe the process used to release a test set to manufacturing. Determine if the test set developed by contract programmers is acceptable. Release a test set. Select, and rename if necessary, the test set files that are required to run the test program in a production environment. Windows NT Explorer enables you to select the files you want released as a test set. Always include circuit preparation files such as the Circuit Description (.CKT), program preparation files such as the Test Program (.TPG), debug files such as the Debug Trace (.DBT), and all Test Set Libraries when backing up the test set, as 38 discussed in Module 3. Release files as <TestSetName>.extension. Create a production batch file to be used by Manufacturing to load and run the test program, if desired. ObjectCode (.OBC) InCircuitDiagnosticData (.IDD) NailDataBase (.NDB) NailContactList (.NCL) DigitalDiagnostics (.DDF) BoundaryScanLibrary (.BSL) DeviceProbeReport (.DPR) PinOpensDiagnostics (.POD) Message (.MES) SymbolTable (.SMT) AtgInternalWork (.WOR) MergedTestProgram (.TPG) Debug (.DBT) DebugTraceOld (.DBO) SingleBoardTpg (.TPS) AutomaticTestOptions (.ATO) CircuitDescription (.CKT) DigitalTestLibrary (.DTL) AnalogComponentLibrary (.ACL) AnalogTestLibrary (.ATL) HybridTestLibrary (.HTL) NailAssignmentReport (.NAR) NailFixtureReport (.NFR) When receiving a test program from a test program developer, use this checklist to verify that it functions properly. Step Action 1. Check fault coverage on the board. 2. Look over Allfault report. 3. Understand what components are not tested and why. 4. Be sure any specialized tests are performed. Before releasing files to Manufacturing, ensure programs are error free. Select files for release. Back up the test set. Production Batch In-Circuit Diagnostic Data 39 Object Code Symbol Table Merged Test Program Practice releasing the test set to Manufacturing. 1 Select the files you want to release, and then place the files in a new directory. Data Logging and Data Display After completing this module, you should be able to: Describe the purpose of each data logging option (Standard, SEL, and RTDC). Use the Production Test menu within the Preferences Menu to select the logging options. Generate a report. Interpret a Logging file. Use Data Display to view a report. Collects data for all components on the UUT. Amount of test data collected for the components is selected by the Logging options. A combination of +PASSES option and LOG page PLOTS generation is commonly used as a debug tool and is sometimes used as acceptance criteria for Analog tests. Enables you to select the components you want logged and the amount of data logged. Selective logging requires a Selective Options file (.SEL) as input. Provides the most comprehensive data collection control. Can include selectable intervals. Commonly used in a real-time network environment as it allows for transfer of Log data at the end of each test run. RTDC requires a Data Collection Options file (.DCO) as input. Option None Times +Fail +Vals Function Logging is disabled. No .LOG file is created or appended. Time stamps are recorded for all main events associated with executing a test program. Includes the failing label and key for each failed component. Measured values are not logged. Includes any measured value for each failed 40 component. Test limits are not logged. Includes test limits and any test type for all tested components. This option also logs No tests. Enables selective data logging. It provides you with more flexibility in logging test data than other options. +Passes Sel The Report Generator truncates part numbers to 20 characters. Selective logging does not affect Bustest, ScratchProbe, Contact, Opens, or Shorts tests; data is always logged for these test failures. Select all the logging options needed to generate the LOG reports before you begin testing the board. For example, all pass and fail data should be collected when plots are generated. Within digital bursts, the selective logging option treats banks and NAME = the same: Passing tests are identified by the bank or burst label. Failing tests are identified separately by the name of each individual failing component. Log File Example File Explanation SY:BOARD.OBC[09-JAN-91 14:08:17 Program loaded. @09-JAN-91 14:08:27 Test started. R1=1.001(0.995,1.005)R =Shunt resistor test. ALL data logged for passing R1 and message. R2<123.4KR No limits for failing high R2. C1>82.02P(90.00P,110.00P)CS Limits included for failing low C1. C2>87.34PCP No limits for failing low C2. /09-JAN-91 14:09:58 Failing board test finished. ]09-JAN-91 14:10:10 Program unloaded; return to Diagnose monitor. Symbol [ Event Program Loaded Action Load the program by pressing the Load Key, or keypad, or Run key on the keyboard at the DIAGNOSE page. @ Test Started Start the test by pressing the start/continue button on the keypad or Run key on the keyboard. ? Test 41 Aborted Abort the test by pressing the Reset key on the keypad or Control C on the keyboard. After you abort a test, the system prompts: Do you wish to cancel the last board’s logging data [Y/N]? ” Passing board test finished Test completed with no failures (vacuum released). / Failing board test finished Test completed with failures (vacuum released). * Error in test A test error occurred, such as a voltage source overload or a current source compliance condition. & System error A Run-Time System error occurred. ! Test canceled Logged test data for last board was ignored. After a board test is completed, if you decide that the results should be ignored, press Reset or Control Y on the keyboard to display the prompt: Do you wish to cancel the last board’s logging data [Y/N]? Entering Y cancels a test entry in the .LOG file for the previous test. Any other operator action will retain the logged data. The logged data not actually deleted, the canceled test entry enables the Log Report Generator to disregard the logged data for that board. ] Return to Diagnose mode Unloads the test program label key value limits type device message The label is associated with the most-recently executed statement 42 that had a label. Multiple measurements between program labels have identical labels. A key is a one or two-character symbol indicating the result of a test which include: Key = < > # % %B (S (O (B (C (F ~ Description Analog measurement passed Analog measurement failed high Analog measurement failed low No measurement made Digital test failed BUSTEST failure caused by an associated IC SHORTS test failure OPENS test failure BUSTEST failure caused by bus SCRATCHPROBING connection failure CONTACT fixture failure MESFILE delimiter when using real-time data collection Value refers to the measured value when applicable. Limits refer to the acceptable high and low test limits when applicable. Type is a one or two-letter code defining the type of test used to make the measurement, when applicable. Type Associated Test Language Statement AC MEAS DVM ACV AI MEAS ACI ACM AR TEST ARITH AV MEAS ACV ACM AY MEAS [ DVM | ( DMM [VOLTAGE|CURRENT] ) ] CS MEAS ACZ CS CP MEAS ACZ CP DC MEAS DVM DCV * DD MEAS ACZ D EV FTM EVENT * HZ FTM FREQ * I MEAS DCM DCI IS TEST DCS DCI LP MEAS ACZ LP LS MEAS ACZ LS QQ MEAS ACZ Q R MEAS R RA FTM RATIO * RP MEAS ACZ RP RS MEAS ACZ RS S FTM PERIOD * 43 TI FTM INTERVAL * V MEAS DCM DCV VS TEST DCS DCV XS MEAS ACZ XS XP MEAS ACZ XP ZM MEAS ACZ Z IC device type; applicable Messages are always preceded by an = (equal sign) and are added at the end of the log file test entry. You must insert messages for the component in the %VALUE section of the .CKT file using the MSG=’info’ parameter before you can log component failure messages. Digital failure messages are taken from the resulting .IDD file and analog failure messages are taken from the .OBC file. You can log additional messages if the selective logging option is chosen and the MESSAGE = ‘text’ is programmed in the %COMPONENTS section of the .SEL file. 1 Access the Diagnose Monitor page. 2 Choose Mode=TEST, then choose the desired Logging = [option] The other fields may be set to the default. 3 Run the test with a sample lot of boards, GenRad recommends 20-25 board sample lots. If you cannot use a sample lot of boards, use the “gold” debugged board and run the test 20 times. To run the test, enter at the TEST mode prompt: RUN=20 4 Set up the LOG page as follows: Mode=GENERATE Report=PLOTS Plot=ALL The other fields may be set to the default. 5 Running the LOG page will create a .REP file. 6 Print the .REP file and analyze the results. The Selective Logging Control (.SEL) file is composed of three optional sections: %Mode %Format %Components Log Option Selective Logging Options Equivalent TIMES %MODE FAILS=NONE PASSES=NONE; %FORMAT TIMES=YES; +FAIL %MODE FAILS=ALL PASSES=NONE; %FORMAT FAILDATA=LABEL,KEY,DEVICE TIMES=YES; +VALS %MODE FAILS=ALL PASSES=NONE; 44 %FORMAT FAILDATA=LABEL,KEY,VALUE,DEVICE TIMES=YES; +PASSES %MODE FAILS=ALL PASSES=ALL; %FORMAT FAILDATA=ALL PASSDATA=LABEL,KEY,VALUE,LIMITS, TYPE TIMES=YES; /* Set up global data logging options; log fail data for all tests; log pass data for those components listed in the %COMPONENTS section only (R1, C1, and C2).*/ % MODE PASSES = ONLY FAILS = ALL; /* Log subset of fail data; log ALL pass data by default; log time stamps. */ %FORMAT FAILDATA = LABEL,KEY,TYPE,VALUE,DEVICE TIMES = YES /* Components to log for ONLY (or not to log for ALLBUT).*/ %COMPONENTS /* Append a message to the logged test data for R1.*/ R1: MESSAGE = ’Shunt resistor test.’; /* Override global FAIL data options to include LIMITS for C1.*/ C1: FAILDATA = LABEL,KEY,TYPE,VALUE,LIMITS; /* Use global fail data options for C2; all lines in the %COMPONENT section must be terminated with a semicolon.*/ C2: ; Log data during specified sampling intervals. Log data during the intervals between the sampling intervals. Change Data Collection Options on the fly without operator intervention. Select options similar to the Logging options on the DIAGNOSE page. Specify failure messages in the log data file, which can include MESFILE data from the test program. Generate individual and merged log files. Create a new individual log file for each test run. You need this feature for compatibility with the Data Sampling LAST TEST ONLY and the Command file options. Specify a user command file that is executed at the end of each test run. This file can perform any data manipulation you identify. 45 Time period for which the report was generated Number of failing, passing, and total boards tested Total testing, waiting, and elapsed times Average passing, failing, and actual board test times Throughput per hour Total faults and faults per failing board, if failure data was collected Contains current failure data on a component level in addition to board-level statistics. Information includes the total number of failures and faults per failing board for each failing component. Generates a failure trend analysis in this mode if you specify the .LOG and .SUM files to be used in the comparison in the LOGf = fields. Both current and summary failure data are reported, and any significant differences in failure rates for a component are flagged to bring attention to it. Component plots generate a distribution of test measurements over a range on the component-level in addition to total number of failures and board-level statistics. The range is determined by the component test limits and measured values for all logged current data. No trend analysis is performed in this mode. You can generate three types of component plots, using data from: Good boards only Component tests that pass regardless of overall board pass and fail results All logged test data 46 Yields of passing and failing boards Total faults and average faults per failing board Total elapsed times, consisting of total testing time and total waiting time Average board test times: actual time, passing boards test time, and failing boards test time Board throughput per hour: actual overall, passing boards, and failing boards Failure data on the most frequently failing components All component failures sorted by failure frequency or component name A plot of measured component values showing the distribution of measurements for good-boards only, all component passes, or all component measurements The LOG page has two modes: Create summary reports (.SUM files) from logged data (.LOG files) Generate board test reports (.REP files) from log and summary files Fast report generation Multi-line color charts 3-D color pie charts 3-D Histogram charts * Run Chart User-annotated charts * Not currently available on Windows NT Testers 47 Report Name Tester Yield Report Description Provides a graph of tester yields over time. Failure Analysis Report Simultaneously plot opens, shorts, resistors, inductors, capacitors, digital, and other failure types as a percent of all failures over the date range you select. Trend Analysis Report Simultaneously plots opens, shorts, resistors, inductors, capacitors, digital, and other failure types as an average per board for the date range you select. Test Times Report Plots the passing board test time against time. Passing Board Volume Report: Operates slightly different from other reports. The volume must be represented as boards during the time period. Failure Analysis Chart Displays either a pie chart or a bar chart representing the distribution of various failure types. Failing Parts/Components Chart: Graphs the most frequently failing parts or components and displays them in either a pie chart or bar chart. Measured Values Chart Shows how a single analog component is performing. 48 49 Practice using the Data Logging tools. 1 Open GR228X software. 2 Set up the Log Monitor Page and generate an REP report, using the following logging file: 12_10.log 3 Review REP report. 4 Open Data Display from the toolbar. 5 Import the above logging file. 6 Generate Component Overview report. 7 Generate Board information reports. 8 Generate Failure reports. TEST XPRESS Tools Overview After completing this module, you should be able to: Describe the purpose and function of Junction Xpress, Opens Xpress, Cap Xpress, and Orient Xpress. Determine the appropriate testing application for a given test scenario. 50 The GR228X test system can apply three different test techniques for detecting and diagnosing device pin defects: Digital in-circuit test Junction Xpress test technique Opens Xpress test technique NOTE: In many cases, more than one test technique should be used for a single device. For example, a combination of Junction Xpress, to detect opens pins defects, and simple digital vectors, to detect wrong or incorrectly programmed part defects, can provide better coverage than can be provided by either technique alone. 51 Works by detecting the responses at the device outputs to stimulus vectors applied at the device inputs. Proven, reliable technique. When used with the Softprobe or Scratchprobe diagnostic techniques, it is capable of diagnosing open pin faults. Only technique that can reliably detect wrong or incorrectly programmed parts. Requires a model of the DUT. Therefore, it is most useful for those devices that have models in the library or for a model that can be automatically generated. Works by injecting an ac signal into a pin on a semiconductor device and detecting the effects of that signal at another pin on the device. It is a low-impedance measurement technique that is able to detect solder joint defects that have a higher than normal resistance (10-50 ohms). Does not require complex fixture hardware, however, it does require a reliable low-resistance contact between the UUT and the fixture. Preferred technique for testing complex digital parts in certain types of packages, such as PGAs, BGAs, FLIP CHIPs, MCMs, 52 PLCC, SOIC, and COB. Works by detecting the coupling of an ac signal by the capacitor formed by the lead frame of a device and a metal plate adjacent to the device. Requires fixture hardware to provide and support connections to the metal plates. It is a high-impedance technique. Typically, a solder joint will have to exhibit several hundred thousand ohms of resistance before a defect will be detected. However, Opens Xpress is quite insensitive to high contact resistance between the UUT and the fixture. This technique can test non-semiconductor parts, such as connectors, sockets, and bypass capacitors. Preferred technique for testing complex analog or mixed-signal parts, such as DSPs, sound generators, and video processors. 53 Junction Xpress Overview After completing this module, you should be able to: Describe how Junction Xpress tests an IC. Identify the Junction Xpress hardware and software requirements. Use the Junction Xpress Predictor tool to evaluate the usability of the Junction Xpress test technique. Test Signals Emanate from PCB Nails. DC Bias and Detector Applied to one IC Pin. AC Source Applied to Other IC Pin. Detector Measures Harmonic Frequencies. Data Compared Against Test Limits. 54 Detector measures magnitude of harmonic frequencies 10 to 1 difference between good / open IC pin SCO UNIX or NT system with GR228X Software Release 3.2.0 or greater Instruments used are either AFTM, ICA, or ATM Scanner Subsystem Uses same ICT fixture, requires no special probes Note: If Junction Xpress is to run on an AFTM module, instead of an ICA module, three passive components need to be added to the fixture at the AFTM slot position. 55 A 1 0W resistor, with an accuracy rating of 1% or better, rated for 1/4 W or greater, and with a drift characteristic of +/- 100 ppm per degree C or less. A 48 kW to 52 kW resistor, preferably metal film, with an accuracy rating of 1% or better, rated for 1/8 W or greater, and with a drift characteristic of +/- 100 ppm per degree C or less. A 0.01 mF capacitor, rated at 1%, with low dielectric absorption such as polypropylene, polycarbonate, polystyrene, NPO ceramic, etc. 56 Use the Junction Xpress Predictor Tool (jxpredictor) tool as a starting point Use the type UKnn for connectors, sockets and test points in the .ckt file RAM banks use vectors or Opens Xpress Large bus-structured boards with a lot of common signal lines need unique pins for detectors - unused or no connection signal pins are ideal for this Device models you want to test should contain at least a head section in the .dts defining VCC, GND, INs, OUTs - don't forget those unused signal pins Combine Junction Xpress with the other techniques - Opens Xpress and Digital ICT Multiple approved vendors of devices may require multiple POLEARNs Hybrid and Analog are better suited for Opens Xpress Leadless devices like BGAs, COB, etc. use Junction Xpress Devices that have a Ground or Power plane can use Junction Xpress Available as of GR228X Software release 3.3.1 and currently available on the web. Evaluates usability of Junction Xpress test technique Views the .idd or .idx file NOTE: Because the predictor tool only examines the .idd or .idx file for a board and does not make electrical measurements on an actual board, its conclusions will in some cases differ from those of the tester-based POLEARN command. jxpredict idd_file > report_file idd_file typically .idd or .idx Report file defaults to screen unless “>“ redirected to a file report_file jxpredict boardcpu.idx > boardcpu_jx.rpt Location of Junction Xpress Predictor Windows NT c:\genrad\228X\exe Opens Xpress Overview After completing this module, you should be able to: Determine the GR228X hardware and software required to use the Opens Xpress tool. Identify the fixturing requirements. Determine which tool (Opens Xpress, Cap Xpress, or Orient Xpress) will provide the most effective test coverage for your 57 needs. ICA-only based systems contain an ICA module but not an AFTM module. With software release version 3.2.0 (or greater), Opens Xpress, Cap Xpress, and Orient Xpress supports ICA-only systems. ICA - only based systems require Opens Fixture - OFM hardware to conduct Opens Xpress, Cap Xpress, or Orient Xpress tests. ICA-only based systems can include the following models: GR2280, GR2281, GR2283, GR2284, GR2285, GR2286, GR2287, GR2287L and GR2289. TEST XPRESS supports AFTM - based systems. AFTM-based systems can use either Opens Fixture - OFM hardware or Opens Fixture - Buffer/MUX hardware to conduct Opens Xpress, Cap Xpress, or Orient Xpress tests. AFTM-based systems can include the following models: GR2280, GR2281, GR2282, GR2283, GR2284, GR2285, GR2286, GR2287, and GR2289. 58 The ATM - based system uses the following modules: Analog MUX Module (AMM) Analog Test Module (ATM) Analog Peripheral Module (APM) Opens Xpress, Cap Xpress, or Orient Xpress supports ATM - based systems. ATM based system can use either the Opens Fixture Module hardware or the buffer/mux hardware (Buffer/MUX) to conduct Opens Xpress, Cap Xpress, or Orient Xpress tests. ATM-based systems can include the following models: GR2281A and GR2287A. 59 Combines multiplexer and buffer boards Each module services 32 probes All electronics reside on overclamp Small footprint (2.5” x 6.5”) Daisy chain interconnect simple expansion Single thirty pin transfer connector Expandable to 192 OX probes Signal processing enhancements - Modified high pass filter - Added low pass filter - Auxiliary active guard connection Probe signal path verification Rotary switch board ID (no jumpers) Single +5V power supply A test fixture that includes Opens Xpress hardware requires that you verify both the fixture's bed-of-nails and Opens Xpress wiring. Verify the wiring and operation of the Opens Xpress portion of the fixture by: Ensuring the Fixture Grounding Rules are satisfied. Verifying agreement between the .dpr file and the fixture. Using LOCPROBE. Debugging the Opens Fixture, if necessary. 60 1. An AC signal is injected into a lead frame of an IC pin / node on an unpowered printed-circuit board. 2. The capacitive coupled voltage at the plate above the IC is buffered, amplified, sampled and channeled into the AFTM's or ICA's sampling DVM. 3. The quality of the pin connection response is processed (DFT) and converted into a value that is compared against precalculated threshold limits. 61 Opens Xpress tests for open pins by applying an AC signal to a node on an unpowered printed-circuit board and measuring the voltage at the plate above the IC. The high and low thresholds are calculated by using the average measured voltage. When a node is connected to a single lead of the IC, the voltage detected is 400 mV or higher. For IC pins that are not connected, the measurement is usually between 2 and 3 mV. • Source Applied to Outer Electrode • Guard Applied to Inner Electrode • Large Signal Value Measured • Source Applied to Inner Electrode • Guard Applied to Outer Electrode • Guard Shields Signal from Sensor • Low Signal Value Measured • Large Characteristic Difference Between Pins WE0006- Axial Can 62 Drop Chip Uses Existing Opens Xpress Probes Components with Multiple Vcc or Gnd Pins Determines Patterns of Rotation Orientation tests for an IC use the principle that if an IC is misoriented such that a VCC or GND pin on the IC is rotated into a testable pin location, the amplitude measured by Opens Xpress for that pin will vary significantly from the learned data because of the internal construction of the IC. The IC orientation test performs an algorithm on those testable pins that would have a VCC or GND pin in their position if the IC were mis-rotated 90, 180, or 270 degrees clockwise. SCO UNIX or NT system with GR228X Software Release 3.2.0 or greater Instruments used are either AFTM, ICA, or ATM Scanner Subsystem ICT fixture requires overclamp, OX probes and special hardware Note: VMS systems with an AFTM can use Opens Xpress to test ICs, connectors, and caps. However VMS systems do not support Cap Xpress or Orient Xpress. Most Opens Xpress problems are fixture related 63 Mis-application of probes Premature failure of probes Inconsistent Opens Xpress implementation by vendor Wiring errors Incomplete diagnostics Electrostatic coupling without proper shielding TEST XPRESS Test Program Development After completing this module, you should be able to: Describe the purpose and content of the four data files that provide TEST XPRESS Tools data to the test program. Describe the TEST XPRESS Tools test program development process. Use the TEST XPRESS Tools procedure to assist you in developing a TEST XPRESS Tools test set. Generate a TEST XPRESS Tools test program. 64 The four data files that provide TEST XPRESS Tools data to the test program are: Device Probe Information (.dpi), Device Probe Report (.dpr), Pin Opens Data (.pod), and POLEARN - generated Coverage Report. Contains data used to produce the .dpr file. Manually created using a text editor. Lists the devices to be tested and describes the interconnections between the Opens Probes and the system for Opens Xpress, Cap Xpress, and Orient Xpress. Produced using the .dpi file as input during NAIL_ASSIGNMENT. The Run-Time-System (RTS) can update the .dpr file when you use PODEBUG mode. Contains the Opens test data generated by POLEARN. This data is later used by the test program to test other UUTs. Contains an analysis of the test results. 65 To develop a TEST XPRESS Tools test set for a new board or to add a TEST XPRESS Tools test to an existing board's test set 1 Create a .dpi file. This input file identifies each IC that TEST XPRESS Tools will test. 2 Select the TEST XPRESS option on the ATG monitor page. 3 Run NAIL_ASSIGNMENT or XPRESS_NAIL. 4 Obtain a fixture with special Opens Xpress hardware or modify an existing fixture using GenRad guidelines for assistance. Note that this step does not apply to Junction Xpress. 5 Learn and verify the TEST XPRESS tests using the Run-Time System (RTS) debug mode. Just specify devices to be tested. /* Component Probe */ J1; U6; U8; C52; U6 JX; 66 These optional .dpi file statements are normally used when adding Opens Xpress to an existing test program. HARDWARE=[ ] MEAS_CONN=[ ] AFTM_SLOT=n AFTM_COMPATIBLE AFTM_SIGNAL_NAIL, AFTM_RTN_NAIL SCANNED_SIGNAL_NAIL, SCANNED_RTN_NAIL GUARD, GUARDGND PIO_USED VPLUS_NAIL, VMINUS_NAIL PRBGND_NAIL VCCGRD_RLY, GNDGRD_RLY Indicates which type of fixture hardware will be used so that the wiring description in the .dpr file will be done correctly. 67 HARDWARE=OFM; (default) or HARDWARE=MUX; Argument OFM MUX Description Indicates OFM hardware will be used. Use OFM hardware on ICA systems with no AFTM, which is also compatible with GR2281A and GR2287A test systems as well as AFTM systems. Indicates the Buffer/ MUX board hardware will be used. The MUX hardware can only be used on GR2281A or GR2287A test systems and systems having an AFTM board. Indicates how the measurement signal from the fixture hardware will be connected to the tester interface. MEAS_CONN=SCANNED; (default) or MEAS_CONN=DIRECT; SCANNED indicates the measurement signal and its associated return pin are connected to pin board scanner nails. The scanning system will route the measurement signal to the AC voltmeter during the test. SCANNED must be used on ICA systems with no AFTM. SCANNED is compatible with GR2281A and GR2287A test systems as well as AFTM systems. SCANNED connections do not require the AFTM position to be in a fixed slot unless there is direct wiring to HFNAILS in the fixture to test oscillators and crystals. This reduces the need for cable connections from the fixture to modified fixture adapter plates. If MEAS_CONN=SCANNED and the configuration is... Then... AFTM-Only Keywords in the .dpi file relating to the AFTM, such as AFTM_COMPATIBLE and AFTM_SLOT are ignored. AFTM and ICA Measurement signal will be routed to the ICA. The ICA will also provide the AC source and the AFTM is not used. GR2282 system MEAS_CONN=DIRECT must be stated in the .dpi file. This is critical because 68 SCANNED is the default. DIRECT can only be used on GR2281A and GR2287A test systems or systems having an AFTM board. If MEAS_CONN=DIRECT and the... Then connections are made Configuration is ATM-based To CSYNC7 and CSYNC8 pins in slot 2 AFTM_COMPATIBLE option is used,and the configuration is AFTM/ICAbased or AFTM/Meas-based: In the fixture from the AFTM slot to the CSYNC7X and CSYNC8X pins in slot 2 AFTM_COMPATIBLE option is not used, and the configuration is AFTM/ICA-based or AFTM/Meas-based: Directly to the AFTM slot The n argument is the slot where AFTM resides. Available for AFTM-based systems only. Include the AFTM_COMPATIBLE keywords in the .dpi file to provide fixture compatibility across all test systems. If MEAS_CONN=SCANNED, the measurement signal output from the Opens Xpress fixture and its associated return signal are wired to pin board scanner nails. If MEAS_CONN=DIRECT, an explicit statement must be included in the .dpi file, and the test system must be an ICA system or a GR2281A or GR2287A tester. The measurement signal is wired to pin 02-A02 and the measurement signal return is wired to pin 02-A03 at slot 2 of the tester receiver. On GR2281A and GR2287A systems, these pins are the dedicated Opens Xpress connections that are switched by the AMM board to the AC voltmeter. These pins are known on other GR228X systems as CSYNC8 and CSYNC7 respectively. When wired for Opens Xpress compatibility, CSYNC7 and CSYNC8 cannot be used as clock sync pins. Causes the device probe report to connect the opens MUX board to the AFTM by way of the AMM connections on slot 2. Alerts nail assignments to create the .dpr file wire list to support fixture wiring that is compatible with both AFTM and ATM based testers. Used in the device probe input file (.dpi) with the keyword AFTM_SLOT=n. /*---------------------------------------------------------This dpi creates wiring for the OFM fixture hardware. The resulting fixture will be compatible on ATM based systems and testers with an AFTM in slot14. The hardware option defaults to OFM. Component U8 will be tested with both Opens and Junction Xpress. 69 ----------------------------------------------------------*/ /* Component Probe */ U6 4; /* Opens Xpress - Assign Channel 4 to U6 */ U8; /* Opens Xpress - Leave channel unassigned */ U8 JX; /* Junction Xpress */ C52; /* Cap Xpress */ VPLUS_NAIL=1210; VMINUS_NAIL=1217; /* Not Used - OFM produces its own -5V supply */ MEAS_CONN=DIRECT; /* Routes signal wires directly to HF nails */ GUARD=1010; GUARDGND=1026; PRBGND_NAIL=900; SCANNED_SIGNAL_NAIL=916; /* Not Used because the connection is DIRECT */ SCANNED_RTN_NAIL=924; /* Not Used because the connection is DIRECT */ VCCGRD_RLY=1; GNDGRD_RLY=4; AFTM_COMPATIBLE; /* Causes Jumpers from CS7X & CS8X to HF nails */ AFTM_SLOT=14; AFTM_SIGNAL_NAIL=3; /* Applies because connection is DIRECT - Use HF3 */ AFTM_RTN_NAIL=4; /* Applies because connection is DIRECT - Use HF4*/ PIO_USED=2,4,6; /* Indicate not to use TDR2, TDR4, and TDR6*/ /* NOTE: Only the minimum of a list of components to be tested is required. Settings will default to OFM and SCANNED. If Junction Xpress tests are to be performed on non-ICA systems, the AFTM_SLOT must also be specified.*/ 已到页(PDF) 70